Theoretical analysis and modeling for nanoelectronics https://t.co/PsFJzoJgC8 #papers #feedly

Theoretical analysis and modeling for nanoelectronics https://t.co/PsFJzoJgC8 #papers #feedly

— Wladek Grabinski (@wladek60) October 15, 2016

from Twitter https://twitter.com/wladek60

October 15, 2016 at 10:00PM
via IFTTT

FOSDEM 2017 EDA Devroom Call for Participation

FOSDEM 2017 Electronic Design Automation Devroom
Call for Participation

This is the call for participation in the FOSDEM 2017 devroom on Free/Open Source Software (FOSS) Electronic Design Automation (EDA) tools, to be held on Sunday 5 February 2017 in Brussels, Belgium. We are looking for contributions under the form of talks and tutorials covering the following main topics:

• Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
• Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce, GHDL, Icarus and Verilator)
• Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen) and HDL synthesis tools (e.g.Yosys)
• Inter-project opportunities for collaboration

We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS EDA developments, share knowledge and identify opportunities to collaborate on development tasks. Have a look at last year's event for a taste of what the EDA devroom is about.

The submission process
Please submit your proposals at 

https://penta.fosdem.org/submission/FOSDEM17 

before 1 December 2016.

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself under Person -> Description -> Abstract. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "Electronic Design Automation (EDA) devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.

Important dates

• 1 December 2016: deadline for submission of proposals
• 11 December 2016: announcement of final schedule
• 5 February 2017: devroom day

Recordings
The FOSDEM organisers hope to be able to live-stream and record all the talks. The recordings will be published under the same licence as all FOSDEM content (CC-BY). Only presentations will be recorded, not informal discussions and whatever happens during the lunch break. By agreeing to present at FOSDEM, you automatically give permission to be recorded. The organisers will agree to make exceptions but only for exceptional and well-reasoned cases.
Mailing list

Feel free to subscribe to the mailing list of the EDA devroom to submit ideas, ask questions and generally discuss about the event.

Spread the word!
This is the third EDA devroom at FOSDEM. The first two were very well received. Let's make sure as many projects and developers as possible are present. Thanks!

[call for papers] 1st EDTM 2017

EDTM Call for Papers 

Submission deadline: November 4th, 2016

Camera ready, one page text and one page figures

1st EDTM 2017

At Toyama International Conference Center, Toyama, Japan

February 28th to March 2nd, 2017

Why EDTM has been started: System performance continues to grow, even though device scaling is saturated. Based on strong manufacturing technologies, Asia has strong potential to take an initiative for system integration. Deep-dive discussions among technical communities on materials, processes, and devices are aimed to accelerate manufacturing innovations through this forum.

1. Technical sessions

EDTM 2017 and beyond will have a strong specific technical focus, and this year’s focus being on devices and process technologies for advanced applications, IoE (Internet of Everything) and related low-power devices, advanced memories, sensors, actuators, MEMS, bio.-chips, passive devices, and all types of (exploratory) devices related to advance applications and IoE. Papers/Posters on materials and processes for enabling above-menHoned devices building in heterogeneous integration such as 2.1, 2.5 and 3D structures using wafer-level packaging process (e.g.) are of great focus. EDTM aims for highest quality, and all papers accepted would be subject to IEEE-EDS standard review processes and conference publishing guidelines. Accepted and presented papers will be published in EDTM proceedings. A selected number of high impact EDTM papers would be invited for the consideration of publication in the IEEE Journal of Electron Devices Society (J- EDS) as extended version of EDTM conference papers following the IEEE publication policy and J-EDS author-guidelines.

2. Education

• Tutorials: We will provide both the basic and advanced programs. Basic program will be presented in local language.
• Poster sessions: Primarily intended for young engineers and students. The best poster will be awarded in the conference.
• Short courses: Will bring high level programs.

3. Exhibition

Given the strong semiconductor manufacturing base in Asia, we intend to offer exhibits that will demonstrate products and technology. All of the exhibitors will have an opportunity to offer technical insight and share their knowhow. Moreover, we hope to offer Forum Making Session to engage and allow deeper discussions between device, material, and equipment engineers and technologists.

Papers in the following areas are requested by Subcommittee on:

• Devices and Manufacturing for “Cloud and Edge”
• Packaging and Manufacturing for “Cloud and Edge”
• Process, Tools, and Manufacturing
• Semiconductor Materials
• Reliability & Modeling (including compact/SPICE)

[read more...]

IEDM 2016 Session 7: Modeling and Simulation Advanced Numerical and Compact Models

IEDM 2016 Session 7

Modeling and Simulation Advanced Numerical and Compact Models

Monday, December 5, 1:30 p.m. Continental Ballroom 7-9 

Co-Chairs: Denis Rideau, STMicroelectronics 

Xing Zhou, Nanyang Technological University

1:35 PM 

7.1 A Novel Synthesis of Rent's Rule and Effective-Media Theory Predicts FEOL and BEOL Reliability of Self-Heated ICs, W. Ahn, H. Jiang, S.H. Shin and M. Alam, Purdue University

2:00 PM 

7.2 New Approach for Understanding "Random Device Physics" from Channel Percolation Perspectives: Statistical Simulations, Key Factors and Experimental Results, Z. Zhang, Z. Zhang, R. Wang, X. Jiang, S. Guo, Y. Wang, X. Wang*, B. Cheng*, A. Asenov* and R. Huang, Peking University, *Synopsys

2:25 PM 

7.3 Oxide-Based Analog Synapse: Physical Modeling, Experimental Characterization, and Optimization, B. Gao, H. Wu, J. Kang*, H, Yu**, H. Qian, Tsinghua University, *Peking University, **Southern University of Science and Technology

2:50 PM 

7.4 Extending the Bounds of Performance in E-mode p-channel GaN MOSHFETs, A. Kumar and M. De Souza, The University of Sheffield

3:15 PM 

7.5 NSP: Physical Compact Model for Stacked-planar and Vertical Gate-All-Around MOSFETs, O. Rozeau, S. Martinie, T. Poiroux, F. Triozon, S. Barraud, J. Lacord, Y.-M. Niquet*, C. Tabone, R. Coquand, E. Augendre, M. Vinet, O. Faynot, and J.-C. Barb, CEA-Leti, *CEA-INAC

3:40 PM 

7.6 A Physics-Based Compact Model for Material- and Operation-Oriented Switching Behaviors of CBRAM, Y. Zhao, J. Hu, P. Huang, F. Yuan*, Y. Chai*, X. Liu and J. Kang, Peking University, *The Hong Kong Polytechnic University

4:05 PM 

7.7 Multi-Domain Compact Modeling for GeSbTe-based Memory and Selector Devices and Simulation for Large-scale 3-D Cross-Point Memory Arrays, N. Xu, J. Wang, Y. Deng, Y. Lu, B. Fu, W. Choi, U. Monga*, J. Jeon*, J. Kim*, K.-H. Lee* and E. S. Jung*, Samsung Semiconductor Inc., *Samsung Electronics

[read more...]

Compound Semiconductor Technical Committee Meeting

SEMI® International Standards Program

Compound Semiconductor Technical Committee Meeting

Fraunhofer IISB, Schottkystrasse 10, D-91058 Erlangen, Germany

Thu 13th October 2016 14:00 to 16:30

Co-chairs:
• Dr. Arnd-Dietrich Weber, SiCrystal
• N.N. 

Agenda: European Compound Semiconductor Committee Meeting

Task Force meetings – tbd

14:00 Welcome and Self-Introductions all

14:05 SEMI Standards Overview and Legal Reminders SEMI Staff

14:10 Review of the minutes and action items from the previous meeting SEMI Staff

14:15 Task Force Reports (~5 minutes each)

SiC-Task Force A. Weber

Status M55 5-year review (doc 4689)

Status M81 5-year-review (doc 6015)

Contactless Capacitive Resistivity Task Force W. Jantz

14:30 Discussion and approval of doc 4689 (M55 review) for ballot A. Weber

15:00 5-Year-Review of published documents

5-year-review of M54 (Guide for semi-insulating GaAs parameters): discuss and

approve TFOF and SNARF U. Kretzer

dentification and discussion of action items all

15:30 Compound Materials Liaison Reports

North America

Japan SEMI Staff

15:45 Any Other Business / Questions A. Weber

16:00 Next Meetings

16:15 Adjourn 

Lectures on Electromagnetism https://t.co/nxi9p90Cte #papers

Lectures on Electromagnetism https://t.co/nxi9p90Cte #papers

— Wladek Grabinski (@wladek60) October 12, 2016

from Twitter https://twitter.com/wladek60

October 12, 2016 at 10:55AM
via IFTTT

[website] Open Circuit Design Software

Visit the Open Circuit Design Software to learn more about the major electronic design automation (EDA) tools hosted by Open Circuit Design:

• Magic, the VLSI layout editor, extraction, and DRC tool
• XCircuit, the circuit drawing and schematic capture tool
• IRSIM, the switch-level digital circuit simulator
• Netgen, the circuit netlist comparison (LVS) and netlist conversion tool
• Qrouter, the over-the-cell (sea-of-gates) detail router
• Qflow, a complete digital synthesis design flow using open-source software and open-source standard cell libraries
• PCB, the printed circuit board layout editor

[More about Open Circuit Design Software]

[paper] Well-Posed Models of Memristive Devices

Well-Posed Models of Memristive Devices

Tianshi Wang, Jaijeet Roychowdhury

(Submitted on 15 May 2016)

Existing compact models for memristive devices (including RRAM and CBRAM) all suffer from issues related to mathematical ill-posedness and/or improper implementation. This limits their value for simulation and design and in some cases, results in qualitatively unphysical predictions. We identify the causes of ill-posedness in these models. We then show how memristive devices in general can be modelled using only continuous/smooth primitives in such a way that they always respect physical bounds for filament length and also feature well-defined and correct DC behaviour. We show how to express these models properly in languages like Verilog-A and ModSpec (MATLAB). We apply these methods to correct previously published RRAM and memristor models and make them well posed. The result is a collection of memristor models that may be dubbed "simulation-ready", i.e., that feature the right physical characteristics and are suitable for robust and consistent simulation in DC, AC, transient, etc., analyses. We provide implementations of these models in both ModSpec/MATLAB and Verilog-A.

Subjects: Emerging Technologies (cs.ET); Computational Engineering, Finance, and Science (cs.CE)
Cite as: arXiv:1605.04897 [cs.ET]
(or arXiv:1605.04897v1 [cs.ET] for this version)

Eben Upton Founder, Raspberry Pi Foundation at ARM TechCon

Hear Big Names Deliver Big Ideas Attend 6 inspirational keynotes with 1 free expo pass [get pass]

ARM TechCon is proud to announce its full keynote lineup for 2016. From the founder of Raspberry Pi to the CEO of SoftBank (and his take on its 32 billion dollar ARM acquisition), these presentations feature the leaders impacting your industry’s future. Hear them all when you register for a free expo pass.

Eben Upton Founder, Raspberry Pi Foundation

Charlie Miller Senior Security Engineer, Uber Advanced Technologies Center

Masayoshi Son CEO and Chairman of the Board, SoftBank Group Corp.

Mike Muller CTO, ARM

Jon Masters Chief ARM Architect and Technical Lead for RHEL Server, Red Hat

Simon Segars CEO, ARM

100 reads: Compact Device Modeling using Verilog-AMS and ADMS

Article reached 100 reads: Compact device modeling using Verilog-AMS and ADMS
Lemaitre L · Grabiński W · McAndrew C
Abstract: This paper shows how high level language as Verily-AMS can serve as support for compact modeling development of new devices. First section gives a full Verily-AMS code of a simplified bipolar transistor. Each part of the code is carefully examined and explained. Second section compared different implementations if the simplified bipolar transistor in different spice simulators. ADMS, an open-source tool developed at Motorola, performs the implementations from Verily-AMS to simulators. Third sections concludes the paper by describing by implementation of the EKV model into ADS using the compact model interface provided by Agilent.
View publication
12 citations 107 reads

SourceForge Project: FreeCAD

FreeCAD is a general purpose feature-based, parametric 3D modeler for CAD, MCAD, CAx, CAE and PLM, aimed directly at mechanical engineering and product design but also fits a wider range of uses in engineering, such as architecture or other engineering specialties. It is 100% Open Source and extremely modular, allowing for very advanced extension and customization.

FreeCAD is based on OpenCasCade, a powerful geometry kernel, features an Open Inventor-compliant 3D scene representation model provided by the Coin 3D library, and a broad Python API. The interface is built with Qt. FreeCAD runs exactly the same way on Windows, Mac OSX and Linux platforms. [Download FreeCAD]

The History of ARM

Free Copy of Mobile Unleashed: The History of ARM!
by Daniel Nenni Published on 10-04-2016

As most of you know SemiWiki published a book which is a really nice history of ARM. We have received many compliments on it and we are very proud. As a thank you to all SemiWiki members I would like to offer a free electronic version of the book (PDF).

Only registered SemiWiki members can access this wiki so if you are not already a member please join as  guest: https://www.semiwiki.com/forum/register.php

A Compact Model of Drain Current for GaN HEMTs Based on 2-DEG Charge Linearization

N. Karumuri; G. Dutta; N. DasGupta; A. DasGupta, "A Compact Model of Drain Current for GaN HEMTs Based on 2-DEG Charge Linearization," in IEEE Transactions on Electron Devices , vol.PP, no.99, pp.1-7 doi: 10.1109/TED.2016.2605130

Abstract: A physics-based simple and accurate compact model of drain current for GaN-based high electron mobility transistors (HEMTs) is presented. The model is developed using analytical relations for charges in the 2-D electron gas and barrier layer. For the first time, a simple charge linearization approach has been used for GaN-based HEMTs. The access regions are accurately modeled using transistors. The model is rigorously validated over a wide range of geometries and parameters for AlGaN/GaN and AlInN/GaN HEMTs. The model also passes the DC Gummel symmetry test.

keywords: {Computational modeling; Electric potential; HEMTs; Integrated circuit modeling; MODFETs; Threshold voltage;2-D electron gas (2-DEG) charge;AlGaN/GaN;AlInN/GaN;GaN high electron mobility transistor (HEMT); Gummel symmetry; SPICE model.;charge linearization; charge-based; compact model;drain current},

[read more...]

Prof. Andrzej Strojwas receives 2016 Kaufman Award

The Dictates of Fate: Andrzej Strojwas receives 2016 Kaufman Award
as of Sept. 29, 2016 by Peggy Aycinena

Dr. Andrzej J. Strojwas, professor of Electrical and Computer Engineering at Carnegie Mellon University, has been named recipient of the 2016 Phil Kaufman Award for Distinguished Contributions to Electronic System Design.

Interestingly, this is the first year that the Kaufman award is being presented for contributions to Electronic System Design, not EDA. Very appropriate given that Strojwas’ contributions are in manufacturing and not design. Prof. Stojwas is CTO at PDF Solutions, which per company CEO John Kibarian has never been an EDA company. And with Kibarian serving as co-chair of the ESD Alliance, the organization formerly known as EDAC has now fully embraced its role across the entirety of electronic system design.

Besides this nod to EDAC’s ongoing evolution, the larger implications in CEDA and the ESD Alliance naming Andrzej Strojwas as this year’s Kaufman recipient are profound: The problems associated with electronic systems are not so much in the design these days, but in the extraordinary difficulties associated with manufacturing those designs. It’s really tough, as you all know, when the structures being manufactured are smaller than the wavelengths of light used to etch them.

Which bring us back to Dr. Strojwas. He has been CTO at PDF for 20 years. Back in the last century/millennium, the problems of manufacturing below 193 nanometers could only have been guessed at, yet the company was already working on the intriguing issues of capturing post-manufacturing data and somehow packaging it up to make it useful: How does the semiconductor supply chain glean vital information about the vagaries of manufacturing a real chip and send it back up to the designers so they can learn from the reality when they put pen to paper to design the next hypothetical?

This engineering of the engineering demands scientific curiosity, steely eyed attitudes towards the realities of physics and material science, and a large dollop of business savvy to navigate between the needs and demands of the foundries and the needs and demands of the designers. Let’s allow Dr. Strojwas to take it from here. We spoke by phone this week after his award was announced. 

[read more...]

Angstrem is developing new radiation-resistant microchips

as of August 16, 2016 by VICTORIA ZAVYALOVA, RBTH

Angstrem is planning to export microchips to India's aerospace sector. This is a major turning point for the Russian microelectronics industry, which until recently was almost entirely dependent on imports.
The Russian company Angstrem is completing the development of new radiation-resistant microchips for use in outer space. In September the manufacturer is planning to begin deliveries to India, its first major export market. This initial delivery will total about 10,000 microchips, and the contract is estimated at $200,000.
"While India has a full-fledged space program, the country does not have a complete technological cycle for the production of spacecraft and launch vehicles," said Vitali Aryshev, Angstrem's director of communications, when explaining the choice of this market. [read more...]

Power Semiconductor Devices and Smart Power IC Technologies CFP https://t.co/P8bWJZLgrw #papers #feedly

Power Semiconductor Devices and Smart Power IC Technologies CFP https://t.co/P8bWJZLgrw #papers #feedly

— Wladek Grabinski (@wladek60) October 1, 2016

from Twitter https://twitter.com/wladek60

October 01, 2016 at 02:29PM
via IFTTT

Good chip engineers are hard to find https://t.co/qdMkL3l1fe #semi #papers

Good chip engineers are hard to find https://t.co/qdMkL3l1fe #semi #papers

— Wladek Grabinski (@wladek60) September 29, 2016

from Twitter https://twitter.com/wladek60

September 29, 2016 at 03:01PM
via IFTTT

Insight into Lateral Band-to-Band-Tunneling in Nanowire Junctionless FETs https://t.co/cOfNerRskb #papers #feedly

Insight into Lateral Band-to-Band-Tunneling in Nanowire Junctionless FETs https://t.co/cOfNerRskb #papers #feedly

— Wladek Grabinski (@wladek60) September 25, 2016

from Twitter https://twitter.com/wladek60

September 25, 2016 at 02:06PM
via IFTTT

Universal Compact Model for Organic Solar Cell https://t.co/canYf4B4V4 #papers #feedly

Universal Compact Model for Organic Solar Cell https://t.co/canYf4B4V4 #papers #feedly

— Wladek Grabinski (@wladek60) September 25, 2016

from Twitter https://twitter.com/wladek60

September 25, 2016 at 09:44AM
via IFTTT

#Europe proposes #copyright reform to help scientists mine #research #papers https://t.co/ZTLo9VJqZ0

#Europe proposes #copyright reform to help scientists mine #research #papers https://t.co/ZTLo9VJqZ0

— Wladek Grabinski (@wladek60) September 20, 2016

from Twitter https://twitter.com/wladek60

September 20, 2016 at 03:34PM
via IFTTT

ASAP7: A 7-nm finFET predictive process design kit https://t.co/KesQkb5g4l #papers

ASAP7: A 7-nm finFET predictive process design kit https://t.co/KesQkb5g4l #papers

— Wladek Grabinski (@wladek60) September 19, 2016

from Twitter https://twitter.com/wladek60

September 19, 2016 at 03:16PM
via IFTTT

Numerical modeling of process parameters on RF metrics in FinFETs, junctionless, and gate-all-around devices https://t.co/93HUZiRtR3 #papers

Numerical modeling of process parameters on RF metrics in FinFETs, junctionless, and gate-all-around devices https://t.co/93HUZiRtR3 #papers

— Wladek Grabinski (@wladek60) September 16, 2016

from Twitter https://twitter.com/wladek60

September 16, 2016 at 12:46PM
via IFTTT

Guest editorial for the special issue on linear and nonlinear modeling of GaN transistors and circuits https://t.co/w0gPdKDbep #papers

Guest editorial for the special issue on linear and nonlinear modeling of GaN transistors and circuits https://t.co/w0gPdKDbep #papers

— Wladek Grabinski (@wladek60) September 7, 2016

from Twitter https://twitter.com/wladek60

September 07, 2016 at 04:01PM
via IFTTT

Europe announces that all scientific #papers should be #free by #2020 https://t.co/yVH9ZM7Wus #software #feedly

Europe announces that all scientific #papers should be #free by #2020 https://t.co/yVH9ZM7Wus #software #feedly

— Wladek Grabinski (@wladek60) September 6, 2016

from Twitter https://twitter.com/wladek60

September 06, 2016 at 06:35PM
via IFTTT

Carbon nanotube transistors finally outperform silicon and gallium arsenide field-effect transistors https://t.co/mSGTEzOWGo #papers

Carbon nanotube transistors finally outperform silicon and gallium arsenide field-effect transistors https://t.co/mSGTEzOWGo #papers

— Wladek Grabinski (@wladek60) September 3, 2016

from Twitter https://twitter.com/wladek60

September 03, 2016 at 04:11PM
via IFTTT

MNA-MAT : An easy-to-use MATLAB tool for SPICE netlist simulation https://t.co/SwPNcF6CCr #spice #feedly #papers

MNA-MAT : An easy-to-use MATLAB tool for SPICE netlist simulation https://t.co/SwPNcF6CCr #spice #feedly #papers

— Wladek Grabinski (@wladek60) September 2, 2016

from Twitter https://twitter.com/wladek60

September 03, 2016 at 12:30AM
via IFTTT

Implementation of TFET SPICE Model for Ultra-Low Power Circuit Analysis https://t.co/z6YQhzAkIv #papers #feedly

Implementation of TFET SPICE Model for Ultra-Low Power Circuit Analysis https://t.co/z6YQhzAkIv #papers #feedly

— Wladek Grabinski (@wladek60) August 30, 2016

from Twitter https://twitter.com/wladek60

August 30, 2016 at 11:06PM
via IFTTT

Modeling Early Breakdown Failures of Gate Oxide in SiC Power MOSFETs https://t.co/gwB6cmDMPB #papers #feedly

Modeling Early Breakdown Failures of Gate Oxide in SiC Power MOSFETs https://t.co/gwB6cmDMPB #papers #feedly

— Wladek Grabinski (@wladek60) August 26, 2016

from Twitter https://twitter.com/wladek60

August 26, 2016 at 12:39PM
via IFTTT

#Write beautiful #LaTeX #papers in an easy way. https://t.co/7HkkbDED7f

#Write beautiful #LaTeX #papers in an easy way. https://t.co/7HkkbDED7f

— Wladek Grabinski (@wladek60) August 25, 2016

from Twitter https://twitter.com/wladek60

August 25, 2016 at 10:56AM
via IFTTT

#Analog #DNA #circuit does math in a test tube https://t.co/iNOWaqkBMO #tech #feedly #papers

#Analog #DNA #circuit does math in a test tube https://t.co/iNOWaqkBMO #tech #feedly #papers

— Wladek Grabinski (@wladek60) August 24, 2016

from Twitter https://twitter.com/wladek60

August 24, 2016 at 08:46PM
via IFTTT

2-D Threshold Voltage Model for the Double-Gate p-n-p-n TFET With Localized Charges https://t.co/oyhQhOSEzQ #papers #feedly

2-D Threshold Voltage Model for the Double-Gate p-n-p-n TFET With Localized Charges https://t.co/oyhQhOSEzQ #papers #feedly

— Wladek Grabinski (@wladek60) August 24, 2016

from Twitter https://twitter.com/wladek60

August 24, 2016 at 12:39PM
via IFTTT

Books You Should Read: Basic Electronics https://t.co/igihHzx3XQ #papers

Books You Should Read: Basic Electronics https://t.co/igihHzx3XQ #papers

— Wladek Grabinski (@wladek60) August 19, 2016

from Twitter https://twitter.com/wladek60

August 19, 2016 at 09:37PM
via IFTTT

ECSCRM 2016 Tutorial Day Announcement

ECSCRM 2016
Announcement of Tutorial Day
Sept.25, 2016, Halkidiki, GREECE

The 11th European Conference on Silicon Carbide and Related Materials (ECSCRM) will be held on Sept. 25-29 in Halkidiki, Greece

Early Registration: August 20, 2016

Late Abstract Submission: August 23, 2016

Please see the conference website, http://ecscrm2016.org/

We are very happy to announce that a SiC MOSFET Tutorial Day is planned for Sunday, Sept.25, as a satellite event of ECSCRM 2016:

Tutorial Day Title: Learn how to develop your SiC MOSFET
in one day!

The main objective of the Tutorial is to introduce the audience to what is arguably the hottest topic in SiC devices: the technology of SiC MOSFETs. The Tutorial is primarily intended for PhD students working on SiC and possessing a solid technical background in semiconductor devices, as well as for semiconductor technology professionals who want to better familiarize themselves in this subject. Its concept/setup is to deliver all key information that will allow the audience to understand most of the content of any paper dedicated to SiC MOSFETs. The topics to be presented and the corresponding speakers are:

1. Material for SiC MOSFET fabrication (bulk/epitaxial growth, selection criteria, defects, screening methods)
   Prof. T. Kimoto (Kyoto University, Japan)
2. Physics and technology of SiO2/SiC interface
   Dr. Kevin Matocha (Monolith, USA)
3. Other MOSFET processing (ohmic contacts, implantation, passivation, specific issues related to device geometry,…)
   Dr. Victor Veliadis (PowerAmerica/NCSU, USA)
4. SiC MOSFET device physics and design (operation principles, charge model, TCAD simulation)
   Prof. J. Cooper (Purdue University, USA)
5. SiC MOSFET electrical static and dynamic characterization, electrical stresses, device reliability
   Prof. A. Castellazzi (Nottingham University, UK)
6. SiC MOSFET as circuit components – targeted applications
   Dr. Ljubisa Stevanovic (GE, USA)
7. Summarizing remarks (evolution of SiC MOSFETs – main open points)
   (under confirmation)

Please note there is separate registration to attend the tutorial. The registration fee is €60 for ECSCRM 2016 participants, and €200 for non-participants. The registration fee for students* is €60, regardless of ECSCRM 2016 registration. The fee covers lectures, tutorial materials, as well as lunch and coffee breaks on tutorial day.

The organizing committee of ECSCRM 2016 Tutorial Day

• Matthias Bucher (Technical University of Crete, TUC, Greece)
• Peter Friedrichs (Infineon, Germany)
• Konstantin Vasilevskiy (Newcastle University, UK)
• Konstantinos Zekentes (FORTH, Greece)

* Student status will be recognized only to PhD and Master students. Post-docs are kindly requested to register as regular participants. Students must provide evidence of their status by sending a student certificate or a copy of a valid student ID to the conference secretariat upon registration.

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at https://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/d/optout.

History Of The Diode https://t.co/fHiuWidp8o #todo #feedly #papers

History Of The Diode https://t.co/fHiuWidp8o #todo #feedly #papers

— Wladek Grabinski (@wladek60) August 15, 2016

from Twitter https://twitter.com/wladek60

August 15, 2016 at 11:56PM
via IFTTT

Effect of gate-length downscaling on the analog/RF and linearity performance of InAs NW TFET https://t.co/If4CzeK8uI #papers #feedly

Effect of gate-length downscaling on the analog/RF and linearity performance of InAs NW TFET https://t.co/If4CzeK8uI #papers #feedly

— Wladek Grabinski (@wladek60) August 15, 2016

from Twitter https://twitter.com/wladek60

August 15, 2016 at 11:45AM
via IFTTT

[mos-ak] [final program] MOS-AK ESSDERC/ESSCIRC Workshop; Lausanne September 12, 2016

 MOS-AK ESSDERC/ESSCIRC Workshop  

   Lausanne September 12, 2016 
    Final Workshop Program

 Together with International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and local workshop coordinator Jean-Michel Sallese, EPFL (CH) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 14th consecutive MOS-AK ESSDERC/ESSCIRC Workshop which will be held at Swisstech Convention Centre in Lausanne on September 12, 2016. The MOS-AK workshop is organized with aim to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Venue:

Swisstech Convention Centre EPFL                                        
Route Louis-Favre 2
CH-1024 Ecublens

Online Workshop Program 

http://www.mos-ak.org/lausanne_2016/

Online Workshop Registration:

http://esscirc-essderc2016.epfl.ch/registration
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at https://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/d/optout.

Flashy Wearable Patch Sees Under Your Skin https://t.co/k4lQcw8gsd #tech #feedly #papers #openinnowation

Flashy Wearable Patch Sees Under Your Skin https://t.co/k4lQcw8gsd #tech #feedly #papers #openinnowation

— Wladek Grabinski (@wladek60) August 3, 2016

from Twitter https://twitter.com/wladek60

August 03, 2016 at 10:49PM
via IFTTT

Retrotechtacular: Old Transistors https://t.co/unvIp5rBPS #todo #feedly #papers

Retrotechtacular: Old Transistors https://t.co/unvIp5rBPS #todo #feedly #papers

— Wladek Grabinski (@wladek60) August 3, 2016

from Twitter https://twitter.com/wladek60

August 03, 2016 at 09:17PM
via IFTTT

H2020 SPICE is not #SPICE- Spintronic-Photonic Integrated Circuit platform for novel Electronics https://t.co/P9hYGPxjsd #papers

H2020 SPICE is not #SPICE- Spintronic-Photonic Integrated Circuit platform for novel Electronics https://t.co/P9hYGPxjsd #papers

— Wladek Grabinski (@wladek60) August 3, 2016

from Twitter https://twitter.com/wladek60

August 03, 2016 at 02:02PM
via IFTTT

In analog, we’re still pasting together #transistors and running #SPICE. What’s Holding Back #Analog? https://t.co/Um1VWwrKqP #papers

In analog, we’re still pasting together #transistors and running #SPICE. What’s Holding Back #Analog? https://t.co/Um1VWwrKqP #papers

— Wladek Grabinski (@wladek60) August 1, 2016

from Twitter https://twitter.com/wladek60

August 01, 2016 at 09:28AM
via IFTTT

Researchers develop ultrathin, transparent oxide #TFT for #wearable #display https://t.co/Z314WvUs3J #papers

Researchers develop ultrathin, transparent oxide #TFT for #wearable #display https://t.co/Z314WvUs3J #papers

— Wladek Grabinski (@wladek60) July 29, 2016

from Twitter https://twitter.com/wladek60

July 29, 2016 at 11:51PM
via IFTTT