4th International DevIC 2021 Conference

DevIC 2021

Conference Date: 19-20 May, 2021

(New date after Postponement due to COVID-19 and W.B. State General Election)

Click here to download the program Schedule of DevIC 2021

We are pleased to announce the upcoming 4th International Conference “2021 Devices for Integrated Circuit (DevIC)”, to be held at Kalyani Government Engineering College from March 24-25 May 19-20, 2021, organized by IEEE KGEC Student Branch Chapter in association with Department of ECE, KGEC and technically co-sponsored by IEEE EDS Kolkata Chapter. There will be keynote lectures, talks, tutorials, and oral presentations  by eminent researchers. We solicit original research and technical papers not published elsewhere.

DevIC 2021 Conference committee appeals ALL to contribute in West Bengal State Emergency Relief Fund and assist the State in prevention and control of situation arising out of unforeseen emergencies like COVID-19 (CORONA)

• IEEE EDS Kalyani Government Engineering College Student Branch Chapter has decided to contribute to the West Bengal State Emergency Relief Fund to combat the coronavirus outbreak.

• IEEE EDS Kalyani Government Engineering College Student Branch Chapter  thanks Dr. Wladek Grabinski (Senior IEEE EDS Member, MOS-AK (EU)) for coming forward to contribute to fight the Corona Virus outbreak.

Due to rapid increase in COVID affected people, request to Kindly join our hands and support us by donating to West Bengal State Emergency relief Fund

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• Donate in West Bengal State Emergency Relief Fund to collectively fight against unprecedented COVID-19 pandemic.

DevIC 2021 is appealing all the participants to help fight the pandemic and saving lives.

Click here to donate in West Bengal State Emergency Relief Fund

Due to COVID-19, the conference will be organized in the online mode. 

DevIC 2021 Conference Committee

DevIC 2021 Registration

DevIC 2021 Plenary Talk

Kalyani Government Engineering College (KGEC) Website

[paper] Well-Posed Models of Memristive Devices

Well-Posed Models of Memristive Devices

Tianshi Wang, Jaijeet Roychowdhury

(Submitted on 15 May 2016)

Existing compact models for memristive devices (including RRAM and CBRAM) all suffer from issues related to mathematical ill-posedness and/or improper implementation. This limits their value for simulation and design and in some cases, results in qualitatively unphysical predictions. We identify the causes of ill-posedness in these models. We then show how memristive devices in general can be modelled using only continuous/smooth primitives in such a way that they always respect physical bounds for filament length and also feature well-defined and correct DC behaviour. We show how to express these models properly in languages like Verilog-A and ModSpec (MATLAB). We apply these methods to correct previously published RRAM and memristor models and make them well posed. The result is a collection of memristor models that may be dubbed "simulation-ready", i.e., that feature the right physical characteristics and are suitable for robust and consistent simulation in DC, AC, transient, etc., analyses. We provide implementations of these models in both ModSpec/MATLAB and Verilog-A.

Subjects: Emerging Technologies (cs.ET); Computational Engineering, Finance, and Science (cs.CE)
Cite as: arXiv:1605.04897 [cs.ET]
(or arXiv:1605.04897v1 [cs.ET] for this version)