Aug 18, 2013

Semiconductor Device Characterization Engineer jobs

Indeed
Qualcomm  90 reviews - San Jose, CA
Interacts with other groups such as Design, Process, System, Reliability, and FA. 5+ years of related hands-on industrial experience....
Qualcomm - 5:25 AM
5+ years of related hands-on industrial design experience. Hands-on experience with device physics, device process, device characterization, and systems....
Qualcomm - 5:25 AM
IBM CORPORATION 1,821 reviews - Somers, NY
Possess working knowledge of semiconductor device development processes. Semiconductor Research and Development Process Improvement Engineer, IBM Corporation,...
New York Times - 8:27 AM

Aug 13, 2013

Fwd: 4 new Semiconductor Device Characterization Engineer jobs

Indeed

4 new jobs found
Knowledge of analog and mixed signal board level design including PCB layout guidelines a strong plus. Knowledge of both analog and digital video interface...
Intersil - 11:04 PM
GLOBALFOUNDRIES - Malta, NY
Technology related Bachelor's degree with 6 years experience ;. or Master's degree plus 5 years experience in process technology development area;....
GLOBALFOUNDRIES - 7:22 PM
Experience would be obtained through your educational level research and/or relevant job/internship experiences....
Intel - 2:45 PM
Quantum Solution - Sunnyvale, CA
Excellent proficiency of Cadence's custom IC design environment, analog/mixed signal circuit simulation (Spectre, Hspice, Ocean scripting, )....
Quantum Solution - 4:53 AM

Aug 8, 2013

[mos-ak] [Final Program] 11th MOS-AK ESSDERC ESSCIRC Workshop with the keynote speaker Larry Nagel

Together with Prof. Andrei Vladimirescu, R&D Scientific Coordinator, the Organizing Committee and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the 11th consecutive MOS-AK ESSDERC ESSCIRC Workshop on Sept. 20, 2013 in Bucharest (RO). The event will open next decade of enabling compact modeling R&D exchange.  

The final workshop program as well as all further details and updates are on-line: <http://www.mos-ak.org/bucharest/

- with regards - WG (for the MOS-AK/GSA Committee

MOS-AK Workshop Program

 9:00 - 12:00Morning Session - Chair: Prof. Andrei Vladimirescu, ISEP (F); UCB (USA)
O_1 Welcome and Workshop Opening
W. Grabinski
MOS-AK Group (EU)
T_2 SPICE - MOS-AK Keynote
Larry Nagel
Omega Enterprises Consulting (USA)
T_3 NGSPICE: recent progresses and future plans
Paolo Nenzi*, Francesco Lannutti*, Robert Larice**, Holger Vogt**, Dietmar Warning**
*DIET - Sapienza University of Roma (I), ** NGSPICE Development Team
T_4 KCL and Linear/NonLinear Separation in NGSPICE
Francesco Lannutti
DIET - Sapienza University of Roma (I) and NGSPICE Development Team

Coffee Break
T_5 Modeling Junction Less FETs
Jean-Michel Sallese, Farzan Jazaeri, Lucian Barbut
EPFL (CH)
T_6 HiSIM-Compact Modeling Framework
Hans Juergen Mattausch
Uni. Hiroshima (J)
P_7 The Correct Account of Nonzero Differential Conductance in the Saturation Regime in the MOSFET Compact Model
Valentin Turin*, Gennady Zebrev**, Sergey Makarov***, Benjamin Iniguez****, and Michael Shur*****
*State University-ESPC (RU),**MEPHI (RU),***SYMICA Inc (RU),****URV (SP),*****RPI (USA)
12:00 -13:00
Lunch Break
13:00 -16:00
Afternoon Session - Chair: W. Grabinski, MOS-AK Group
T_8 State of the Art Modeling of Passive CMOS Components
Bernd Landgraf 
Infineon Technologies (A)
T_9 Compact I-V Model of Amorphous Oxide TFTs
Benjamin Iniguez*,Alejandra Castro-Carranza* , Muthupandian Cheralathan* , Slobodan Mijalkovic**, Pedro Barquinha***, Elvira Fortunato***, Rodrigo Martins***,Magali Estrada****, and Antonio Cerdeira****
*URV (SP), **Silvaco Ltd (UK), ***UNL(P), ****CINVESTAV (MEX)

Coffee Break
T_10 Three-Dimensional Electro-Thermal Circuit Model of Power Super-Junction MOSFET
Aleš Chvála, Daniel Donoval, Juraj Marek, Patrik Príbytný and Marián Molnár
Institute of Electronics and Photonics, Slovak University of Technology in Bratislava (SK)
T_11 A Close Comparison of Silicon and Silicon Carbide Double Gate JFETs
Matthias Bucher, Rupendra Sharma
Technical University of Crete, Chania, (GR)
T_12 Towards wide-frequency substrate model of advanced FDSOI MOSFET
Sergej Makovejev, Valeriya Kilchytska, Jean-Pierre Raskin, Denis Flandre
UCL (B)
16:00
End of the MOS-AK Workshop

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Jul 8, 2013

[repost nanobuff] On compact modeling

Posted on June 27, 2013 on nanobuff
"While the modeling industry is full of software solutions for all sorts of things in the operation of electronics from the very low to the very high level, there seems to be very sparse tools for simulating radiation effects. This would be normal if there was little interest or public research on the subject, but that is not the case. The models are out there, most of the basic concepts have been examined lots of decades ago, so what is stopping the industry? I really don’t know and I will not even try to answer.

Having said that, I would also like to state that compact modelling, in the case of radiation effects, is at least beneath me. I recently found this old compact modelling project. It is like a plugin to the Silvaco software. How would a compact modelling platform work in the ever-reducing dimensions of today? Things get fairly uncertain below 0.1 µm gate lengths. We need 3D, we need quantum models etc. just for the operation. And for the radiation part? That is now a materials science problem, I guess. And if you decide to go Monte Carlo, that’s even more demanding. The problem seems to be a “chicken and egg” one. We need more processing power to be able to simulate our next generation electronics that will give us more processing power."

[Leave a Reply]

Jul 5, 2013

Third Berkeley Symposium on Energy Efficient Electronic Systems

Time: October 28 - 29, 2013
Place: Sutardja Dai Hall, UCB, California, USA

Message from Symposium Organizers
Once again, we look forward to hosting another Berkeley Symposium on Energy Efficient Electronic Systems, a forum that we founded in 2009. Biennially, we bring together researchers who are working on breakthrough improvements in energy efficiency for information processing systems. Our goal is that the Symposium continue to be a venue for the attendees to gain an integrated perspective of the challenges and advances in this domain of technology through sessions that cover the entire food chain, from devices to systems. As in the two previous symposia, we expect that the academic setting of UC Berkeley will encourage open exchanges of ideas, and foster closer cooperation and collaborations among the researchers.

For the first time, we welcome IEEE Electronic Devices Society as a technical co-sponsor. Also new, the 2013 Organizing Committee is issuing a Call for Papers. These changes are intended to broaden participation at the Symposium, thereby furthering the Symposium's goal of fostering information exchanges and collaborations.

We look forward to seeing you at the 3rd Berkeley Symposium on Energy Efficient Electronic Systems.

Eli Yablonovitch, Co-Chair, Organizing Committee
Jeffrey Bokor, Co-Chair, Organizing Committee

[Symposium Link]

Jul 4, 2013

URSI-C Commission Workshop (Kawasaki)

Theme: "Simulation Techniques for wireless communication integrated circuit design" 

Sponsorship:
Sponsored by:
  • IEEE MTT-S Japan Chapter 
  • IEEE AP-S Japan Chapter 
  • IEEE VT-S Japan Chapter 
  • IEEE SSC-S Japan Chapter 
Date and time: Friday, 12:30 to 16:30, July 05, 2013
Location:  Toshiba Science Museum (directions from Komukaitoshiba town)
Entry fee: Free

Program
12:15 - 12:30 Reception
12:30 - 13:15 Toshiba Science Museum tour
13:30 - 13:40 Opening Remarks Masahiro Morikura (Kyoto University)
13:40 - 14:20 "High frequency modeling of the MOSFET, including the process variation" Yoshitomi Sadayuki (Toshiba)
14:20 - 15:00 "Challenges and Solutions for RFIC Realization"  Sugaya Hidehiko (Cadence Japan)
15:00 - 15:10 Break (10 minutes)
15:10 - 15:50 "Methodology for substrate coupling analysis with high frequency accuracy" Sotiris Bantas (Helic, Inc.)
15:50 - 16:30 "Behavioral technology of RF transceiver circuit" Takahiro Kikuchi (Agilent Technologies)
16:30 Closing
17:30 - social gathering

[read more...]

Jun 27, 2013

[mos-ak] "Advances in Condensed Matter Physics" Special Issue on Device Modeling

Advances in Condensed Matter Physics is published using an open access publication model, meaning that all interested readers are able  to freely access the journal online without the need for a subscription. Moreover, the journal currently has an Impact Factor of 1.158.

 

This special issue focuses on novel advances in the broad field of device modeling. Models of semiconductor devices are used in circuit simulators in order to predict the functionality of circuits and are an important prerequisite for successful circuit design. The currently available semiconductor models are facing enormous challenges in modeling the observed physical phenomena in the sub-50nm technologies. The demand for advanced models, which can describe emerging devices necessary in the near future and can account for their physical effects, has led to enormous R&D efforts in the development of advanced physics-based models. These novel devices that can reduce the cost of the actual ones (by using organic materials) and/or improve their performances (low leakage, low power, and high speed in a smaller footprint) will be preferred in circuits, thus calling for accurate and reliable models, including new device specific effects. Modeling these devices is of high importance in order to analyze and predict the behaviour of emerging ones, without the high cost necessary to fabricate the real components. For some specific purposes, like power and timing analysis, it is really necessary to incorporate models at gate level, too. These models also suffer the effects of nanoscaling and are currently under intense development.


Potential topics include, but are not limited to:
  • Modeling the physical behaviour of novel silicon-based FETs (FinFETs, DG FETs, nanowires, junctionless FETs, tunneling FETs, variable barrier transistors, etc.)
  • Modeling the physical behaviour of graphene-based devices
  • Modeling the physical behaviour of organic semiconductor-based devices (OLEDs, junctions, TFTs, sensors, etc.)
  • Device and gate level model implementation for circuit simulations

Before submission authors should carefully read over the journal's Author Guidelines, which are located at http://www.hindawi.com/journals/acmp/guidelines/.

Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at http://mts.hindawi.com/submit/journals/acmp/rdsd/ according to the following timetable:

 

Manuscript Due  Friday, 13 December 2013

First Round of Reviews  Friday, 7 March 2014

Publication Date  Friday, 2 May 2014

 

Lead Guest Editor

Oana Moldovan, Universitat Rovira i Virgili, Tarragona, Spain

Guest Editors 

AlejandraCastro-Carranza, Universitat Rovira i Virgili, 43007 Tarragona, Spain

François Lime, Universitat Rovira i Virgili, 43007 Tarragona, Spain

Rodrigo Picos, Universitat de les Illes Balears. Cra. deValldemossa, km 7.5, Palma, Illes Balears, Spain

Bogdan Mihai Nae, Universitat Rovira i Virgili, 43007 Tarragona, Spain

Spiros Nikolaidis, Aristotle Universityof Thessaloniki, Thessaloniki, Greece

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Jun 23, 2013

CMC @ Si2

The CMC as a member of the Si2 will continue its basic goal of examining, promoting and standardizing SPICE modeling efforts based upon business needs. CMC (see its Member List)  encourages developers to dwell on current and near-term problems that will advance compact modeling. They will continue to provide industry resources and funding for monitoring/mentoring compact model development.

[read more: CMC Presentation at DAC]

Jun 21, 2013

[mos-ak] 11th MOS-AK/GSA ESSDERC ESSCIRC Workshop with the keynote speaker Larry Nagel

Together with Prof. Andrei Vladimirescu, R&D Scientific Coordinator, the Organizing Committee and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the 11th MOS-AK/GSA ESSDERC ESSCIRC Workshop on Sept. 20, 2013 in Bucharest (RO). The event will open next decade of enabling compact modeling R&D exchange.  

Speakers - previsionary list (in alphabetic order)
  • Larry Nagel
    • MOS-AK Keynote Speaker
  • Prof. Matthias Bucher, TUC Chania
  • Dr. Ales Chvala, STU Bratislava
  • Prof. Benjamin Iniguez, URV Tarragona
  • Prof. Hans Juergen Mattausch, Uni Hiroshima
  • Dr. Paolo Nenzi, Uni Roma, NGSpice
  • Dr. Jean-Michel Sallese, EPFL Lausanne
  • Prof. Valentin Turin, OSTU Orel
  • Prof. Andrei Vladimirescu, ISE Paris and UC Berkeley
In the terms of participation, intending participants and authors should also note the following dates: 
  • Call for Papers - May 2013
  • 2nd Announcement - June 2013
  • Final Workshop Program - July, 2013
  • MOS-AK/GSA Workshop - Sept. 20, 2013

Further details and updates: <http://www.mos-ak.org/bucharest/
Email contact: <workshops@mos-ak.org

- with regards - WG (for the MOS-AK/GSA Committee

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Jun 14, 2013

Jobs for modelling specialists

This time, in Paris:

Senior Modelling Engineer

Location:
Paris, France
Sector:
Contract:
Permanent
Salary:
€50,000 – €70,000
 
Look here for more information.

Jun 11, 2013

EU Goal: Reach 20% World-Share in Chip Manufacturing by 2020

EU to spend € 10 billion to trigger € 100 billion investments — SEMI provides the platforms for our members to share critical implementation issues and actions to support the goals set by the EU [H. Kundert, president, SEMI Europe] 

The new European industrial strategy for micro- and nano-electronics, published on 23 May 2013, sets the framework for targeted investment across the electronics value and innovation chain. An Industrial Strategy Roadmap for Investment, to be developed by end 2013, will cover three complementary lines:
  • Transition to 450mm, expected to primarily benefit equipment and material manufacturers in Europe
  • “More than Moore” on 200mm and 300 mm
  • “More Moore” for ultimate miniaturization on 300mm wafers
Investment will be concentrated, focusing on Europe’s clusters of excellence in manufacturing and design (Grenoble, Dresden and Eindhoven-Leuven), but will also support partnerships and alliances across the value chain in Europe.

[read more...] also don't miss the SEMICON Europa 2013 Call for Papers (open until June 27). The conferences are a great opportunity to present your technology and latest achievements to a large audience of industry professionals. For more information about SEMICON Europe programs, the Call for Papers and opportunities to exhibit and present your products please go online and visit semiconeuropa.org.

Jun 6, 2013

Jobs for compact modelling specialists

Some jobs I've found while surfing the internet: (remember, we're not offering these jobs, only commenting on them!!).

(look at http://www.semiconductorjobs.com/a/jobs/find-jobs/q-compact+model+device for more information).


May 30 Modeling Engineering Manager TriQuint Semiconductor US Richardson, TX
device characterization measurement, device model parameter extraction, and model ... product design. Produce and maintain 'compact' models for GaAs and GaN RFIC... more
 
May 05 Spice Modeling Engineer Globalfoundries California
experienced Spice modeling engineer in the Compact Modeling & Characterization (CMC) ... Working closely with lab engineers on the device characterization (DC/AC/Transient/RF),... more
 
Mar 26 Compact Device Modeling Engineer Intel Hillsboro, OR
Title: Compact Device Modeling Engineer Location: USA-Oregon, Hillsboro Job Number: 705850 ... * Developing and maintaining compact device models in internal circuit... more

May 30 Senior Software Architect Xilinx San Jose, CA
Candidate will work in Device Modeling group in FPGA Implementation tools division of ... and coming up with new algorithms and compact data structures to represent Xilinx... more
 
May 23 Tcad device engineer Job Micron Boise, ID
In this position, you will be studying detailed process and device design/optimization usi ... - Experience/knowledge in CMOS process, deep submicron device physics, state of the art mo... more

May 17 Staff Engineer
Santa Clara, CA
special needs in device modeling (e.g. device measurement, reliability stress, and ... Knowledge in numerical device/process simulation and chip level extraction is a plus. more
 
May 15 Compact Device Modeling Engineer Job Intel Hillsboro, OR
involves developing state-of-the-art compact device models and working in a highly ... - Developing and maintaining compact device models in internal circuit... more






Jun 1, 2013

[mos-ak] Si2 Announces Acquisition of the Compact Model Council

Standard SPICE Models, API, and Language Foundational to Industry

AUSTIN, Texas — (BUSINESS WIRE) — May 31, 2013 — The Silicon Integration Initiative (Si2) has announced the acquisition of the Compact Model Council (CMC). The CMC, formed in 1996, develops and standardizes compact models of electronic devices used within commercial circuit simulators across the electronics industry, including virtually all SPICE-class simulation. The CMC will be renamed the Compact Model Coalition to blend with Si2's organizational structure. The CMC, represented by 37 member companies, supports 20 active subcommittees and has produced over a dozen widely-used standard device models, modeling API, and SPICE language standard.

Details of the transfer and future plans will be presented at the Design Automation Conference (DAC) to be held in Austin, TX from June 2-6. The first presentation will be at the Si2 25th Anniversary Luncheon Celebration on June 3, 12-1:30 PM in Room 9ABC in the Austin Convention Center. The luncheon is free of charge. Other presentations are scheduled in the Si2 Booth #1427 on the DAC exhibit floor at: June 4 - 10:30AM and 4:30PM, and June 5 - 1:30PM. More information on this and other Si2 events can be found at this link: http://www.si2.org/?page=1544

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May 22, 2013

[mos-ak] Workshop on Compact TFT Modeling for Circuit Simulation

Call for Papers
5th International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation (CTFT)
CEA-LITEN, MINATEC Campus, Grenoble, France, June 21, 2013

In recent years, the increasing use of active matrix flat-panel displays and bio-medical imagers in commercial electronic products has drawn a significant attention to thin-film transistors (TFT) and technologies. TFTs on amorphous- and poly-silicon as well as newly emerging organic, transparent metal oxide and nano-composite semiconductor technologies are becoming increasingly common. For example, flat panel displays are finding widespread use in many products such as cellular phones, personal digital assistants (PDAs), camcorders, laptop personal computers (PCs), to name a few. The active matrix display is composed of a grid or matrix of picture elements called as "pixels". Thousands or millions of these pixels together create an image on the display, in which the TFTs act as switches to individually turn each pixel. More increasingly TFTs are starting to be used as analog circuit elements for rudimentary signal conditioning. Therefore, physically-based compact modeling of TFTs for circuit simulation is crucial to accurately and reliably predict TFT behavior in the active matrix. A concentrated R&D effort is critical for developing physically-based compact TFT models for emerging thin-film technologies, and significant R&D efforts along these lines are underway world-wide.

The CTFT workshop will provide a forum for discussions and current practices on compact TFT modeling. The 2013 CTFT workshop edition will be held on June 21 in Grenoble (France) in combination with the 9th International Conference on Organic Electronics (ICOE, June 18-20, www.icoe2013.org ). The CTFT workshop is sponsored by IEEE EDS Compact Modeling Technical Committee in joint collaboration with CEA-LITEN, the Universitat Rovira i Virgili (Tarragona Spain) and the University of Cambridge (UK).

A partial list of the areas of interest includes:
  • Physics of TFTs and operating principles
  • Compact TFT device models for circuit simulation
  • Model implementation and circuit analysis techniques
  • Model parameter extraction techniques
  • Applications of compact TFT models in emerging products
  • Compact models for interconnects in active matrix flat panels
Abstract (500 Word) Submission deadline:  May 24, 2013
Prospective authors should submit a 500-word abstract to: Bogdan Mihai Nae (nae.bogden@urv.cat)
Submission of a 1-page or 2-page single-column paper to be included in proceedings: June 8, 2013.
Download the word template here for the 1-page or 2-page final version of the paper.

 

Committee Members      

Anis Daami, CEA-LITEN, France (General Co-Chair)

François Templier, CEA-LITEN, France (General Co-Chair)

Vincent Fischer, CEA-LITEN, France

Arokia Nathan, Cambridge University, UK

Benjamin Iniguez, Universitat Rovira i Virgili, Spain

Jamal Deen, McMaster University, Canada

Bill Milne, Cambridge University, UK

Andre Sazonov, University of Waterloo, Canada

John Robertson, Cambridge University, UK

Xiaojun Guo, Shanghai Jiaotong University, China

Flora Li, Polymer Vision, The Netherlands

Hyun Jae Kim, Yonsei University, Korea

Samar Saha, Silterra Corp., USA

Zhou Xing, Nanyang Technological University, Singapore

Norbert Fruehauf, University of Stuttgart, Germany

Peyman Servati, University of British Columbia, Canada

Man Wong, HKUST, Hong Kong

 

 

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May 3, 2013

[mos-ak] [Call for Papers] 11th MOS-AK/GSA ESSDERC ESSCIRC Workshop Sept. 20, 2013 Bucharest

Together with the Organizing Committee and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the 11th MOS-AK/GSA ESSDERC ESSCIRC Workshop on Sept. 20, 2013 in Bucharest (RO). The event will open next decade of enabling compact modeling R&D exchange.

Topics to be covered include the following:
  • Advances in semiconductor technologies and processing
  • Compact Modeling (CM) of the electron devices
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • CM of passive, active, sensors and actuators
  • Emerging Devices, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and IC Designs
  • Foundry/Fabless Interface Strategies
In the terms of participation, intending participants and authors should also note the following dates: 
  • Call for Papers - May 2013
  • 2nd Announcement - June 2013
  • Final Workshop Program - July, 2013
  • MOS-AK/GSA Workshop - Sept. 20, 2013
Abstract on-line submission <http://www.mos-ak.org/bucharest/abstracts.php>

Further details and updates: <http://www.mos-ak.org/bucharest/
Email contact: <workshops@mos-ak.org

- with regards - WG (for the MOS-AK/GSA Committee

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May 1, 2013

13th HICUM Workshop 2013


HICUM Workshop at TU-Delft, May 27-28, 2013
The HIgh CUrrent Model (HICUM) has become an industry standard and one of the most suitable compact models for modern HBTs fabricated in latest process technologies covering a wide range of high frequency and mmW applications.
Since 2001, the annual HICUM Workshop has become a technical forum for the needs and interests of model users and developers for discussing the present trends and future needs of the bipolar transistor modeling and circuit design community.

Workshop Highlights:
  • Special presentation by Prof. Spirito on mm-wave on-wafer measurements
  • Various presentations covering the modeling of various bipolar transistor phenomena, new parameter extraction strategies, production-type model development, model testing and performance comparisons
  • Special presentations on benchmark circuits for model verification (solicited)

Apr 29, 2013

[mos-ak] [press note] Spring MOS-AK/GSA Workshop in Munich; April 11-12, 2013

press note highlighting recent Spring MOS-AK/GSA Workshop in Munich is available online:
http://www.gsaglobal.org/2013/04/mos-akgsa-munich-workshop-press-note/

The MOS-AK/GSA Modeling Working Group is coordinating several upcoming modeling events: a special compact modeling session at the MIXDES Conference in Gdynia (https://www.mixdes.org); an autumn Q3/2013 MOS-AK/GSA workshop in Bucharest (http://www.mos-ak.org/bucharest/), a winter Q4/2013 MOS-AK/GSA meeting in Washington DC, and a spring Q2/2014 MOS-AK/GSA meeting in London (http://www.mos-ak.org).

Harrison Beasley
Technical Working Groups Manager
Global Semiconductor Alliance (GSA)


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Apr 26, 2013

[mos-ak] BSIM6.0 is industry standard model

recently, Prof. Yogesh Singh Chauhan, the BSIM6 project coordinator and lead developer, has announced that the BSIM6.0 has been approved as industry standard bulk MOSFET model by CMC on April 18, 2013. The BSIM6 model Verilog-A code, its manual and related documents will be available thru its website.

Related links:
BSIM6 Model Home Page
BSIM-EPFL Collaboration Announcement

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[mos-ak] [on-line publications] Spring MOS-AK/GSA Workshop in Munich; April 11-12, 2013

Together with the workshop host, Prof. Dr. Doris Schmitt-Landsiedel, Lehrstuhl fur Technische Elektronik, TUM and Extended MOS-AK/GSA TPC Committee and the workshop sponsors MunEDA and Tanner EDA as well as the IEEE EDS Chapter Germany, the technical program cosponsor, we have organized recent spring MOS-AK/GSA Workshop in Munich. The workshop's presentations are available on-line at <http://www.mos-ak.org/munich_2013/

The MOS-AK/GSA Modeling Working Group coordinates several upcoming modeling events: a special compact modeling session at the MIXDES Conference in Gdynia (PL) (https://www.mixdes.org);  an autumn Q3/2013 MOS-AK/GSA workshop in Bucharest (RO) (http://www.mos-ak.org/bucharest/), a winter Q4/2013 MOS-AK/GSA meeting in Washington DC, USA, spring Q2/2014 MOS-AK/GSA meeting in London (http://www.mos-ak.org).

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Apr 24, 2013

TED Call for Papers on Compact Modeling of Emerging Devices

Compact Models (CMs) for circuit simulation have been at the heart of CAD tools for circuit design for almost five decades. As the mainstream CMOS technology is scaled into the nanometer regime, development of a truly physical and predictive CM for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge. The last call for a special issue on “advanced compact models and 45-nm modeling challenges” was in 2005. Seven years have passed, new technology nodes have been implemented, compact models have evolved and new compact models as well as compact models for new devices are being developed. Therefore, there is a need for another special issue dedicated to the advancement and challenges in core field-effect transistor (FET) models for 32-nm technologies and beyond as well as emerging technologies. For the core FET models, the associated noise/mismatch and reliability/variability models as well as proximity effects have become an essential part of the modeling effort. High-frequency, high-voltage, high-power, high-temperature devices have been extensively investigated, and their CMs are being reported in the literature. Device/circuit interaction and layout-dependent proximity effects are also hot topics today that are essential in nanometer chip designs. It is timely to report advances in these CMs in the 32-nm/22-nm technology era.

Concurrently, nonclassical MOSFETs as well as their CMs, such as multigate FinFETs and nanowire FETs, partially/fully-depleted ultrathin body (UTB) SOT, and thin-film transistors (TFTs), have emerged over the past decades. With the announcement of FinFETs being used in 22-nm and sub-22nm technology nodes, the need for such core models for fabless designers becomes an urgent reality. In these nonclassical devices, transistors are essentially short-channel, narrow-width, and thin-body. Tt is also an interesting topic to discuss and debate on the two different formalisms “top-down” drift-diffusion formulation adding ballistic effects versus “bottom-up” quasi-ballistic formulation adding scattering effects for modeling the real devices that are somewhere in between. Heterogeneous integration of various devices into the CMOS platform also becomes an important trend.
In addition, it is also timely to report advances in CMs of emerging devices beyond traditional silicon CMOS, such as different materials (III-V/Ge channel, organic) and different source/drain injection mechanisms (Schottky-barrier, tunneling, and junctionless FETs). These emerging device options for future VLSI building blocks have been studied extensively, while good physical CMs are still lacking. The special issue in these topics will stimulate research and development to promote modeling efforts such that theory would lead and guide technology realization and selection for future generations.
The special issue for the TRANSACTIONS ON ELECTRON DEVICES on compact modeling of emerging devices is devoted to the review and report of advancements in CMs for 32-nm technologies and beyond, including bulk and nonclassical CMOS and their associated noise/mismatch and reliability/variability models, as well as various emerging devices as future generation device options. It is timely as the industry is in the transition from traditional planar bulk-CMOS towards vertical FinFET technologies, and exploration of heterogeneous integration with various materials and structural choices.


Please submit manuscripts by using the following URL: http://mc.manuscriptcentral.com/ted
MAKE SURE TO MENTION THE SPECIAL ISSUE IN THE COVER LETTER

Paper submission Deadline: June 30, 2013
Scheduled Publication Date: February 2014

Guest Editors:
Xing Zhou, Nanyang Technological University, 
Jamal Deen, McMaster University, 
Benjamin Iniguez, Universitat Rovira i Virgili, 
Christian Enz, Swiss Federal Institute of Technology, 
Rafael Rios, Intel Corp.

If you have any questions about submitting a manuscript, please contact:
IEEE EDS Publications Office
445 Hoes Lane Piscataway JN 08854
Phone: +1 732 562 6855

Digital Object Identifier 10.1109/TED.2013.2253418

Apr 11, 2013

A single European semiconductor strategy is on its way...

From Solid-State Technology:

At the International Semiconductor Strategy Symposium (ISS Europe), the European semiconductor industry affirmed its ability to innovate. More than 170 top industry representatives agreed on a number of joint steps and strategic measures to strengthen their competitiveness and sustainability. The controversial question whether the best way to attack future challenges will be "More Moore" or "More than Moore," ended in an expected compromise, namely that the industry should pursuit both strategies concurrently, the participants of a panel expressed. Whilst the More than Moore sector is traditionally strong in Europe, going on with More Moore is important for two to three device makers in Europe and in particular for the European equipment suppliers which export 80% of their products.
In a global scale, the semiconductor industry is approaching the move to 450mm wafer processing technology – a step that promises to greatly boost the productivity of semiconductor manufacturers. However, since the investment to build a 450mm fab easily exceeds the 10 billion dollar mark, this move is regarded as risky and, for this reason, reserved to only the very largest enterprises. In the past, this perspective divided the European industry into two camps - the "More Moore" group that advocates taking on the 450mm challenge, and the "More than Moore" group which shunned this risky investment and preferred to rely on application-oriented differentiation instead.
At the event SEMI Europe, an industry association embracing enterprises that represent the entire value chain and organizer of the ISS Europe, set up a high-ranking panel discussion on options and choices of a single European semiconductor strategy. The panel proved that entrepreneurial spirit is well alive among Europe's chipmakers, technology suppliers and researchers.

Read more...

Apr 5, 2013

[mos-ak] CMC GaN HEMT Model Standardization Effort - Call for Candidate Models

Since its inception, the Compact Model Council (CMC) has collaborated to develop, maintain, and standardize compact models for widely used semiconductor components. CMC members have decided that gallium nitride (GaN) technology is important for their business and the CMC intends to develop its first standard GaN HEMT transistor model. More information about the CMC can be found in the attached document. The ability for the model to generalize from GaN to other III-V FETs would be a bonus but is not a requirement. After the CMC evaluates and standardizes a model for GaN HEMTs, the CMC may decide to extend this effort to all III-V FET/HEMT devices. We are currently soliciting candidate models for this standard.

 

GaN transistors are high electron mobility transistors (HEMTs), a FET technology based on a heterojunction channel and a Schottky / Insulated / Junction (pGaN) gate. The primary applications for GaN transistors are for high voltage / high power devices to be used as for example as switches; and for high frequency / high power devices to be used for example in RF power amplifiers.

 

The CMC plans a three-phase process for identification and evaluation of candidate models. We currently have started Phase I which is a solicitation of available models which meet the fundamental requirements set forth in the attached Requirements Document. The GaN Subcommittee will review written proposals and request top candidates to present an overview of their model at a CMC Meeting. Candidates identified in Phase I which have sufficient support from CMC sponsors will be subjected to thorough testing in subsequent Phases. All developers submitting a proposed standard to CMC for adoption will read and accept the CMC Standard Model Copyright Policy.

 

The attached document lists the model requirements and various types of measurements that the model must reproduce. They include IV curves over various bias and temperature conditions, high frequency measurements, switching measurements, and time dependent measurements to characterize trapping effects. The attached check-list should be used to identify which requirements are or will be met by the candidate model.

 

After a set of candidate models is obtained, Phase II starts with a set of measured data against which the models will be evaluated. This technology has not yet been decided. At this point the CMC will need brief documentation outlining the list of measurements and the data. The details of how the GaN devices are being fabricated, nor the details of their internal structure, will be required. A minimum set of device physical dimensions would be needed in order to feed candidate models with meaningful parameters, such as channel length, channel width, gate to source/drain contact distance, etc. The CMC GaN FET subcommittee will review the proposed measurement data and will determine which data set(s) will be used for model evaluation. It is possible that data from more than one source will be retained for the model evaluation, to cover an as wide as possible range of applications.

 

If you are aware of any organization willing to contribute, please forward this document, or contact the GaN FET subcommittee chair, Samuel Mertens (samuel_mertens(at)agilent.com). Don't hesitate to ask me any questions about the standardization process or the CMC.




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Apr 3, 2013

[mos-ak] [Final Program] Spring MOS-AK/GSA Workshop in Munich; April 11-12, 2013

Together with the workshop host, Prof. Dr. Doris Schmitt-Landsiedel, Lehrstuhl fur Technische Elektronik, TUM and Extended MOS-AK/GSA TPC Committee and the workshop sponsors MunEDA and Tanner EDA as well as the IEEE EDS Chapter Germany, the technical program cosponsor, we have pleasure to invite to the spring MOS-AK/GSA Workshop in Munich 

Venue:
Lehrstuhl fur Technische Elektronik
Room: 5325, 5th floor <http://www.lte.ei.tum.de/index.html>
Technische Universitat Munchen 
Arcisstr. 21 D-80333 Munchen

MOS-AK/GSA Workshop Agenda

April 11 Thursday, Afternoon Session 
13:00 - 16:00
 Oral presentations

Welcome and Workshop Opening
Wladek Grabinski; MOS-AK

Statistical modeling with backward propagation of variance (BPV) and covariance equations
Klaus-Willi Pieper and Elmar Gondro; Infineon Technologies

Circuit Sizing: Corner Models Challenges & Applications
Matthias Sylvester; MunEDA (D)

Compact Modeling Activities in The Framework of the EU-Funded "COMON" Project
Benjamin Iñiguez; URV, Tarragona (SP)

Effective Device Modeling And Verification Tools
Ingo Nickeleit; Agilent Technologies
16:00 - 17:00
 Software/Hardware Demos

MunEDA Framework Applications
Tanner TSpice Verilog-A
Agilent B1505A Power Device Analyzer / Curve Tracer

Networking Evening Event
April 12 Friday, Sessions
9:00 - 12:00
 Morning Oral Presentations

Institute for Technical Electronics (LTE) Presentation 
Prof. Dr. rer. nat. Doris Schmitt-Landsiedel, LTE, TUM (D)

STEEPER: Tunnel Field Effect Transistors (TFETs) Technology, Devices and Applications 
Thomas Schulz and Reinhard Mahnkopf, Intel, IMC, (D)

Current and Future Challenges for TCAD
Christoph Jungemann and Christoph Zimmermann; RWTH Aachen University (D)

Advances in Verilog-A Compact Semiconductor Device Modeling with Qucs/QucsStudio
Mike Brinson; London Metropolitan University, London, UK
12:00 - 13:00
 Lunch
13:00 - 16:00 Afternoon Oral Presentations

FDSOI Devices Bentchmarking
Bich-Yen Nguyen; SOITEC (F)

COMON: SOI Multigate Devices Modeling
Alexander Kloes; THM (D)

COMON: FinFET Modeling Activities 
Udit Monga; Intel, IMC, (D)

COMON: HV MOS Devices Modeling
Matthias Bucher; TUC, (GR)
 End of the Workshop

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