Interacts with other groups such as Design, Process, System, Reliability, and FA. 5+ years of related hands-on industrial experience.... 5+ years of related hands-on industrial design experience. Hands-on experience with device physics, device process, device characterization, and systems.... Possess working knowledge of semiconductor device development processes. Semiconductor Research and Development Process Improvement Engineer, IBM Corporation,... |
Aug 18, 2013
Semiconductor Device Characterization Engineer jobs
Aug 13, 2013
Fwd: 4 new Semiconductor Device Characterization Engineer jobs
Knowledge of analog and mixed signal board level design including PCB layout guidelines a strong plus. Knowledge of both analog and digital video interface... GLOBALFOUNDRIES - Malta, NY Technology related Bachelor's degree with 6 years experience ;. or Master's degree plus 5 years experience in process technology development area;.... Experience would be obtained through your educational level research and/or relevant job/internship experiences.... Quantum Solution - Sunnyvale, CA Excellent proficiency of Cadence's custom IC design environment, analog/mixed signal circuit simulation (Spectre, Hspice, Ocean scripting, ).... |
Aug 8, 2013
[mos-ak] [Final Program] 11th MOS-AK ESSDERC ESSCIRC Workshop with the keynote speaker Larry Nagel
9:00 - 12:00 | Morning Session - Chair: Prof. Andrei Vladimirescu, ISEP (F); UCB (USA) |
O_1 | Welcome and Workshop Opening W. Grabinski MOS-AK Group (EU) |
T_2 | SPICE - MOS-AK Keynote Larry Nagel Omega Enterprises Consulting (USA) |
T_3 | NGSPICE: recent progresses and future plans Paolo Nenzi*, Francesco Lannutti*, Robert Larice**, Holger Vogt**, Dietmar Warning** *DIET - Sapienza University of Roma (I), ** NGSPICE Development Team |
T_4 | KCL and Linear/NonLinear Separation in NGSPICE Francesco Lannutti DIET - Sapienza University of Roma (I) and NGSPICE Development Team |
Coffee Break | |
T_5 | Modeling Junction Less FETs Jean-Michel Sallese, Farzan Jazaeri, Lucian Barbut EPFL (CH) |
T_6 | HiSIM-Compact Modeling Framework Hans Juergen Mattausch Uni. Hiroshima (J) |
P_7 | The Correct Account of Nonzero Differential Conductance in the Saturation Regime in the MOSFET Compact Model Valentin Turin*, Gennady Zebrev**, Sergey Makarov***, Benjamin Iniguez****, and Michael Shur***** *State University-ESPC (RU),**MEPHI (RU),***SYMICA Inc (RU),****URV (SP),*****RPI (USA) |
12:00 -13:00 | Lunch Break |
13:00 -16:00 | Afternoon Session - Chair: W. Grabinski, MOS-AK Group |
T_8 | State of the Art Modeling of Passive CMOS Components Bernd Landgraf Infineon Technologies (A) |
T_9 | Compact I-V Model of Amorphous Oxide TFTs Benjamin Iniguez*,Alejandra Castro-Carranza* , Muthupandian Cheralathan* , Slobodan Mijalkovic**, Pedro Barquinha***, Elvira Fortunato***, Rodrigo Martins***,Magali Estrada****, and Antonio Cerdeira**** *URV (SP), **Silvaco Ltd (UK), ***UNL(P), ****CINVESTAV (MEX) |
Coffee Break | |
T_10 | Three-Dimensional Electro-Thermal Circuit Model of Power Super-Junction MOSFET Aleš Chvála, Daniel Donoval, Juraj Marek, Patrik Príbytný and Marián Molnár Institute of Electronics and Photonics, Slovak University of Technology in Bratislava (SK) |
T_11 | A Close Comparison of Silicon and Silicon Carbide Double Gate JFETs Matthias Bucher, Rupendra Sharma Technical University of Crete, Chania, (GR) |
T_12 | Towards wide-frequency substrate model of advanced FDSOI MOSFET Sergej Makovejev, Valeriya Kilchytska, Jean-Pierre Raskin, Denis Flandre UCL (B) |
16:00 | End of the MOS-AK Workshop |
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at http://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/groups/opt_out.
Jul 8, 2013
[repost nanobuff] On compact modeling
[Leave a Reply]
Jul 5, 2013
Third Berkeley Symposium on Energy Efficient Electronic Systems
Place: Sutardja Dai Hall, UCB, California, USA
Message from Symposium Organizers
Eli Yablonovitch, Co-Chair, Organizing Committee
Jeffrey Bokor, Co-Chair, Organizing Committee
[Symposium Link]
Jul 4, 2013
URSI-C Commission Workshop (Kawasaki)
Sponsorship:
Sponsored by:
- IEEE MTT-S Japan Chapter
- IEEE AP-S Japan Chapter
- IEEE VT-S Japan Chapter
- IEEE SSC-S Japan Chapter
Location: Toshiba Science Museum (directions from Komukaitoshiba town)
Entry fee: Free
Program
12:15 - 12:30 Reception
12:30 - 13:15 Toshiba Science Museum tour
13:30 - 13:40 Opening Remarks Masahiro Morikura (Kyoto University)
13:40 - 14:20 "High frequency modeling of the MOSFET, including the process variation" Yoshitomi Sadayuki (Toshiba)
14:20 - 15:00 "Challenges and Solutions for RFIC Realization" Sugaya Hidehiko (Cadence Japan)
15:00 - 15:10 Break (10 minutes)
15:10 - 15:50 "Methodology for substrate coupling analysis with high frequency accuracy" Sotiris Bantas (Helic, Inc.)
15:50 - 16:30 "Behavioral technology of RF transceiver circuit" Takahiro Kikuchi (Agilent Technologies)
16:30 Closing
17:30 - social gathering
[read more...]
Jun 27, 2013
[mos-ak] "Advances in Condensed Matter Physics" Special Issue on Device Modeling
Advances in Condensed Matter Physics is published using an open access publication model, meaning that all interested readers are able to freely access the journal online without the need for a subscription. Moreover, the journal currently has an Impact Factor of 1.158.
This special issue focuses on novel advances in the broad field of device modeling. Models of semiconductor devices are used in circuit simulators in order to predict the functionality of circuits and are an important prerequisite for successful circuit design. The currently available semiconductor models are facing enormous challenges in modeling the observed physical phenomena in the sub-50nm technologies. The demand for advanced models, which can describe emerging devices necessary in the near future and can account for their physical effects, has led to enormous R&D efforts in the development of advanced physics-based models. These novel devices that can reduce the cost of the actual ones (by using organic materials) and/or improve their performances (low leakage, low power, and high speed in a smaller footprint) will be preferred in circuits, thus calling for accurate and reliable models, including new device specific effects. Modeling these devices is of high importance in order to analyze and predict the behaviour of emerging ones, without the high cost necessary to fabricate the real components. For some specific purposes, like power and timing analysis, it is really necessary to incorporate models at gate level, too. These models also suffer the effects of nanoscaling and are currently under intense development.
- Modeling the physical behaviour of novel silicon-based FETs (FinFETs, DG FETs, nanowires, junctionless FETs, tunneling FETs, variable barrier transistors, etc.)
- Modeling the physical behaviour of graphene-based devices
- Modeling the physical behaviour of organic semiconductor-based devices (OLEDs, junctions, TFTs, sensors, etc.)
- Device and gate level model implementation for circuit simulations
Before submission authors should carefully read over the journal's Author Guidelines, which are located at http://www.hindawi.com/
Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at http://mts.hindawi.com/submit/
Manuscript Due Friday, 13 December 2013
First Round of Reviews Friday, 7 March 2014
Publication Date Friday, 2 May 2014
Lead Guest Editor
Oana Moldovan, Universitat Rovira i Virgili, Tarragona, Spain
Guest Editors
--AlejandraCastro-Carranza, Universitat Rovira i Virgili, 43007 Tarragona, Spain
François Lime, Universitat Rovira i Virgili, 43007 Tarragona, Spain
Rodrigo Picos, Universitat de les Illes Balears. Cra. deValldemossa, km 7.5, Palma, Illes Balears, Spain
Bogdan Mihai Nae, Universitat Rovira i Virgili, 43007 Tarragona, Spain
Spiros Nikolaidis, Aristotle Universityof Thessaloniki, Thessaloniki, Greece
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at http://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/groups/opt_out.
Jun 23, 2013
CMC @ Si2
[read more: CMC Presentation at DAC]
Jun 21, 2013
[mos-ak] 11th MOS-AK/GSA ESSDERC ESSCIRC Workshop with the keynote speaker Larry Nagel
- Larry Nagel
- MOS-AK Keynote Speaker
- Prof. Matthias Bucher, TUC Chania
- Dr. Ales Chvala, STU Bratislava
- Prof. Benjamin Iniguez, URV Tarragona
- Prof. Hans Juergen Mattausch, Uni Hiroshima
- Dr. Paolo Nenzi, Uni Roma, NGSpice
- Dr. Jean-Michel Sallese, EPFL Lausanne
- Prof. Valentin Turin, OSTU Orel
- Prof. Andrei Vladimirescu, ISE Paris and UC Berkeley
- Call for Papers - May 2013
- 2nd Announcement - June 2013
- Final Workshop Program - July, 2013
- MOS-AK/GSA Workshop - Sept. 20, 2013
Email contact: <workshops@mos-ak.org>
- with regards - WG (for the MOS-AK/GSA Committee)
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at http://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/groups/opt_out.
Jun 14, 2013
Jobs for modelling specialists
Senior Modelling Engineer
Jun 11, 2013
EU Goal: Reach 20% World-Share in Chip Manufacturing by 2020
The new European industrial strategy for micro- and nano-electronics, published on 23 May 2013, sets the framework for targeted investment across the electronics value and innovation chain. An Industrial Strategy Roadmap for Investment, to be developed by end 2013, will cover three complementary lines:
- Transition to 450mm, expected to primarily benefit equipment and material manufacturers in Europe
- “More than Moore” on 200mm and 300 mm
- “More Moore” for ultimate miniaturization on 300mm wafers
Jun 6, 2013
Jobs for compact modelling specialists
(look at http://www.semiconductorjobs.com/a/jobs/find-jobs/q-compact+model+device for more information).
May 30 | Modeling Engineering Manager | TriQuint Semiconductor US | Richardson, TX |
device characterization measurement, device model parameter extraction, and model ... product design. Produce and maintain 'compact' models for GaAs and GaN RFIC...
more
|
|||
May 05 | Spice Modeling Engineer | Globalfoundries | California |
experienced Spice modeling engineer in the Compact Modeling & Characterization (CMC) ... Working closely with lab engineers on the device characterization (DC/AC/Transient/RF),...
more
|
|||
Mar 26 | Compact Device Modeling Engineer | Intel | Hillsboro, OR |
Title: Compact Device Modeling Engineer Location: USA-Oregon, Hillsboro Job Number: 705850 ... * Developing and maintaining compact device models in internal circuit...
more
|
May 30 | Senior Software Architect | Xilinx | San Jose, CA |
Candidate will work in Device Modeling group in FPGA Implementation tools division of ... and coming up with new algorithms and compact data structures to represent Xilinx...
more
|
|||
May 23 | Tcad device engineer Job | Micron | Boise, ID |
In this position, you will be studying detailed process and device design/optimization usi ... - Experience/knowledge in CMOS process, deep submicron device physics, state of the art mo...
more
|
May 17 | Staff Engineer | Santa Clara, CA | |
special needs in device modeling (e.g. device measurement, reliability stress, and ... Knowledge in numerical device/process simulation and chip level extraction is a plus.
more
|
|||
May 15 | Compact Device Modeling Engineer Job | Intel | Hillsboro, OR |
involves developing state-of-the-art compact device models and working in a highly ... - Developing and maintaining compact device models in internal circuit...
more
|
Jun 1, 2013
[mos-ak] Si2 Announces Acquisition of the Compact Model Council
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at http://groups.google.com/group/mos-ak?hl=en.
For more options, visit https://groups.google.com/groups/opt_out.
May 22, 2013
[mos-ak] Workshop on Compact TFT Modeling for Circuit Simulation
5th International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation (CTFT)
CEA-LITEN, MINATEC Campus, Grenoble, France, June 21, 2013
In recent years, the increasing use of active matrix flat-panel displays and bio-medical imagers in commercial electronic products has drawn a significant attention to thin-film transistors (TFT) and technologies. TFTs on amorphous- and poly-silicon as well as newly emerging organic, transparent metal oxide and nano-composite semiconductor technologies are becoming increasingly common. For example, flat panel displays are finding widespread use in many products such as cellular phones, personal digital assistants (PDAs), camcorders, laptop personal computers (PCs), to name a few. The active matrix display is composed of a grid or matrix of picture elements called as "pixels". Thousands or millions of these pixels together create an image on the display, in which the TFTs act as switches to individually turn each pixel. More increasingly TFTs are starting to be used as analog circuit elements for rudimentary signal conditioning. Therefore, physically-based compact modeling of TFTs for circuit simulation is crucial to accurately and reliably predict TFT behavior in the active matrix. A concentrated R&D effort is critical for developing physically-based compact TFT models for emerging thin-film technologies, and significant R&D efforts along these lines are underway world-wide.
The CTFT workshop will provide a forum for discussions and current practices on compact TFT modeling. The 2013 CTFT workshop edition will be held on June 21 in Grenoble (France) in combination with the 9th International Conference on Organic Electronics (ICOE, June 18-20, www.icoe2013.org ). The CTFT workshop is sponsored by IEEE EDS Compact Modeling Technical Committee in joint collaboration with CEA-LITEN, the Universitat Rovira i Virgili (Tarragona Spain) and the University of Cambridge (UK).
A partial list of the areas of interest includes:
- Physics of TFTs and operating principles
- Compact TFT device models for circuit simulation
- Model implementation and circuit analysis techniques
- Model parameter extraction techniques
- Applications of compact TFT models in emerging products
- Compact models for interconnects in active matrix flat panels
Prospective authors should submit a 500-word abstract to: Bogdan Mihai Nae (nae.bogden@urv.cat)
Submission of a 1-page or 2-page single-column paper to be included in proceedings: June 8, 2013.
Download the word template here for the 1-page or 2-page final version of the paper.
Committee Members
Anis Daami, CEA-LITEN, France (General Co-Chair) | François Templier, CEA-LITEN, France (General Co-Chair) |
Vincent Fischer, CEA-LITEN, France | Arokia Nathan, Cambridge University, UK |
Benjamin Iniguez, Universitat Rovira i Virgili, Spain | Jamal Deen, McMaster University, Canada |
Bill Milne, Cambridge University, UK | Andre Sazonov, University of Waterloo, Canada |
John Robertson, Cambridge University, UK | Xiaojun Guo, Shanghai Jiaotong University, China |
Flora Li, Polymer Vision, The Netherlands | Hyun Jae Kim, Yonsei University, Korea |
Samar Saha, Silterra Corp., USA | Zhou Xing, Nanyang Technological University, Singapore |
Norbert Fruehauf, University of Stuttgart, Germany | Peyman Servati, University of British Columbia, Canada |
Man Wong, HKUST, Hong Kong |
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at http://groups.google.com/group/mos-ak?hl=en.
For more options, visit https://groups.google.com/groups/opt_out.
May 3, 2013
[mos-ak] [Call for Papers] 11th MOS-AK/GSA ESSDERC ESSCIRC Workshop Sept. 20, 2013 Bucharest
- Advances in semiconductor technologies and processing
- Compact Modeling (CM) of the electron devices
- Verilog-A language for CM standardization
- New CM techniques and extraction software
- CM of passive, active, sensors and actuators
- Emerging Devices, CMOS and SOI-based memory cells
- Microwave, RF device modeling, high voltage device modeling
- Nanoscale CMOS devices and circuits
- Technology R&D, DFY, DFT and IC Designs
- Foundry/Fabless Interface Strategies
- Call for Papers - May 2013
- 2nd Announcement - June 2013
- Final Workshop Program - July, 2013
- MOS-AK/GSA Workshop - Sept. 20, 2013
Email contact: <workshops@mos-ak.org>
- with regards - WG (for the MOS-AK/GSA Committee)
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at http://groups.google.com/group/mos-ak?hl=en.
For more options, visit https://groups.google.com/groups/opt_out.
May 1, 2013
13th HICUM Workshop 2013
Workshop Highlights:
- Special presentation by Prof. Spirito on mm-wave on-wafer measurements
- Various presentations covering the modeling of various bipolar transistor phenomena, new parameter extraction strategies, production-type model development, model testing and performance comparisons
- Special presentations on benchmark circuits for model verification (solicited)
Apr 29, 2013
[mos-ak] [press note] Spring MOS-AK/GSA Workshop in Munich; April 11-12, 2013
http://www.gsaglobal.org/2013/04/mos-akgsa-munich-workshop-press-note/
The MOS-AK/GSA Modeling Working Group is coordinating several upcoming modeling events: a special compact modeling session at the MIXDES Conference in Gdynia (https://www.mixdes.org); an autumn Q3/2013 MOS-AK/GSA workshop in Bucharest (http://www.mos-ak.org/bucharest/), a winter Q4/2013 MOS-AK/GSA meeting in Washington DC, and a spring Q2/2014 MOS-AK/GSA meeting in London (http://www.mos-ak.org).
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at http://groups.google.com/group/mos-ak?hl=en.
For more options, visit https://groups.google.com/groups/opt_out.
Apr 26, 2013
[mos-ak] BSIM6.0 is industry standard model
BSIM6 Model Home Page
BSIM-EPFL Collaboration Announcement --
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at http://groups.google.com/group/mos-ak?hl=en.
For more options, visit https://groups.google.com/groups/opt_out.
[mos-ak] [on-line publications] Spring MOS-AK/GSA Workshop in Munich; April 11-12, 2013
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at http://groups.google.com/group/mos-ak?hl=en.
For more options, visit https://groups.google.com/groups/opt_out.
Apr 24, 2013
TED Call for Papers on Compact Modeling of Emerging Devices
Please submit manuscripts by using the following URL: http://mc.manuscriptcentral.com/ted
Paper submission Deadline: June 30, 2013
Guest Editors:
Digital Object Identifier 10.1109/TED.2013.2253418
Apr 11, 2013
A single European semiconductor strategy is on its way...
At the International Semiconductor Strategy Symposium (ISS Europe), the European semiconductor industry affirmed its ability to innovate. More than 170 top industry representatives agreed on a number of joint steps and strategic measures to strengthen their competitiveness and sustainability. The controversial question whether the best way to attack future challenges will be "More Moore" or "More than Moore," ended in an expected compromise, namely that the industry should pursuit both strategies concurrently, the participants of a panel expressed. Whilst the More than Moore sector is traditionally strong in Europe, going on with More Moore is important for two to three device makers in Europe and in particular for the European equipment suppliers which export 80% of their products.
In a global scale, the semiconductor industry is approaching the move to 450mm wafer processing technology – a step that promises to greatly boost the productivity of semiconductor manufacturers. However, since the investment to build a 450mm fab easily exceeds the 10 billion dollar mark, this move is regarded as risky and, for this reason, reserved to only the very largest enterprises. In the past, this perspective divided the European industry into two camps - the "More Moore" group that advocates taking on the 450mm challenge, and the "More than Moore" group which shunned this risky investment and preferred to rely on application-oriented differentiation instead.
At the event SEMI Europe, an industry association embracing enterprises that represent the entire value chain and organizer of the ISS Europe, set up a high-ranking panel discussion on options and choices of a single European semiconductor strategy. The panel proved that entrepreneurial spirit is well alive among Europe's chipmakers, technology suppliers and researchers.
Read more...
Apr 5, 2013
[mos-ak] CMC GaN HEMT Model Standardization Effort - Call for Candidate Models
Since its inception, the Compact Model Council (CMC) has collaborated to develop, maintain, and standardize compact models for widely used semiconductor components. CMC members have decided that gallium nitride (GaN) technology is important for their business and the CMC intends to develop its first standard GaN HEMT transistor model. More information about the CMC can be found in the attached document. The ability for the model to generalize from GaN to other III-V FETs would be a bonus but is not a requirement. After the CMC evaluates and standardizes a model for GaN HEMTs, the CMC may decide to extend this effort to all III-V FET/HEMT devices. We are currently soliciting candidate models for this standard.
GaN transistors are high electron mobility transistors (HEMTs), a FET technology based on a heterojunction channel and a Schottky / Insulated / Junction (pGaN) gate. The primary applications for GaN transistors are for high voltage / high power devices to be used as for example as switches; and for high frequency / high power devices to be used for example in RF power amplifiers.
The CMC plans a three-phase process for identification and evaluation of candidate models. We currently have started Phase I which is a solicitation of available models which meet the fundamental requirements set forth in the attached Requirements Document. The GaN Subcommittee will review written proposals and request top candidates to present an overview of their model at a CMC Meeting. Candidates identified in Phase I which have sufficient support from CMC sponsors will be subjected to thorough testing in subsequent Phases. All developers submitting a proposed standard to CMC for adoption will read and accept the CMC Standard Model Copyright Policy.
The attached document lists the model requirements and various types of measurements that the model must reproduce. They include IV curves over various bias and temperature conditions, high frequency measurements, switching measurements, and time dependent measurements to characterize trapping effects. The attached check-list should be used to identify which requirements are or will be met by the candidate model.
After a set of candidate models is obtained, Phase II starts with a set of measured data against which the models will be evaluated. This technology has not yet been decided. At this point the CMC will need brief documentation outlining the list of measurements and the data. The details of how the GaN devices are being fabricated, nor the details of their internal structure, will be required. A minimum set of device physical dimensions would be needed in order to feed candidate models with meaningful parameters, such as channel length, channel width, gate to source/drain contact distance, etc. The CMC GaN FET subcommittee will review the proposed measurement data and will determine which data set(s) will be used for model evaluation. It is possible that data from more than one source will be retained for the model evaluation, to cover an as wide as possible range of applications.
If you are aware of any organization willing to contribute, please forward this document, or contact the GaN FET subcommittee chair, Samuel Mertens (samuel_mertens(at)agilent.com). Don't hesitate to ask me any questions about the standardization process or the CMC.
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at http://groups.google.com/group/mos-ak?hl=en.
For more options, visit https://groups.google.com/groups/opt_out.
Apr 3, 2013
[mos-ak] [Final Program] Spring MOS-AK/GSA Workshop in Munich; April 11-12, 2013
April 11 | Thursday, Afternoon Session |
13:00 - 16:00 | Oral presentations |
Welcome and Workshop Opening Wladek Grabinski; MOS-AK | |
Statistical modeling with backward propagation of variance (BPV) and covariance equations Klaus-Willi Pieper and Elmar Gondro; Infineon Technologies | |
Circuit Sizing: Corner Models Challenges & Applications Matthias Sylvester; MunEDA (D) | |
Compact Modeling Activities in The Framework of the EU-Funded "COMON" Project Benjamin Iñiguez; URV, Tarragona (SP) | |
Effective Device Modeling And Verification Tools Ingo Nickeleit; Agilent Technologies | |
16:00 - 17:00 | Software/Hardware Demos |
MunEDA Framework Applications Tanner TSpice Verilog-A Agilent B1505A Power Device Analyzer / Curve Tracer | |
Networking Evening Event | |
April 12 | Friday, Sessions |
9:00 - 12:00 | Morning Oral Presentations |
Institute for Technical Electronics (LTE) Presentation Prof. Dr. rer. nat. Doris Schmitt-Landsiedel, LTE, TUM (D) | |
STEEPER: Tunnel Field Effect Transistors (TFETs) Technology, Devices and Applications Thomas Schulz and Reinhard Mahnkopf, Intel, IMC, (D) | |
Current and Future Challenges for TCAD Christoph Jungemann and Christoph Zimmermann; RWTH Aachen University (D) | |
Advances in Verilog-A Compact Semiconductor Device Modeling with Qucs/QucsStudio Mike Brinson; London Metropolitan University, London, UK | |
12:00 - 13:00 | Lunch |
13:00 - 16:00 | Afternoon Oral Presentations |
FDSOI Devices Bentchmarking Bich-Yen Nguyen; SOITEC (F) | |
COMON: SOI Multigate Devices Modeling Alexander Kloes; THM (D) | |
COMON: FinFET Modeling Activities Udit Monga; Intel, IMC, (D) | |
COMON: HV MOS Devices Modeling Matthias Bucher; TUC, (GR) | |
End of the Workshop |
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at http://groups.google.com/group/mos-ak?hl=en.
For more options, visit https://groups.google.com/groups/opt_out.