Wednesday, 3 April 2013

[mos-ak] [Final Program] Spring MOS-AK/GSA Workshop in Munich; April 11-12, 2013

Together with the workshop host, Prof. Dr. Doris Schmitt-Landsiedel, Lehrstuhl fur Technische Elektronik, TUM and Extended MOS-AK/GSA TPC Committee and the workshop sponsors MunEDA and Tanner EDA as well as the IEEE EDS Chapter Germany, the technical program cosponsor, we have pleasure to invite to the spring MOS-AK/GSA Workshop in Munich 

Venue:
Lehrstuhl fur Technische Elektronik
Room: 5325, 5th floor <http://www.lte.ei.tum.de/index.html>
Technische Universitat Munchen 
Arcisstr. 21 D-80333 Munchen

MOS-AK/GSA Workshop Agenda

April 11 Thursday, Afternoon Session 
13:00 - 16:00
 Oral presentations

Welcome and Workshop Opening
Wladek Grabinski; MOS-AK

Statistical modeling with backward propagation of variance (BPV) and covariance equations
Klaus-Willi Pieper and Elmar Gondro; Infineon Technologies

Circuit Sizing: Corner Models Challenges & Applications
Matthias Sylvester; MunEDA (D)

Compact Modeling Activities in The Framework of the EU-Funded "COMON" Project
Benjamin IƱiguez; URV, Tarragona (SP)

Effective Device Modeling And Verification Tools
Ingo Nickeleit; Agilent Technologies
16:00 - 17:00
 Software/Hardware Demos

MunEDA Framework Applications
Tanner TSpice Verilog-A
Agilent B1505A Power Device Analyzer / Curve Tracer

Networking Evening Event
April 12 Friday, Sessions
9:00 - 12:00
 Morning Oral Presentations

Institute for Technical Electronics (LTE) Presentation 
Prof. Dr. rer. nat. Doris Schmitt-Landsiedel, LTE, TUM (D)

STEEPER: Tunnel Field Effect Transistors (TFETs) Technology, Devices and Applications 
Thomas Schulz and Reinhard Mahnkopf, Intel, IMC, (D)

Current and Future Challenges for TCAD
Christoph Jungemann and Christoph Zimmermann; RWTH Aachen University (D)

Advances in Verilog-A Compact Semiconductor Device Modeling with Qucs/QucsStudio
Mike Brinson; London Metropolitan University, London, UK
12:00 - 13:00
 Lunch
13:00 - 16:00 Afternoon Oral Presentations

FDSOI Devices Bentchmarking
Bich-Yen Nguyen; SOITEC (F)

COMON: SOI Multigate Devices Modeling
Alexander Kloes; THM (D)

COMON: FinFET Modeling Activities 
Udit Monga; Intel, IMC, (D)

COMON: HV MOS Devices Modeling
Matthias Bucher; TUC, (GR)
 End of the Workshop

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