[virtual] ToM2020/2 Announcement

ToM2020/2 Course

September, 8th, 2020
    14.00-17.30    Danilo Gerna (Melexis Technologies), “Advanced Hall Element Based Magnetic Sensors Front End Design”

September, 9th, 2020
    9.00-12.30    Carlo Samori (Milan Politechnic), “PLL: From Analog to Digital and Recent Trends”
    14.00-17.30    Alex Tranca (Infineon), “Robust Design of Smart Power ICs for Automotive Applications, with Focus on Load Current Sensing”

September, 10th, 2020
    9.00-12.30    Alfio Dario Grasso (Univ. Catania), “Ultra-Low Power Amplifiers for IoT Nodes”
    14.00-17.30    Gabriella Ghidini (STMicroelectronics), “Dielectric Reliability in Microelectronics”

In this particular situation, the PhD School at University of Milan-Bicocca decided to fully support the costs of the ToM2020/2 course, whose participation will then be free-of-charge for the attendees. However, for proper managing internet access to the virtual ToM2020/2 course, registration is mandatory at the following website:
http://www.innotechevents.com/index.php?page=ToM/RegistrationForm.html

Only registered participants will receive access information for the course.
At the end of the course, an exam will be proposed for certifying the positive attendance (please register to the exam with the course registration).
We look forward to virtually meeting you !!!!

More information at:
http://www.innotechevents.com/index.php?page=ToM/ToM.html

[virtual] IEEE EDS DL Mini-Colloquium at MIXDES Wroclaw

EDS Distinguished Lecturer Mini-Colloquium 

"Semiconductor-based sensors - technology, modeling, applications" 

(virtual at MIXDES), June 27, 2020

Chairs: Wladek Grabinski, Daniel Tomaszewski

10.00-10.45	Arokia Nathan "Ultralow Power, High-Resolution Sensor Interfaces" EDS Distinguished Lecturer, Cambridge Touch Technologies, UK; E-mail: an299@cam.ac.uk
10.45-11.30	Mike Schwarz "Sensor Design – From Prototype to Series" Robert Bosch GmbH, 72703 Reutlingen,Germany; E-mail: Mike.Schwarz@de.bosch.com
12.00-12.45	Benjamin Iñíguez "Compact Modeling and Parameter Extraction for Oxide and Organic Thin Film Transistors (TFTs) from 150K to 350K" EDS Distinguished Lecturer, Department of Electrical, Electronics Engineering and Automatic Control Engineering, Universitat Rovira i Virgili, 43007 Tarragona, Spain; E-mail: benjamin.iniguez@urv.cat
12.45-13.30	Teoder Gotszalk " Microsystem Electronics and Photonics " Faculty of Microsystem Electronics and Photonics, Wroclaw University of Technology, Poland; E-mail: teodor.gotszalk@pwr.edu.pl
13.30-14.15	Mina Rais-Zadeh "Phase change electro-optical devices for space applications" (recorded) EDS Distinguished Lecturer, NASA Jet Propulsion Lab., California Institute of Techn., USA; E-mail: minar@umich.edu

#SilTerra - #MEMS Technology Roadmap https://t.co/X0g0M0ImoL #paper https://t.co/n0Nthns32a

#SilTerra - #MEMS Technology Roadmap https://t.co/X0g0M0ImoL #paper pic.twitter.com/n0Nthns32a

— Wladek Grabinski (@wladek60) June 19, 2020

from Twitter https://twitter.com/wladek60

June 19, 2020 at 10:29AM
via IFTTT

[Short Course] Modeling and Simulation of Nano-Transistors

Short Course

Modeling and Simulation of Nano-Transistors

6 - 10 July 2020 at Outreach Auditorium,IIT Kanpur

http://www.iitk.ac.in/nanolab/sc2020/

by Prof. Yogesh S. Chauhan

Nanolab, IIT Kanpur

http://home.iitk.ac.in/~chauhan/

Aim: VLSI design will soon use transistors whose size will be as small as 10nm. The aim of this short course is to educate and train bright minds on different aspects of Nano-transistors. Modeling especially compact modeling is the heart of circuit simulation. TCAD simulations are used for early device design and to understand the internal physics of transistor. Electrical characterization includes current and capacitance voltage measurement of transistor. RF measurement is an exciting area which involves understanding of devices as well as high frequency effects. This short course will cover various topics in modeling, simulation and characterization of transistors especially at nanoscale.

Topics: (1) VLSI design and Nanoelectronics, (2) Physics and Operation of MOSFET, (3) SPICE and Circuit simulation, (4) TCAD simulation: Theory and demonstration, (5) Compact Modeling: Theory and demonstration, (6) Scaling and Moore's Law, (7) Nano-Transistors: FinFET, FDSOI, Negative Capacitance FET, Nanosheet FETs, 2D-FETs etc. (8) Characterization: Current and capacitance measurement, (9) RF CMOS and GaN High Electron Mobility Transistors

Hands-on Sessions: (1) Verilog-A coding, (2) SPICE ckt. Simulation, (3) TCAD Simulation, (4) Parameter Extraction

Coordinator: Prof. Yogesh S. Chauhan Dept. of Electrical Engg., IIT Kanpur

Registration: This short course has been postponed to end of this year or early next year due to ongoing pandemic. New Dates will be announced once normalcy returns in the country.

A Benchmark Study Of Complementary-Field Effect Transistor (#FET) Process Integration Options: Comparing #Bulk vs. #SOI vs. DSOI Starting Substrates https://t.co/rYE24rym7L #paper https://t.co/T3ECdVJa5c

A Benchmark Study Of Complementary-Field Effect Transistor (#FET) Process Integration Options: Comparing #Bulk vs. #SOI vs. DSOI Starting Substrates https://t.co/rYE24rym7L #paper pic.twitter.com/T3ECdVJa5c

— Wladek Grabinski (@wladek60) June 17, 2020

from Twitter https://twitter.com/wladek60

June 17, 2020 at 05:02PM
via IFTTT

[paper] CV of Graphene–Silicon Heterojunction Photodiodes

Sarah Riazimehr,  Melkamu Belete,  Satender Kataria,  Olof Engström and Max Christian Lemme

Capacitance–Voltage (C –V) Characterization 

of Graphene–Silicon Heterojunction Photodiodes

Advanced Optical Materials 

First Published Open Access: 07 May 2020

DOI: 10.1002/adom.202000169

Abstract: Heterostructures of 2D and 3D materials form efficient devices for utilizing the properties of both classes of materials. Graphene/silicon (G/Si) Schottky diodes have been studied extensively with respect to their optoelectronic properties. Here, a method to analyze measured capacitance–voltage (C –V) data of G/Si Schottky diodes connected in parallel with G/silicon dioxide/Si (GIS) capacitors is introduced. The accurate extraction of the built‐in potential (Φbi) and the Schottky barrier height (SBH) from the measurement data independent of the Richardson constant is also demonstrated.

Figure 2

Fig.: a) Cross section of the test device showing both MIS and GIS regions. b) Small‐signal C –V characteristics of Dtest (line) compared to a theoretically calculated C –V curve (dashed ) at 10 kHz.

Acknowledgements: Financial support from the European Commission (Graphene Flagship, 785219, 881603) and the German Ministry of Education and Research, BMBF (GIMMIK, 03XP0210) is gratefully acknowledged.

[paper] Compact Model for Ferroelectric FET

Lu, Darsen, Sourav De, Mohammad Aftab Baig, Bo-Han Qiu, and Yao-Jen Lee

Computationally efficient compact model for ferroelectric field-effect transistors 

to simulate the online training of neural networks

Semiconductor Science and Technology (2020)

DOI: 10.1088/1361-6641/ab9bed

Abstract: In this paper, a compact drain current formulation that is simple and adequately computationally efficient for the simulation of neural network online training was developed for the ferroelectric memory transistor. Tri-gate ferroelectric field effect transistors (FETs) with Hf0.5Zr0.5O2 gate insulators were fabricated with a gate-first high-k metal gate CMOS process. Ferroelectric switching was confirmed with double sweep and pulse programming and erasure measurements. Novel characterization scheme for drain current was proposed with minimal alteration of ferroelectric state in subthreshold for accurate threshold voltage measurements. The resultant threshold voltage exhibited highly linear and symmetric across multilevel states. The proposed compact formulation accurately captured the FET gate-bias dependence by considering the effects of series resistance, Coulomb scattering, and vertical field dependent mobility degradation.

Fig.: Transmission electron micrograph of the fabricated tri-gate Fe

finFET device across the fin, with approximately 60 nm fin width, 30 nm fin

height, and 10 nm HZO Fe layer.

Acknowledgements: This work was jointly supported by the Ministry of Science and Technology (Taiwan) grant MOST–108–2634–F–006–08 and is part of research work by MOST’s AI Biomedical Research Center. We are grateful to the Taiwan Semiconductor Research Institute for nanofabrication facilities and services and to Dr. Wen-Jay Lee and Nan-Yow Chen of the National Center for High-Performance Computing for helpful suggestions on AI computation. This manuscript was edited by Wallace Academic Editing.

#Samsung #MOSIS Collaboration https://t.co/IOrXK5W1Y8 #paper https://t.co/VXZqf03bmY

#Samsung #MOSIS Collaboration https://t.co/IOrXK5W1Y8 #paper pic.twitter.com/VXZqf03bmY

— Wladek Grabinski (@wladek60) June 17, 2020

from Twitter https://twitter.com/wladek60

June 17, 2020 at 09:14AM
via IFTTT

Learning with brain chemistry https://t.co/UJRbFdHuUh #paper https://t.co/PB4Ty0moUg

Learning with brain chemistry https://t.co/UJRbFdHuUh #paper pic.twitter.com/PB4Ty0moUg

— Wladek Grabinski (@wladek60) June 16, 2020

from Twitter https://twitter.com/wladek60

June 16, 2020 at 05:39PM
via IFTTT

#GNU #Health #Embedded #OpenSource Health Platform Works on Raspberry Pi 3/4, and soon Olimex SBC's https://t.co/mIXu3NfQPy https://t.co/I0tkTqXijs

#GNU #Health #Embedded #OpenSource Health Platform Works on Raspberry Pi 3/4, and soon Olimex SBC's https://t.co/mIXu3NfQPy pic.twitter.com/I0tkTqXijs

— Wladek Grabinski (@wladek60) June 16, 2020

from Twitter https://twitter.com/wladek60

June 16, 2020 at 04:46PM
via IFTTT

[paper] TFT Compact Modeling

Arun Dev Dhar Dwivedi, Sushil Kumar Jain, Rajeev Dhar Dwivedi and Shubham Dadhich

Numerical Simulation and Compact Modeling 

of Thin Film Transistors for Future Flexible Electronics

Submitted: July 4th 2019Reviewed: October 28th 2019Published: June 10th 2020

DOI: 10.5772/intechopen.90301

Abstract: In this chapter, we present a finite element method (FEM)-based numerical device simulation of low-voltage DNTT-based organic thin film transistor (OTFT) by considering field-dependent mobility model and double-peak Gaussian density of states model. Device simulation model is able to reproduce output characteristics in linear and saturation region and transfer characteristics below and above threshold region. We also demonstrate an approach for compact modeling and compact model parameter extraction of organic thin film transistors (OTFTs) using universal organic TFT (UOTFT) model by comparing the compact modeling results with the experimental results. Results obtained from technology computer-aided design (TCAD) simulation and compact modeling are compared and contrasted with experimental results. Further we present simulations of voltage transfer characteristic (VTC) plot of polymer P-channel thin film transistor (PTFT)-based inverter to assess the compact model against simple logic circuit simulation using SmartSpice and Gateway.

Fig.: Schematic cross-sectional diagram of organic TFTs 

along with the chemical structure of SAM and organic semiconductor.

Acknowledgments: The authors are thankful to SERB, DST, Government of India, for the financial support under Early Career Research Award (ECRA) for Project No. ECR/2017/000179.

#Intel’s #10nm Node: Past, Present, and Future [EETimes] https://t.co/P3Fi3xUogJ #paper https://t.co/QoFX5z22br

#Intel’s #10nm Node: Past, Present, and Future [EETimes] https://t.co/P3Fi3xUogJ #paper pic.twitter.com/QoFX5z22br

— Wladek Grabinski (@wladek60) June 16, 2020

from Twitter https://twitter.com/wladek60

June 16, 2020 at 02:31PM
via IFTTT

[slides] (Ultra-) Wide-Bandgap Devices

(Ultra-) Wide-Bandgap Devices: Reshaping the Power Electronics Landscape

Presenter Dr. Yuhao Zhang, Assistant Professor,
Center for Power Electronics Systems, Virginia Tech

IEEE EDS SCV-SF Seminar 

Friday, June 12, 2020 at 12PM – 1PM PDT

Abstract: Power electronics is the application of solid-state electronics for the control and processing of electrical energy. It is used ubiquitously in consumer electronics, electric vehicles, data centers, renewable energy systems, and smart grid. The power semiconductor device, as the cornerstone technology in power electronics, is key to improving the efficiency, cost and form factor of power electronic systems.  Recently, the power electronics landscape has been significantly reshaped with the production and application of power devices based on wide-bandgap (WBG) semiconductors, such as gallium nitride (GaN) and silicon carbide (SiC). Besides advancing the performance of traditional power systems, WBG devices have also enabled many emerging applications that are beyond the realm of silicon (Si) as well as changed the manufacturing paradigm of power electronics. On the horizon is the power devices based on ultra-wide-bandgap (UWBG) materials, which promises superior performance over GaN and SiC and is at the relatively early stage of research development.  This talk will provide a comprehensive overview of major WBG and UWBG power device technologies, spanning materials, devices, reliability and applications. Some research projects in the PI’s group in collaboration with industry will also be introduced.

FIG: WBG Semiconductor: Superior Power Semiconductor Over Si

The seminar presentation is now available on our IEEE EDS SCV-SF webpage:
http://site.ieee.org/scv-eds/files/2020/06/SCV_SF_EDS_Yuhao_Zhang_excerpt.pdf

More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page. Subscribe or Invite your friends to sign up for our mailing list and get to hear about exciting electron-device relevant talks. We, EDS SCV-SF, promise no spam and try to minimize email. You can (un)subscribe easily.

[paper] Future of Ultra-Low Power SOTB CMOS

Nobuyuki Sugii¹, Shiro Kamohara², Makoto Ikeda³

The Future of Ultra-Low Power SOTB CMOS Technology and Applications

NANO-CHIPS 2030. The Frontiers Collection. Springer, Cham

DOI: 10.1007/978-3-030-18338-7_6

1.Hitachi, Ltd.Tokyo, Japan
2.Renesas Electronics Corp.Tokyo, Japan
3.The University of Tokyo, Japan

Abstract: Ultra-low power technology has drawn much attention recently as the number of connecting (Internet-of-Things) devices rapidly increases. The silicon-on-thin-buried oxide (SOTB) technology is a CMOS device technology that uses fully depleted silicon-on-insulator (FDSOI) transistors with a thin buried oxide layer enabling enhanced back-bias controllability and that can be monolithically integrated with the conventional bulk CMOS circuits. It can significantly reduce both the operation and the standby powers by taking advantage of low-voltage operation and back-biasing, respectively. In this chapter, advantages of the SOTB technology in terms of ultra-low power, circuits design and chip implementation examples including ultra-low power micro-controllers operating with harvested power, reconfigurable logic circuits, analog circuits, are reviewed, and a future perspective is shown.

Fig.: Schematic cross section of SOTB transistors. Hybrid bulk transistors are shown. SOTB  transistors are used in low-voltage (< ~1.5 V) logic and analog circuits including SRAMs. Bulk  transistors are used in peripheral, ESD-protection, high-voltage analog and power circuits, on-chip,  flash memory, and reuse of legacy circuits

Acknowledgements: The part of the work, especially on developing the SOTB technology by the Low-power Electronics Association and Project (LEAP), is supported by the Ministry of Economy, Trade and Industry (METI) and the New Energy and Industrial Technology Development Organization (NEDO). Part of the chip fabrication by the universities is done under a support of VLSI Design and Education Center (VDEC) in collaboration with Renesas Electronics Corporation, Cadence Corporation, Synopsys Corporation and Mentor Graphics Corporation.

IEEE PS Webinar "G2V and V2G Technologies in Electric Vehicles"

IEEE Photonics Society Student Chapter of Mangalam College of Engineering is geared up with webinar series to provoke the little spark in you

• Date:16-06-2020
• Time:10:30 - 11:30 AM IST
• Pre registration link: https://bit.ly/3dTeDzP
• Topic: G2V and V2G Technologies in Electric Vehicles
• Speaker: Dr.Sreejith.S; Assistant Professor,
  Department of Electrical Engineering,
  National Institute of Technology, Silchar, Assam

We, IEEE Photonics Society Student Chapter, invite you all to join this webinar and take away some useful stuffs in this quarentine. Registration free!!! See you there. All registered participants are honoured with e-certificates

Webinar Link: https://bit.ly/2ZgJuBY
For further queries contact our coordinators:
Alsufiyan   : +91 7736598136
Nandhu : +91 9061383258

Stay Safe, Enjoy learning!! Stay updated with us for more exciting events!...

[paper] Organic Permeable Base Transistors

Darbandy, G., Dollinger, F., Formánek, P., Hübner, R., Resch, S., Roemer, C., Fischer, A., Leo, K., Kloes, A., Kleemann, H., 

Unraveling Structure and Device Operation of Organic Permeable Base Transistors

Adv. Electron. Mater. 2020, 2000230 

DOI 10.1002/aelm.202000230

Abstract: Organic permeable base transistors (OPBTs) are of great interest for flexible electronic circuits, as they offer very large on‐current density and a record‐high transition frequency. They rely on a vertical device architecture with current transport through native pinholes in a central base electrode. This study investigates the impact of pinhole density and pinhole diameter on the DC device performance in OPBTs based on experimental data and TCAD simulation results. A pinhole density of N Pin = 54 µm−2 and pinhole diameters around L Pin = 15 nm are found in the devices. Simulations show that a variation of pinhole diameter and density around these numbers has only a minor impact on the DC device characteristics. A variation of the pinhole diameter and density by up to 100% lead to a deviation of less than 4% in threshold voltage, on/off current ratio, and subthreshold slope. Hence, the fabrication of OPBTs with reliable device characteristics is possible regardless of statistical deviations in thin film formation.

Fig.: Device stack of an OPBT. The central base electrode is permeable to electrons. The device current flows between emitter and collector, while the base layer is passivated by an oxide layer.

The device current can be modulated by the base‐emitter voltage V_BE

Acknowledgements: G.D. and F.D. contributed equally to this work. This project was funded by the German Research Foundation (DFG) under the grants KL 1042/9‐2 and LE 747/52‐2 (SPP FFlexCom) and by the European Community’s Seventh Framework Programme under Grant Agreement No. FP7‐267995 (NUDEV). This work was supported in part by the German Research Foundation (DFG) within the Cluster of Excellence Center for Advancing Electronics Dresden (cfaed) and the DFG project HEFOS (Grant No. FI 2449/1‐1). Furthermore, the use of HZDR Ion Beam Center TEM facilities and the funding of TEM Talos by the German Federal Ministry of Education of Research (BMBF; grant No. 03SF0451) in the frame‐work of HEMCP are acknowledged. The authors thank Tobias Günther and Andreas Wendel of IAPP for sample preparation.

[paper] GaN/AlGaN 2DEGs grown on bulk GaN

Luisa Krückeberg¹,  Steffen Wirth²,  Victor V. Solovyev³, Andreas Großer¹, Igor V. Kukushkin^3,4,  Thomas Mikolajick^1,5, and  Stefan Schmult⁵

Quantum and transport lifetimes in optically induced GaN/AlGaN 2DEGs

grown on bulk GaN

Journal of Vacuum Science and Technology B 38, 042203 (2020)

DOI: 10.1116/1.5145198

¹NaMLab GmbH, Dresden (D)
²Max-Planck-Institute for Chemical Physics of Solids, Dresden (D)
³Institute of Solid State Physics RAS, Moscow (RU)
⁴National Research University Higher School of Economics, Moscow (RU)
⁵Institute of Semiconductors and Microsystems, TU Dresden, Dresden (D)

ABSTRACT A two-dimensional electron gas (2DEG) is absent in ultrapure GaN/Al0.06Ga0.94N heterostructures grown by molecular beam epitaxy on bulk GaN at 300 K and in the dark. However, such a 2DEG can be generated by UV illumination and persists at low temperature after blanking the light. Under steady UV illumination as well as under persistence conditions, pronounced quantum transport with Shubnikov–de Haas oscillations commencing below 2 T is observed. The low temperature 2DEG mobility amounts to only ∼20 000 cm2/V s, which is much lower than predicted for the dominant scattering mechanisms in GaN/AlGaN heterostructures grown on GaN with low threading dislocation density. A rather small ratio of the transport and quantum lifetimes τt/τq of ∼10 points at elastic scattering events limiting both the transport and quantum lifetimes.

FIG. (a) Photograph of a Hall bar device and (b) its two-terminal resistance R2pt at stabilized temperatures between 120 and 135K. The estimated UV power during illumination is in the low nanowatts range, which does not result in a saturation of R2pt at these specific temperatures. The recombination time, i.e., the time until disappearance of the 2DEG, increases significantly at 120K. At 100 K, no increase in R2pt is observed after switching off the illumination.

ACKNOWLEDGMENTS The NaMLab gGmbH part was financially supported by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation)—Project No. 405782347, the German Federal Ministry of Education and Research—BMBF (Project “ZweiGaN,” No. 16ES0145K), and the German Federal Ministry of Economics and Technology—BMWi (Project No. 03ET1398B). V.V.S. and I.V.K. acknowledge the support from the Russian Science Foundation (Grant No. 19-42-04119). The TU Dresden part of the work was partially funded by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation)—Project No. 348524434.

[paper] Nanowire gate-all-around MOSFETs modeling

Cheng, He, Tiefeng Liu, Chao Zhang, Zhijia Yang, Zhifeng Liu, Kazuo Nakazato

and Zhipeng Zhang

Nanowire gate-all-around MOSFETs modeling:

ballistic transport incorporating the source-to-drain tunneling

Japanese Journal of Applied Physics (2020)

Accepted Manuscript online 5 June 2020

DOI: 10.35848/1347-4065/ab99db

Abstract: Incorporating the source-to-drain tunneling current valid in all operating regions, an analytical compact model is proposed for cylindrical ballistic GAA-nMOSFETs with ultra-short Silicon channel. From taking the DIBL effect into consideration, the potential distribution within the device channel has been modeled based upon a 2-D analysis in our previous work. In this study, by introducing a parabolic function when modeling the potential profile in the channel direction, we found out that the source-to-drain tunneling effect in the subthreshold region could be evaluated analytically by applying WKB approximation. Then, it is practical to estimate the drain current for all operating regions analytically with this compact model considering both the source-to-drain tunneling and thermionic transport. The resulting analytic compact model is tested against NEGF simulation using SILVACO, and good accuracy is demonstrated. Finally, we perform an NMOS inverter circuit simulation using HSPICE, introducing our model to it as a Verilog-A script.

Fig: Rough sketch of the potential energy profile along the channel and illustration of mechanisms governing the carrier transport in ballistic tunneling and thermionic modes.
(a) Representation of energy levels distribution along the z-direction at the channel center (r = 0).
(b) Schematics of confinement potential energy distribution along r-component at the barrier top (z = zMAX) in the cross section. The elementary charge stands for letter e. 

Acknowledgment: The authors would like to thank Prof. S. Uno for his support to this work. This work has been supported by the science and technology program of Liaoning, the major industrial projects (Grant No. 2019JH1/1010022

Virtual Education Events at ESSDERC/ESSCIRC 2020

Given this uncertain situation, the organizing committee of ESSDERC/ESSCIRC 2020 in Grenoble and its Steering Committee, have decided to propose a new format for coming conference, which will include a NEW and Virtual Education Event series being developed for September 14th 2020 consisting of 13 educational sessions (workshops and tutorial) comprising invited presentations by leading academic and industrial experts and technologists. All related technical program details are also available online: https://www.esscirc-essderc2020.org/educationals

1. TUTORIAL | Quantum Computing: Myth or Reality?

Chairs: M. Vinet (CEA) and Farhana Sheikh (Intel)
Full content duration ~6h

2. WORKSHOP | Emerging Solutions for Imaging Devices, Circuits and Systems

Chairs: Matteo Perenzoni (FBK) and Albert Theuwissen (Harvest Imaging)
Full content duration ~6h

3. WORKSHOP | Non-Volatile Memories: Opportunities and Challenges from Devices to Systems

Chairs: Gabriel Molas (CEA) and Mahmut Sinangil (TSMC)
Full content duration ~6h

4. WORKSHOP | New 5G integration solutions, and related technologies (from materials to system)

Chairs: Nadine Collaert (imec) and Stefan G. Andersson (Ericsson)
Full content duration ~6h

5. WORKSHOP | Advances in device technologies for automotive industry (power devices, SiC, GaN)

Chairs: Ionut Radu (Soitec) and Stefaan Decoutere (IMEC)
Full content duration ~6h

6. WORKSHOP | Embedded monitoring and compensation design for energy or safety constrained applications

Chairs: Sylvain Clerc (ST) and Keith Bowman (Qualcomm)
Full content duration ~4h

7. WORKSHOP | Edge AI and In-Memory-Computing for energy efficient AIoT solutions​

Chairs:  Andreas Burg (EPFL) and Marian Verhelst (KUL)
Full content duration ~6h

8. WORKSHOP | Ab-initio simulations supporting new materials & process developments

Chairs: Denis Rideau (ST) and Philippe Blaise (Silvaco)
Full content duration ~3h

9. WORKSHOP | RISC-V cooking session

Chairs: Bora Nikolic (BWRC)
Full content duration ~3h

10. DISSEMINATION WORKSHOP |  Toward sustainable IOT from rare materials to big data

Chairs:  Thierry Baron (CEA, LTM/UGA) and Audrey Dieudonné (UGA)
Full content duration ~3h

11. DISSEMINATION WORKSHOP | High Density 3D CMOS Mixed-Signal Opportunities

Chair: Philipp Häfliger (UiO)
Full content duration ~3h

12. MOS-AK WORKSHOP | Compact/SPICE Modeling and its Verilog-A Standardization

Chair: Wladek Grabinski (MOS-AK) and Daniel Tomaszewski (ITE Warsaw)
Full content duration ~6h

13. IPCEI on Microelectronics: Innovative Technologies for Shaping the Future

Chairs: Dominique Thomas (ST), Klaus Pressel (Infineon), Rainer Pforr (Zeiss)
Full content duration ~6h

2020 IEEE ED Poland Chapter MQ

Date

2020-06-26

Location

Virtual

Region

IEEE Region 8 (Europe, Middle East and Africa)

Contact

Krzysztof Górecki – k.gorecki@we.am.gdynia.pl

Description

Distinguished Lecturer

Arokia Nathan - Oxide Electronics Univ. Cambridge (UK)

Mina Rais-Zadeh - MEMS development at JPL (US)

Benjamin Iniguez - Universitat Rovira i Virgili, Tarragona (SP)

Teodor Gotszalk - TU Wrocław (PL)

Mike Schwarz - MEMS Design & Simulation, Bosch (D)

REGISTER at the MQ site
https://eds.ieee.org/education/distinguished-lecturer-mini-colloquia-program/upcoming-dl-and-mq-events?eid=731&m=10e18da593444dc0cb20a2f377717f95

[paper] NESS

Nano-electronic Simulation Software (NESS): 

a flexible nano-device simulation platform

Salim Berrada, Hamilton Carrillo-Nunez, Jaehyun Lee, Cristina Medina-Bailon, Tapas Dutta, Oves Badami, Fikru Adamu-Lema, Vasanthan Thirunavukkarasu, Vihar Georgiev and Asen Asenov 

Journal of Computational Electronics (2020)

DOI: 10.1007/s10825-020-01519-0

Abstract: The aim of this paper is to present a flexible and open-source multi-scale simulation software which has been developed by the Device Modelling Group at the University of Glasgow to study the charge transport in contemporary ultra-scaled Nano-CMOS devices. The name of this new simulation environment is Nano-electronic Simulation Software (NESS). Overall NESS is designed to be flexible, easy to use and extendable. Its main two modules are the structure generator and the numerical solvers module. The structure generator creates the geometry of the devices, defines the materials in each region of the simulation domain and includes eventually sources of statistical variability. The charge transport models and corresponding equations are implemented within the numerical solvers module and solved self-consistently with Poisson equation. Currently, NESS contains a drift–diffusion, Kubo–Greenwood, and non-equilibrium Green’s function (NEGF) solvers. The NEGF solver is the most important transport solver in the current version of NESS. Therefore, this paper is primarily focused on the description of the NEGF methodology and theory. It also provides comparison with the rest of the transport solvers implemented in NESS. The NEGF module in NESS can solve transport problems in the ballistic limit or including electron–phonon scattering. It also contains the Flietner model to compute the band-to-band tunneling current in heterostructures with a direct band gap. Both the structure generator and solvers are linked in NESS to supporting modules such as effective mass extractor and materials database. Simulation results are outputted in text or vtk format in order to be easily visualized and analyzed using 2D and 3D plots. The ultimate goal is for NESS to become open-source, flexible and easy to use TCAD simulation environment which can be used by researchers in both academia and industry and will facilitate collaborative software development.

FIG: Flowchart of NESS detailing its modular structure

NESS will be released in the summer of 2020 as an open-source software which makes it very interesting for both academia and industry in helping to address the challenges subsequent to the further down-scaling of CMOS components.

Acknowledgements: This work was supported by the European Union’s Horizon 2020 research and innovation programme under Grant Agreement No. 688101 SUPERAID7. Also, this project has received funding from EPSRC UKRI under Grant Agreements No. EP/S001131/1 (QSEE) and No. EP/P009972/1 (QUANTDEVMOD).

Semi-talk: Low Cost Photonics | Dr. Naresh Chand, Life Fellow of IEEE, Associate Vice President, Chapter Relations of the IEEE Photonics Society https://t.co/mQkIAGoI51 #paper https://t.co/zmPh8QDa3F

Semi-talk: Low Cost Photonics | Dr. Naresh Chand, Life Fellow of IEEE, Associate Vice President, Chapter Relations of the IEEE Photonics Society https://t.co/mQkIAGoI51#paper pic.twitter.com/zmPh8QDa3F

— Wladek Grabinski (@wladek60) June 8, 2020

from Twitter https://twitter.com/wladek60

June 08, 2020 at 09:52AM
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The Simplest #Microwave #Receiver https://t.co/atbhia4ZZy #paper https://t.co/WZDsDvXeoD

The Simplest #Microwave #Receiver https://t.co/atbhia4ZZy #paper pic.twitter.com/WZDsDvXeoD

— Wladek Grabinski (@wladek60) June 8, 2020

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June 08, 2020 at 09:16AM
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[paper] Electrostatically doped drain engineered DG‐TFET

Shaikh, MRU, Loan, SA, Alshahrani, A.
Electrostatically doped drain engineered DG‐TFET:
Proposal and Analysis
IJNM 2020;e2769
DOI: 10.1002/jnm.2769

Abstract: In this paper, a drain‐engineered double‐gate Tunnel‐FET (DE‐DG‐TFET) to enhance the electrical characteristics and analog parameters of a conventional DG‐TFET is proposed and examined through calibrated TCAD simulations. Unlike DG‐TFET, a constant n‐type doping, N_cd, (5E17 cm⁻³ − 2E18 cm⁻³), in the channel/drain regions of DE‐DG‐TFET is used, resulting in a p+‐n‐n structure instead of conventional p+‐i‐n structure. Further, p+‐n‐n is modified to p+‐n‐n+ using electrostatic doping (ED) method on the drain side with Hafnium (ϕ_m = 3.9 eV) as a lateral (top and bottom) and side metal electrode. A high n+‐drain doping ensures the drain contact remains ohmic. Higher electric field at p+‐n source‐channel junction enhances the ON‐state BTBT current. While the absence of metallurgical junction provides large tunneling width across the channel/drain junction, resulting in suppression of ambipolar current (I_AMB). At N_cd doping of 1E18 cm⁻³, DE‐DG‐TFET demonstrates ~7 times increase in I_ON while I_AMB is suppressed by ~5 orders of magnitude. In addition to this, the proposed device improves analog/RF figures of merit, 45% in voltage gain and ~5 times in peak f_T.

FIG: Key steps for fabrication of the proposed DEDG-TFET

Acknowledgement: This work was supported by Ministry of Electronics & Information Technology (MeitY), Government of India through Visvesvaraya PhD Scheme.

Reading about #OpenSource in French https://t.co/A5lXEvoSOL https://t.co/OjByvKO4la

Reading about #OpenSource in French https://t.co/A5lXEvoSOL pic.twitter.com/OjByvKO4la

— Wladek Grabinski (@wladek60) June 5, 2020

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[paper] Large-signal behavioral model for RF power transistors

Cai J, King J, Liu J, Wang J, Sun L.
Large-signal behavioral model for radio frequency power transistors 

based on modified canonical sectionwise piecewise-linear functions

IJNM 2020;e2767
DOI: 10.1002/jnm.2767

Abstract: A novel, large-signal behavioral modeling methodology for radio frequency power transistors, based on the modified canonical sectionwise piecewiselinear (CSWPL) functions, is presented in this article. The basic theory of the proposed model is provided. Compared with the existing standard CSWPL model, the proposed model provides superior prediction capabilities for a reasonable increase in model complexity. Model verification is performed through comparisons with simulated and experimental data of a 10 W GaN HEMT device at mild and severe mismatch conditions, across a wide range of input power levels. The models can predict, more accurately, both the fundamental and the second harmonic scattered waves compared with the standard CSWPL model.

Fig: Comparison between circuit, CSWPL model, and proposed modified CSWPL model, when the available input power is 5dBm, the number of partitions K=J=3, and the number of Fourier terms L=3

Correspondence: Jialin Cai, The Key Laboratory of RF Circuit and System, Ministry of Education, Hangzhou Dianzi University, Hangzhou, CN

[paper] Unified Analytical Transregional MOSFET Model

Kalra, S, Bhattacharyya, AB. 

A Unified Analytical Transregional MOSFET Model for Nanoscale CMOS Digital Technologies

Int J Numer Model. 2020; 33:e2700

https://doi.org/10.1002/jnm.2700

Abstract: For IC designers, power has always been the main design constraint. Near threshold (moderate inversion) computing is a promising technique to manage power and energy requirements. A modeling framework specific to moderate inversion is developed in literature known as Transregional Mosfet Model (TRM). This paper presents an extension of TRM model by considering the lateral and vertical field dependent mobility of carriers that make it suitable for circuit design at supply voltages not restricted to near threshold voltage. The model proposed is the unified model applicable in all operating regions (weak, moderate, and strong) and all saturation levels from a long channel with negligible effect of velocity saturation to a short channel having extreme velocity saturation. Further, it has been shown that the proposed drain current model can be reduced to unified interpolated expression of EKV model for long channel MOSFET.

FIG: Comparison of (A) proposed model, (B) weak inversion approximation, (C) strong inversion approximation, with transregional MOSFET model (TRM) and BSIM4 at 22nm technology node. 

[paper] On-Wafer FinFET-Based EUV/eBeam Detector Arrays

Wang, Chien-Ping, Yi-Pei Tsai, Burn Jeng Lin, Zheng-Yong Liang, Po-Wen Chiu, Jiaw-Ren Shih, Chrong Jung Lin, and Ya-Chin King

On-Wafer FinFET-Based EUV/eBeam Detector Arrays for Advanced Lithography Processes

IEEE TED (2020)

Abstract: A novel microdetector array (MDA) for monitoring electron beam (eBeam) and extreme ultraviolet (EUV) lithography processes in 5 nm and beyond FinFET technology is first-time presented. This on-wafer detector array consists of high-density sensing cells which are fully compatible with standard FinFET CMOS processes. Fin coupling structures and energy-sensing pads are first applied in an ultrasmall detector for realizing efficient eBeam and EUV photon detection. In advanced lithography process, eBeam or EUV level projected on the wafer can be precisely recorded on the on-wafer MDA without power or batteries. The distributions and variations on the beam intensities collected by MDA can be electrically measured in real time or inline through wafer level test after eBeam or EUV exposures. The proposed MDA is expected to provide real-time feedback for the optimization and stable maintenance of advanced photolithography processed critical to the development nanometer CMOS technologies.

FIG: (a) Schematic of lithography system and (b) 3-D illustration of unit detector cell of the MDA consisting of ESP and FG on the shallow trench isolation (STI) region.

Acknowledgment: The authors gratefully acknowledge the contributions of Taiwan Semiconductor Manufacturing Company (TSMC) and Ministry of Science and Technology (MOST), Taiwan (Project Number: MOST 108-2622-8-007-017).

IEEE EDS Delhi Chapter DL: FOSS TCAD/EDA tools for Compact/SPICE Modeling

The IEEE EDS Delhi Chapter, New Delhi, India is conducting a series of the IEEE EDS DL Talks with coming one on June 03, 2020 at 06:00 pm (GMT+05:30, IST)  with following topic:

FOSS TCAD/EDA tools for Compact/SPICE Modeling

Wladek Grabinski 

Senior Member-IEEE MOS-AK Association (EU)

Abstract: Compact/SPICE models of circuit elements (passive, active, MEMS, RF) are essential to enable advanced IC design using nanoscaled semiconductor technologies. Compact/SPICE models are also a communication means between the semiconductor foundries and the IC design teams to share and exchange all engineering and design information. To explore all related interactions, we are discussing selected FOSS CAD tools along complete technology/design tool chain from nanascaled technology processes; thru the MOSFET, FDSOI, FinFET and TFET compact modeling; to advanced IC transistor level design support. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, we will present two FOSS CAD simulation and design tools: ngspice and Qucs. Application and use of these tools for advanced IC design (e.g. analog/RF IC applications) directly depends on the quality of the compact models implementations in these tools as well as reliability of extracted models and generated libraries/PDKs. Discussing new model implementation into the FOSS CAD tools (Gnucap, Xyce, ngspice and Qucs as well as others) we will also address an open question of the compact/SPICE model Verilog-A standardization. We hope that this presentation will be useful to all the researchers and engineers actively involved in the developing compact/SPICE models as well as designing the integrated circuits in particular at the transistor level and then trigger further discussion on the compact/SPICE model Verilog-A standardization to encourage development FOSS CAD tools. 

And the webinar has drawn attention of 150+ online participants

The series of the IEEE EDS DLs are coordinated by:

Professor Mridula Gupta

Chairperson-IEEE EDS Delhi Chapter

Professor & Head of Department of Electronic Science 

University of Delhi South Campus

New Delhi 110021INDIA

Professor  Manoj Saxena

Regional Editor for South Asia, IEEE EDS Newsletter

EDS Distinguished Lecturer and Fellow-IETE, India

Associate Professor, Department of Electronics 

Deen Dayal Upadhyaya College, University of Delhi 

Dwarka Sector-3, New Delhi-110078, India 

Webinars by IEEE Photonics Society Student Chapter

The IEEE Photonics Society Student Chapter of Mangalam College of Engineering has organized a series of the webinars to take away some useful stuffs during current COVID-19 quarantine. The webinar #5 was on:

FOSS TCAD/EDA Tools for Semiconductor Device Modeling

Dr. Wladyslaw Grabinski  

MOS-AK Association   

[paper] TID Effects in SOI FinFETs

Bias and geometry dependence of total-ionizing-dose effects in SOI FinFETs

Zhexuan Ren¹, Xia An¹, Gensong Li¹, Runsheng Wang¹, Nuo Xu², Xing Zhang¹ and Ru Huang¹

¹Institute of Microelectronics, Peking University, Beijing 100871, CN

²Department of Electrical Engineering and Computer Sciences, UCB, CA 94720, USA

Semiconductor Science and Technology, Volume 35, Number 7

Abstract: In this paper, a systematic research on the total-ionizing-dose (TID) effects of NMOS and PMOS silicon-on-insulator (SOI) FinFETs is performed experimentally. The bias and geometry dependence of TID effects are analysed. The experimental results show that the threshold voltage (Vth) shift occurs in SOI FinFETs after x-ray irradiation. After 1 Mrad (Si) irradiation, the maximum Vth shift is about 40 mV. The 'worst case' irradiation bias conditions for NMOS and PMOS are TG and ON states, respectively, which induces the largest Vth shift after irradiation. The 3D TCAD simulation is carried out to further analyse the bias dependence results. Simulation results highlight the difference in electric field distribution in the buried oxide under different bias configurations, which leads to different distribution of irradiation-induced trapped charges. Finally, clear geometry dependence is observed in the TID experiment. Both NMOS and PMOS devices with larger fin width and/or smaller gate length are more sensitive to TID irradiation. The results deepen the understanding of the TID effect of SOI FinFETs and provide important technical support for the radiation-hardened research of FinFET technology.

Figure: (a) SOI NMOS FinFET in 3D TCAD software with Z-cut in BOX layer. Simulated electric field distribution in Z-cut plane for OFF (b), ON (c) and TG (d) bias conditions. The white dashed box in figure (b), (c), (d) indicates the relative position of the channel region.

Acknowledgments: This work was supported in part by the National Natural Science Foundation of China (No.61421005, 61434007) and 111 Project (B18001). The authors would like to thank the staff of the Xinjiang Technical Institute of Physics and Chemistry (XTIPC), Chinese Academy of Sciences (CAS) for their assistance in the TID irradiation experiment.

[paper] In-memory hyperdimensional computing

In-memory hyperdimensional computing

Geethan Karunaratne, Manuel Le Gallo, Giovanni Cherubini, Luca Benini, Abbas Rahimi

and Abu Sebastian 

Nature Electronics (2020)

DOI: 10.1038/s41928-020-0410-3

Abstract: Hyperdimensional computing is an emerging computational framework that takes inspiration from attributes of neuronal circuits including hyperdimensionality, fully distributed holographic representation and (pseudo)randomness. When employed for machine learning tasks, such as learning and classification, the framework involves manipulation and comparison of large patterns within memory. A key attribute of hyperdimensional computing is its robustness to the imperfections associated with the computational substrates on which it is implemented. It is therefore particularly amenable to emerging non-von Neumann approaches such as in-memory computing, where the physical attributes of nanoscale memristive devices are exploited to perform computation. Here, we report a complete in-memory hyperdimensional computing system in which all operations are implemented on two memristive crossbar engines together with peripheral digital complementary metal–oxide–semiconductor (CMOS) circuits. Our approach can achieve a near-optimum trade-off between design complexity and classification accuracy based on three prototypical hyperdimensional computing-related learning tasks: language classification, news classification and hand gesture recognition from electromyography signals. Experiments using 760,000 phase-change memory devices performing analog in-memory computing achieve comparable accuracies to software implementations.

Fig.: The concept of in-memory hyperdimensional computing.

Acknowledgements: This work was supported in part by the European Research Council through the European Union’s Horizon 2020 Research and Innovation Programme under grant no. 682675 and in part by the European Union’s Horizon 2020 Research and Innovation Programme through the project MNEMOSENE under grant no. 780215.

[paper] Device Scaling for 3-nm Node and Beyond

Opportunities in Device Scaling for 3-nm Node and Beyond:

FinFET Versus GAA-FET Versus UFET

U. K. Das and T. K. Bhattacharyya

in IEEE TED, vol. 67, no. 6, pp. 2633-2638, June 2020, 

doi: 10.1109/TED.2020.2987139

Abstract: The performances of FinFET, gate-all-around (GAA) nanowire/nanosheet, and U-shaped FETs (UFETs) are studied targeting the 3-nm node (N3) and beyond CMOS dimensions. To accommodate a contacted gate pitch (CGP) of 32 nm and below, the gate length is scaled down to 14 nm and beyond. While going from 5-nm node (N5) to 3-nm node (N3) dimensions, the GAA-lateral nanosheet (LNS) shows 8% reduction in the effective drain current (I_eff) due to an enormous rise in short channel effects, such as subthreshold slope (SS) and drain-induced barrier lowering (DIBL). On the other hand, 5-nm diameter-based lateral nanowire shows an 80% rise in I_eff. Therefore, to enable future devices, we explored electrostatics and I_eff in FinFET, GAA-FET, and UFET architectures at a scaled dimension. The performances of both Si- and SiGe-based transistors are compared using an advanced TCAD device simulator.

Fig: Transistor architectures for future technologies. (a) FinFET device

(in {001} substrate plane, and sidewalls are in {110} planes) with crosssectional

fin channel (5 nm thin). (b) Fin is changed into a four-stacked

GAA-LNWs. (c) GAA- LNS having 20-nm width (W). (d) UFET structure.

Acknowledgment: The authors would like to thank Dr. Bidhan Pramanik, IIT Goa, India, Dr. KB Jinesh, IIST, Trivandrum, India, and Dr. Geert Eneman, IMEC, Leuven, Belgium, for their valuable technical support.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9078841&isnumber=9098120

#US putting $37bn into #semiconductors. The aim is to match #China in its state investment in semiconductors. https://t.co/jJ6adDEiSE #paper https://t.co/pHv5mcyi6m

#US putting $37bn into #semiconductors. The aim is to match #China in its state investment in semiconductors. https://t.co/jJ6adDEiSE #paper pic.twitter.com/pHv5mcyi6m

— Wladek Grabinski (@wladek60) June 1, 2020

from Twitter https://twitter.com/wladek60

June 01, 2020 at 08:59AM
via IFTTT

#DISLIN Graphics Library to plot S- and Y-parameters on Smith Charts, and to create arbitrary Cartesian plots of S-parameter data along with Polar plots of radiation patterns. https://t.co/Fj7CEHywUv #paper https://t.co/A0cRlYw3uH

#DISLIN Graphics Library to plot S- and Y-parameters on Smith Charts, and to create arbitrary Cartesian plots of S-parameter data along with Polar plots of radiation patterns. https://t.co/Fj7CEHywUv#paper pic.twitter.com/A0cRlYw3uH

— Wladek Grabinski (@wladek60) May 31, 2020

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May 31, 2020 at 09:55PM
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[paper] ReRAM: History, Status, and Future

ReRAM: History, Status, and Future

Y. Chen, Member, IEEE

Western Digital Corporation, Milpitas, CA

in IEEE TED, vol. 67, no. 4, pp. 1420-1433, April 2020

doi: 10.1109/TED.2019.2961505.

Abstract: This article reviews the resistive random-access memory (ReRAM) technology initialization back in the 1960s and its heavily focused research and development from the early 2000s. This review goes through various oxygen/oxygen vacancy and metal-ion-based ReRAM devices and their operation mechanisms. This review also benchmarks the performance of various oxygen/oxygen vacancy and metal-ion-based ReRAM devices with general trend drawn. Being a semiconductor memory and storage technology, the commercialization attempts for both stand-alone mass storage/storage-class memory and embedded nonvolatile memory are also reviewed. Looking toward the coming era, the potential of using ReRAM technology to improve machine learning efficiency is discussed. 

Fig: General category of resistive switching memory technologies

with ReRAM highlighted as the review focus

Acknowledgment: Sincere acknowledgment to people who ever contribute to ReRAM technology development and understanding.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8961211&isnumber=9046113

What Rhymes With #SPICE And Simulates Huge Circuits? https://t.co/RGyWLKVDzS #paper https://t.co/trzKPb8w2A

What Rhymes With #SPICE And Simulates Huge Circuits?https://t.co/RGyWLKVDzS#paper pic.twitter.com/trzKPb8w2A

— Wladek Grabinski (@wladek60) May 29, 2020

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May 29, 2020 at 03:58PM
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Open PhD and Post-Doc positions at BIU

Dr. Adam Teman is a tenure track Senior Lecturer at Bar-Ilan University in Ramat Gan, Israel and a leading member of the Emerging Nanoscaled Circuits and Systems (EnICS) Labs at BIU. Dr.Temen is also among  the Woolf Foundation's 2020 Krill Award winners for young Israeli researchers. Dr.Teman is looking now for candidates for PhD and Post-Doc positions. Please contact him at adam.teman@biu.ac.il 

Dr. Adam Teman Research IC Tapeouts

• 2019 - SoC2 System-on-Chip (TSMC 16FFC)
• 2018 - Kwak Gain Cell eDRAM T(Samsung 28nm FD-SOI)
• 2017 - Martini Gain Cell eDRAM (ST 28nm FD-SOI)
• 2016 - BEER Gain Cell eDRAM (ST 28nm FD-SOI)
• 2016 - DAFNA Gain Cell eDRAM (TSMC 28nm)

#Kioxia has a paper on #ferroelectric #RAM. The symposia have gone virtual in 2020 and take place June 15 to 19 https://t.co/k0wo1wGRzk #paper https://t.co/9cSMZCh3cv

#Kioxia has a paper on #ferroelectric #RAM. The symposia have gone virtual in 2020 and take place June 15 to 19https://t.co/k0wo1wGRzk#paper pic.twitter.com/9cSMZCh3cv

— Wladek Grabinski (@wladek60) May 27, 2020

from Twitter https://twitter.com/wladek60

May 27, 2020 at 06:04PM
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