[paper] SPICE PCM Model

A SPICE Model of Phase Change Memory for Neuromorphic Circuits

Xuhui Chen¹, Huifang Hu¹, Xiaoqing Huang¹, Weiran Cai², Ming Liu³ (Fellow, Ieee), Chung Lam⁴,  Xinnan Lin¹ (Member, IEEE), Lining Zhang⁵ (Senior Member, IEEE)

and Mansun Chan⁶ (Fellow, IEEE)

¹The Shenzhen Key Lab of Advanced Electron Device and Integration, ECE, Peking University Shenzhen Graduate School, Shenzhen 518055 CN
²Institute of Microscale Optoelectronics, Shenzhen University, Shenzhen 518061 CN
³Key Laboratory of Microelectronics Devices and Integration Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, and the University of Chinese Academy of Sciences, Beijing 100049 CN
⁴Jiangsu Advanced Memory Technology Co., Ltd, Huaian 223302 CN
⁵School of Electronic and Computer Engineering, Peking University, Shenzhen 518055, CN
⁶HKUST Shenzhen Research Institute, Shenzhen 518057, China, and Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, HK

doi: 10.1109/ACCESS.2020.2995907

Abstract: A phase change memory (PCM) model suitable for neuromorphic circuit simulations is developed. A crystallization ratio module is used to track the memory state in the SET process, and an active region radius module is developed to track the continuously varying amorphous region in the RESET process. To converge the simulations with bi-stable memory states, a predictive filament module is proposed using a previous state in iterations of nonlinear circuit matrix under a voltage-driven mode. Both DC and transient analysis are successfully converged in circuits with voltage sources. The spiking-timedependent- plasticity (STDP) characteristics essential for synaptic PCM are successfully reproduced with SPICE simulations verifying the model’s promising applications in neuromorphic circuit designs. Further on, the developed PCM model is applied to propose a neuron circuit topology with lateral inhibitions which is more bionic and capable of distinguishing fuzzy memories. Finally, unsupervised learning of handwritten digits on neuromorphic circuits is simulated to verify the integrity of models in a large-scale-integration circuits. For the first time in literature an emerging memory model is developed and applied successfully in neuromorphic circuit designs, and the model is applicable to flexible designs of neuron circuits for further performance improvements. 

FIG: Schematic diagram of commonly used PCM mushroom structure

URL: https://IEEExplore.IEEE.org/stamp/stamp.jsp?tp=&arnumber=9097232&isnumber=6514899

[paper] Graphene/4H-SiC/Graphene MSM UV-photodetector

An optimized Graphene/4H-SiC/Graphene MSM UV-photodetector operating
in a wide range of temperature 

H. Bencherif ¹, L. Dehimi1 ², G. Messina ³, P. Vincent ⁴, F. Pezzimenti ³, F. G. Della Corte ^{3 1}Laboratory of Metallic and Semiconductor Materials, University of Biskra, Biskra, DZ

²Faculty of Science, University of Batna 1, DZ

³DIIES, Mediterranea University of Reggio Calabria, Reggio Calabria, IT

⁴School of Electronics Engineering, KNU, 80 Daehakro, Buk-gu, Daegu, 702-701, KP

Abstract: In this paper, .an accurate analytical model has been developed to optimize the performance of an Interdigitated Graphene Electrode/p-silicon carbide (IGE/p-4H-SiC) Metal semiconductor Metal (MSM) photodetector operating in a wide range of temperatures. The proposed model considers different carrier loss mechanisms and can reproduce the experimental results well. An overall assessment of the electrodes geometrical parameters’ influence on the device sensitivity and speed performances was executed. Our results confirm the excellent ability of the suggested Graphene electrode system to decrease the unwanted shadowing effect. A responsivity of 238 μA/W was obtained under 325-nm illumination compared to the 16.7 μA/W for the conventional Cr-Pd/p-SiC PD. A photocurrent to- dark-current ratio (PDCR) of 5.75 × 105 at 300K and 270 at 500K was distinguished. The response time was found to be around 14 μs at 300K and 54.5 μs at 500K. Furthermore, the developed model serves as a fitness function for the multi objective optimization (MOGA) approach. The optimized IGE/p-4H-SiC MSM-PD design not only exhibits higher performance in terms of PDCR (7.2×105), responsivity (430A/cm2) and detectivity (1.3×1014 Jones) but also balances the compromise between ultrasensitive and high-speed figures of merit with a response time of 4.7 μs. Therefore, the proposed methodology permits to realize ultra-sensitive, high-speed SiC optoelectronic devices for extremely high temperature applications. 

FIG: a) Energy band diagram of Graphene/p-SiC/Graphene structure, b) Cross-sectional view of the suggested IGE/4H-SiC MSM UV-PD with interdigitated electrodes

Acknowledgments: This work was supported by DGRSDT Of Ministry of Higher education of Algeria. The work was done in the unit of research of materials and renewable energies (URMER).

Open Science Idea

Open Science Idea

2020 TEDxSkoltech Moscow

[full pdf: https://sci-hub.tw/alexandra/works/skoltech.pdf]

Talk  by Александра Элбакян, the Sci-Hub creator, at the TEDx conference at Uni Skoltech. The text transcript is given with  slides. All the video recording of that performance has been removed from TED website as the organizers referred to the fact that it violated some TED rules.

[PhD] Printed Inorganic Materials Electronics

Circuit Design and Compact Modeling in Printed Electronics Based on Inorganic Materials

PhD Dissertation

Gabriel Cadilha Marques

Veröffentlicht am 30.04.2020

DOI: 10.5445/IR/1000118801

Abstract - The goal of this thesis is therefore to develop an inorganic printed electronics technology with corresponding modeling methodologies to capture device behavior for industry standard circuit simulators as well as circuit designs as building blocks for future applications. To reduce the high supply voltage requirements (~5V) in PE, alternative gating approaches for FETs are considered. One approach is to replace the dielectric with an electrolyte. Due to the formation of a Helmholtz double layer (HDL), a FET with a high gate-capacitance (~5 μFcm-2) is expected, reducing the voltage requirements to ~1V. By combining the indium oxide channel with the electrolyte-gating approach, high performance devices with low voltage requirements are available in PE.

[paper] Polymer Electrodes in Clinical EEG and MEG

Laura M. Ferrari, Usein Ismailov, Jean-Michel Badier, Francesco Greco and Esma Ismailova 

Conducting polymer tattoo electrodes in clinical electro- and magneto-encephalography

npj Flex Electron 4, 4 (2020)
Received: 17 October 2019; Accepted: 20 February 2020;

DOI: 10.1038/s41528-020-0067-z

Abstract - Temporary tattoo electrodes are the most recent development in the field of cutaneous sensors. They have successfully demonstrated their performances in the monitoring of various electrophysiological signals on the skin. These epidermal electronic devices offer a conformal and imperceptible contact with the wearer while enabling good quality recordings over time. Evaluations of brain activity in clinical practice face multiple limitations, where such electrodes can provide realistic technological solutions and increase diagnostics efficiency. Here we present the performance of inkjet-printed conducting polymer tattoo electrodes in clinical electroencephalography and their compatibility with magnetoencephalography. The working mechanism of these dry sensors is investigated through the modeling of the skin/electrode impedance for better understanding of the biosignals transduction at this interface. Furthermore, a custom-made skin phantom platform demonstrates the feasibility of high-density recordings, which are essential in localizing neuropathological activities. These evaluations provide valuable input for the successful application of these ultrathin electronic tattoos sensors in multimodal brain monitoring and diagnosis.

Fig: Temporary tattoo electrodes (TTEs) for EEG: a The layered structure of the temporary tattoo paper permits the release of the top film on which electrodes are fabricated. b Expanded view of an all-polymer printed TTE. c A TTE released on the scalp, in Oz position. d Close-in view of a TTE released on the scalp after 12 h from application. e Impedance recordings on the forearm using TTE and Ag/AgCl electrodes. 

Experiments involving human participants -Two able-bodied participants (one male and one female aged 33.5 ± 3.5 years old) free of any motor and neural disorders gave their informed consent and participated in this study. One participant performed the impedance recordings with the three diverse TTEs sets while another participant volunteered in the EEG/MEG evaluations with TTEs and Ag/AgCl electrodes. All experiments are performed following Timone hospital’s regulations regarding personal data protection. The experiment was conducted under conditions provided by French regulations.

Data Availability - The experimental data referenced in this text is available from the authors upon reasonable request.

#EU Parliament Strongly Recommends Developing and Using #opensource Software https://t.co/6HxdUaUHQK https://t.co/7czSKFmwh7

#EU Parliament Strongly Recommends Developing and Using #opensource Software https://t.co/6HxdUaUHQK pic.twitter.com/7czSKFmwh7

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[paper] Novel Design and Optimization and the gm/ID Ratio

A Novel Design and Optimization Approach for Low Noise Amplifiers (LNA) Based on MOST Scattering Parameters and the gm/ID Ratio

Juan L. Castagnola¹*, Fortunato C. Dualibe² Agustín M. Laprovitta¹ and Hugo García-Vázquez³

¹Facultad de Ingeniería, Universidad Católica de Córdoba, Córdoba 5017 (AN)

²Service d’Électronique et Microélectronique, Université de Mons (UMONS), 7000 Mons (BE)

³Departamento de Electrónica, Instituto de Astrofísica de Canarias (IAC), 38200 La Laguna (SP)

* Author to whom correspondence should be addressed.

Electronics 2020, 9(5), 785; https://doi.org/10.3390/electronics9050785

Received: 31 March 2020 / Revised: 30 April 2020 

Accepted: 9 May 2020 / Published: 11 May 2020

Abstract - This work presents a new design methodology for radio frequency (RF) integrated circuits based on a unified analysis of the scattering parameters of the circuit and the gm/ID ratio of the involved transistors. Since the scattering parameters of the circuits are parameterized by means of the physical characteristics of transistors, designers can optimize transistor size and biasing to comply with the circuit specifications given in terms of S-parameters. A complete design of a cascode low noise amplifier (LNA) in 65nm CMOS technology is taken as a case study in order to validate the approach. In addition, this methodology permits the identification of the best trade-off between the minimum noise figure and the maximum gain for the LNA in a very simple way.

Figure: gm/ID versus iD

Acknowledgement - This research was funded by Universidad Católica de Córdoba (Argentina), the Walloon Region DGO6 BEWARE Fellowships Academia Programme (1410164-POHAR, cofunded by the European Marie Curie Actions), the Belgian FNRS (Fond National pour la Recherche Scientifique) and the Argentinean MINCyT (Ministerio de Ciencia y Tecnología).

[paper] Electrical characterization of advanced MOSFETs

Valeriya Kilchytska, Sergej Makovejev, Babak Kazemi Esfeh, Lucas Nyssens, Arka Halder,

Jean-Pierre Raskin and Denis Flandre

Electrical characterization of advanced MOSFETs towards analog and RF applications

IEEE LAEDC, San Jose, Costa Rica, 2020, 

doi: 10.1109/LAEDC49063.2020.9073536

Abstract - This invited paper reviews main approaches in the electrical characterization of advanced MOSFETs towards their target analog and RF applications. Advantages and necessity of those techniques will be demonstrated on different study cases of various advanced MOSFETs, such as FDSOI, FinFET, NW in a wide temperature range, based on our original research over the last years. 

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9073536&isnumber=9072949

Acknowledgements - This work was partially funded by Eniac “Places2Be”, Ecsel “Waytogofast”, FNRS - FRFC “Towards Highly-efficient 10 nm MOSFETs”, FP7 “Nanosil” and “Nanofunction” projects. The authors thank our colleagues from CEA-Leti, ST and Imec, and particularly, F. Andrieu, O. Faynot, T. Poiroux, S. Barraud, M. Haond, N. Planes, N. Collaert, C. Claeys, M. Jurczak, B. Parvais, R. Rooyackers, for providing UTBB FD SOI, NW and FinFET devices and valuable discussions.

#Linux not #Windows: Why #Munich is shifting back from Microsoft to #opensource ...again https://t.co/7kCWSVHIOk https://t.co/KVPAvUZr8o

#Linux not #Windows: Why #Munich is shifting back from Microsoft to #opensource ...again https://t.co/7kCWSVHIOk pic.twitter.com/KVPAvUZr8o

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#paper: Smith, A.F., Liu, X., Woodard, T.L. et al. #Bioelectronic protein nanowire sensors for ammonia detection. Nano Res. (2020) https://t.co/eTvrtblGS0 A new, highly sensitive #chemical #sensor uses protein nanowires https://t.co/lj2MoELcLp https://t.co/03cHA6MNIc

#paper: Smith, A.F., Liu, X., Woodard, T.L. et al. #Bioelectronic protein nanowire sensors for ammonia detection. Nano Res. (2020)https://t.co/eTvrtblGS0
A new, highly sensitive #chemical #sensor uses protein nanowires https://t.co/lj2MoELcLp pic.twitter.com/03cHA6MNIc

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#OpenRAMAN: #OpenSource Raman Spectrometer Is Cheaper, But Not Cheap https://t.co/SAKV61rdou https://t.co/SotKelrOVK

#OpenRAMAN: #OpenSource Raman Spectrometer Is Cheaper, But Not Cheap https://t.co/SAKV61rdou pic.twitter.com/SotKelrOVK

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[paper] Computing-in-Memory

Computing-in-Memory for Performance and Energy Efficient Homomorphic Encryption

Dayane Reis, Student Member, IEEE, Jonathan Takeshita, Taeho Jung, Member, IEEE, Michael Niemier, Senior Member, IEEE and Xiaobo Sharon Hu, Fellow, IEEE

preprint arXiv:2005.03002 (2020).

Abstract - Homomorphic encryption (HE) allows direct computations on encrypted data. Despite numerous research efforts, the practicality of HE schemes remains to be demonstrated. In this regard, the enormous size of ciphertexts involved in HE computations degrades computational efficiency. Near-memory Processing (NMP) and Computing-in-memory (CiM) — paradigms where computation is done within the memory boundaries — represent architectural solutions for reducing latency and energy associated with data transfers in data-intensive applications such as HE. This paper introduces CiM-HE, a Computing-in-memory (CiM) architecture that can support operations for the B/FV scheme, a somewhat homomorphic encryption scheme for general computation. CiM-HE hardware consists of customized peripherals such as sense amplifiers, adders, bit-shifters, and sequencing circuits. The peripherals are based on CMOS technology, and could support computations with memory cells of different technologies. Circuit-level simulations are used to evaluate our CiM-HE framework assuming a 6T-SRAM memory. We compare our CiM-HE implementation against (i) two optimized CPU HE implementations, and (ii) an FPGA-based HE accelerator implementation.When compared to a CPU solution, CiM-HE obtains speedups between 4.6x and 9.1x, and energy savings between 266.4x and 532.8x for homomorphic multiplications (the most expensive HE operation). Also, a set of four end-toend tasks, i.e., mean, variance, linear regression, and inference are up to 1.1x, 7.7x, 7.1x, and 7.5x faster (and 301.1x, 404.6x, 532.3x, and 532.8x more energy efficient). Compared to CPUbased HE in a previous work, CiM-HE obtain 14.3x speed-up and >2600x energy savings. Finally,our design offers 2.2x speed-up with 88.1x energy savings compared to a state-of-the-art FPGAbased accelerator.

Fig: Log shifter implemented in CiM-HE.

This work was supported in part by ASCENT, one of six centers in JUMP, a Semiconductor Research Corporation (SRC) program sponsored by DARPA.

Corresponding author: Xiaobo Sharon Hu, Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, IN, 46556, USA. e-mail: .

Conference Paper Reached 500 Reads

Wladek 

Wladek Grabinski, Daniel Tomaszewski, Farzan Jazaeri, Anurag Mangla, Jean-Michel Sallese, Maria-Anna Chalkiadaki, Antonios Bazigos, and Matthias Bucher

FOSS EKV 2.6 Parameter Extractor

22nd International MIXDES Conference, pp. 181-186 (2015)

Abstract: The design of advanced integrated circuits (IC) in particular for low power analog and radio-frequency (RF) application becomes more complex as the device level modeling confronting challenges in micro- and nano-meter CMOS processes. As present CMOS technologies continue geometry scaling the designers can benefit using dedicated SPICE MOSFET models and apply specific analog design methodologies. The EKV was developed especially to meet altogether the analog/RF design requirements. This paper describes a basic set of the DC parameter extraction steps for the EKV 2.6 model. The free open source software (FOSS) Profile2D tool was used to illustrate an accurate EKV 2.6 DC extraction strategy. 

[paper] BSIM-HV: High-Voltage MOSFET Model

H. Agarwal , Member, IEEE, C. Gupta , Graduate Student Member, IEEE, R. Goel , Graduate Student Member, IEEE, P. Kushwaha , Member, IEEE, Y.-K. Lin , Graduate Student Member, IEEE, M.-Y. Kao , Graduate Student Member, IEEE, J.-P. Duarte , Graduate Student Member, IEEE, H.-L. Chang , Member, IEEE, Y. S. Chauhan , Senior Member, IEEE, S. Salahuddin, Fellow, IEEE, and C. Hu, Life Fellow, IEEE

BSIM-HV: High-Voltage MOSFET Model Including Quasi-Saturation and Self-Heating Effect

IEEE TED, vol. 66, no. 10, pp. 4258-4263, Oct. 2019

doi: 10.1109/TED.2019.2933611

Abstract - A BSIM-based compact model for a high-voltage MOSFET is presented. The model uses the BSIM-BULK (formerly BSIM6) model at its core, which has been extended to include the overlap capacitance due to the drift region as well as quasi-saturation effect. The model is symmetric and continuous, is validated with the TCAD simulations and experimental 35- and 90V LDMOS and 40V VDMOS transistors, and shows excellent agreement.

FIG: Schematic of the LDMOS. Lightly doped n-region constitutes the drain. Majority of the applied drain voltage drops across this region, which protects the intrinsic transistor region from breakdown.

Manuscript received March 3, 2019; revised May 23, 2019 and July 24, 2019; accepted July 31, 2019. Date of publication August 26, 2019; date of current version September 20, 2019. This work was supported in part by the members of the Berkeley Center for Negative Capacitance Technology and the members of the Berkeley Device Modeling Center. The review of this article was arranged by Editor B. Iñiguez.

[paper] Compact Device Models for FinFET and Beyond

D. D. Lu, M. V. Dunga, A. M. Niknejad, C.Bing Hu, F.-X. Liang, W.-C. Hung, J. Lee, C.-H. Hsu
and M.-H. Chiang,

Compact device models for FinFET and beyond

ArXiv, vol. abs/2005.02580, 2020

Abstract - Compact device models play a significant role in connecting device technology and circuit design. BSIM-CMG and BSIM-IMG are industry standard compact models suited for the FinFET and UTBB technologies, respectively. Its surface potential based modeling framework and symmetry preserving properties make them suitable for both analog/RF and digital design. In the era of artificial intelligence / deep learning, compact models further enhanced our ability to explore RRAM and other NVM-based neuromorphic circuits. We have demonstrated simulation of RRAM neuromorphic circuits with Verilog-A based compact model at NCKU. Further abstraction with macromodels is performed to enable larger scale machine learning simulation.

Fig: Simulation of a novel floating - gate synaptic transistor. (a) Device structure with separate negative feedback gate (nfb) for programming and synaptic gate (sg) readout. (b) Equivalent circuit diagram for compact modeling 

Acknowledgements - The authors would like to express sincere gratitude to Chip Implementation Center (CIC), Hsinchu, Taiwan for providing SPICE simulation environment for RRAM simulations.

[PhD] Compact DC Modeling of Tunnel-FETs

Compact DC Modeling of Tunnel-FETs

November 2019

PhD Thesis of Fabian Horst 

Doctor Advisor: Profs. Benjamin Iniguez and Alexander Kloes

Abstract - In the last decade, the tunnel field-effect transistor (TFET) has gained a lot of interest and is handled as a possible successor of the conventional MOSFET technology. The current transport of a TFET is based on the band-to-band (B2B) tunneling mechanism and therefore, the subthreshold slope at room temperature can overcome the limit of 60 mV/dec. In order to describe and analyze the TFET behavior in circuit simulations, this dissertation introduces a compact DC model for double-gate TFETs. The modeling approach considers the B2B tunneling and the parasitic effect of trap-assisted tunneling (TAT) in the ON- and AMBIPOLAR-state of the TFET. It includes a 2D compact potential equation package to de-scribe the band diagram of the TFET. Based on the band diagram, the B2B tunneling and TAT current part are derived separately. In order to do so, firstly a compact expression for the tunneling length is found, which is then used together with a numerical robust Wentzel-Kramers-Brillouin (WKB) approach to calculate the tunneling probability. Afterwards, using Landauer’s tunneling equation, the tunneling generation rate is calculated and approximated to come to a closed-form expression for the current density. Further approximation of the current density by a mathematical function, compact expressions for the resulting B2B tun-neling and TAT current are achieved. The verification of the model is done with the help of TCAD Sentaurus simulation data for various simulation setups. Furthermore, the validity of the model is proven by measurements of fabricated complementary TFETs. In order to demonstrate the numerical stability and continuity as well as the flexibility, simulations of TFET-based logic circuits like a single-stage inverter or an SRAM cell are performed and analyzed. The combination of the DC model with an TFET AC model allows for a transient simulation of an 11-stage ring oscillator. 

Fig: 2D sketch of the n-type DG TFET device geometry, showing the channel thickness t ch , the channel length l ch , the gate oxide thickness tox and the length of the S/D region l sd . Source (S) and drain (D) region are highly p/n-doped with a doping concentration N s/d 

URL: http://hdl.handle.net/10803/668957

IEEE EDS DL Series by the EDS Delhi Chapter

	IEEE Electron Device Society (EDS) Delhi Chapter – India & Department of Electronic Science University of Delhi South Campus, New Delhi, India
Jointly Organizes

EDS Distinguished Lecture

(Live Session under EDS Distinguished Lecturer Program - Virtual Lectures)

Online Live Webinar Lecture Schedule (via Google Meet)

April 30, 2020 at 10:30 am (past event) High-k Dielectric and Interface Engineering for High Performance Si/Ge MOS and FinFETs	Kuei-Shu Chang-Liao Department of Engineering and System Science National Tsing Hua University, Hsinchu, Taiwan
May 01, 2020 at 10:30 am  (past event) Two-dimensional Layered Materials for Nanoelectronics	Yang Chai Associate Professor, Department of Applied Physics The Hong Kong Polytechnic University
May 05, 2020 at 01:30 pm (past event) Introducing two-dimensional layered dielectrics in solid-state micro-electronic devices	Mario Lanza Institute of Functional Nano & Soft Materials, Soochow University, Collaborative Innovation Center of Suzhou Nano Science & Technology, China
May 06, 2020 at 06:30 pm (past event) Field Effect Transistors: From MOSFET to Tunnel-FET	Joao Antonio Martino Professor at University of Sao Paulo, Brazil
May 08,2020 at 06:30 pm IST Junctionless Nanowire Transistors: Electrical Characteristics and Compact Modeling	Marcelo Antonio Pavanello Centro Universitario FEI, Department of Electrical Engineering Av. Humberto de Alencar Castelo Branco, Sao Bernardo do Campo,  Brazil
May 11, 2020 at 01:30 pm IST From CMOS to Neuromorphic Computing - A peek into the future	Maria Merlyne De Souza Department of Electronic and Electrical Engineering The University of Sheffield, United Kingdom
May 12, 2020 at 10:30 am IST Phase change electro-optical devices for space applications	Mina Rais-Zadeh Group Supervisor, Advanced Optical and Electromechanical Microsystems Group, Micro Device Laboratory, NASA JPL, Pasadena, CA
May 15, 2020 at 08:30 pm IST State-of-the-Art Silicon Very Large Scale Integrated Circuits: Industrial Face of Nanotechnology	Michael S. Shur  Electrical, Computer and Systems Engineering and Physics, Applied Physics, and Astronomy Rensselaer Polytechnic Institute
May 16, 2020 at 02:00 pm IST Transparent and Flexible Large Area Electronics	Arokia Nathan  Cambridge Touch Technologies,  University of Cambridge, United Kingdom (UK)
May 20, 2020 at 02:30 pm IST Trends and challenges in Nanoelectronics for the next decade	Elena Gnani  Department of Electrical, Electronic and Information Engineering, University of Bologna, Italy
May 22, 2020 at 07:30 pm IST Accelerating commercialization of SiC power electronics	Victor Veliadis Executive Director and CTO, Power America Professor of Electrical and Computer Engineering,  North Carolina State University
May 27, 2020 at 07:30 pm IST Advanced III-N Devices for 5G and Beyond	Patrick Fay Department of Electrical Engineering,  University of Notre Dame

More talks will be added so if you wish to attend any of these then then kindly register on:

https://docs.google.com/forms/d/e/1FAIpQLSddt6Dq53G1aK4kk_ulyUiqc0_m_Be1lXxcXYxdULhANxB09Q/viewform

Coordinated by:

Dr. Manoj Saxena, SMIEEE, FIETE, MNASc (India) EDS BoG Member (2018-2020) & EDS DL Regional Editor for South Asia, IEEE EDS Newsletter Associate Professor, Department of Electronics  Deen Dayal Upadhyaya College, University of Delhi  Dwarka Sector-3, New Delhi, India; Email: msaxena@ieee.org

Professor Mridula Gupta, SMIEEE, FIETE Chairperson-IEEE EDS Delhi Chapter Head, Department of Electronic Science University of Delhi South Campus New Delhi 110021, India Email: mridula@south.du.ac.in

[paper] A Compact Model for SiC Schottky Barrier Diodes Based on the Fundamental Current Mechanisms

J. R. Nicholls and S. Dimitrijev

Queensland Micro- and Nanotechnology Centre

School of Engineering and Built Environment

Griffith University, Brisbane, QLD 4111, Australia

A Compact Model for SiC Schottky Barrier Diodes Based on the Fundamental Current Mechanisms

IEEE Journal of the Electron Devices Society

doi: 10.1109/JEDS.2020.2991121.

Abstract - We develop a complete compact model to describe the forward current, reverse current, and capacitance of SiC Schottky barrier diodes. The model is based on the fundamental current mechanisms of thermionic emission and tunneling, and is usable over a large range of voltages, temperatures, and for a large range of device parameters. We also demonstrate good agreement with measured data. Furthermore, the development of this model outlines a methodology for transforming a tunneling equation into a compact form without numerical integration-this methodology can potentially be applied to other device structures.

Fig: (a) Structure of a Schottky barrier diode. (b) Equivalent circuit of a Schottky barrier diode, consisting of two current sources (for the forward and reverse bias currents), a shunt capacitance and a series resistance

Acknowledgement - This work was performed at the Queensland Microtechnology Facility (Griffith University), part of the Queensland node of the Australian National Fabrication Facility (ANFF), a company established under the National Collaboration Research Infrastructure Strategy to provide nanofabrication and microfabrication facilities to Australia’s researchers. 

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9081977&isnumber=6423298

[paper] Two Transistors Voltage-Measurement-Based Test Structure for Fast MOSFET Device Mismatch Characterization

J. P. M. Brito and S. Bampi

Two Transistors Voltage-Measurement-Based Test Structure 

for Fast MOSFET Device Mismatch Characterization

IEEE Transactions on Semiconductor Manufacturing

doi: 10.1109/TSM.2020.2988095

Abstract - This work presents a test structure targeted to measure MOSFET mismatches with a fast method. It relies on two single-spot voltage measurements in order to extract VTH and β/β separately. The new methodology gives a theoretical increase in the measurement speed of 30x (23.17x in practice). The coefficient of determination (R2) of the linear regression analysis is used to compare standalone transistor measurements against the new proposed methodology. The correlation in the data demonstrates values not less than 0.94 (R2≥ 0.94). The test structure can reproduce parameter correlations, and it is capable of extracting MOSFET mismatch design parameters, such as Pelgrom’s AVTH, with an error of 2% and Aβ, with a negligible error. The experimental data presented herein are taken from measurements in prototypes fabricated in a 65nm CMOS bulk process. The whole circuit is composed of 16 2D addressable DUT device matrices, each having 256 same-size closely-placed MOSFET devices, totaling 4,096 MOS devices used in single-type (NMOS) transistor array. 

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9068274&isnumber=5159394

[paper] reached 2000 reads at ResearchGate

Grabiński, Władysław, Daniel Tomaszewski, Laurent Lemaitre, and Andrzej Jakubowski

Standardization of the compact model coding: non-fully depleted SOI MOSFET example

Journal of Telecommunications and Information Technology (2005): 135-141.

Abstract - The initiative to standardize compact (SPICE-like) modelling has recently gained momentum in the semiconduc-tor industry. Some of the important issues of the compact modelling must be addressed, such as accuracy, testing, avail-ability, version control, verification and validation. Most com-pact models developed in the past did not account for these key issues which are of highest importance when introducing a new compact model to the semiconductor industry in par-ticular going beyond the ITRS roadmap technological 100 nm node. An important application for non-fully depleted SOI technology is high performance microprocessors, other high speed logic chips, as well as analogue RF circuits. The IC de-sign process requires a compact model that describes in detail the electrical characteristics of SOI MOSFET transistors. In this paper a non-fully depleted SOI MOSFET model and its Verilog-AMS description will be presented. 

Fig: Approximation of the distribution of currents components

in the non-fully depleted SOI MOSFET.  

Keywords: Verilog-AMS, compact model coding, SOI MOSFET.

References:

1. ITRS Roadmap Update, 2003, http://www.public.itrs.net
2. Open Verilog International, "Verilog-AMS, Language Reference Manual", Version 1.9, 1999, http://www.accellera.org/
3. D. Tomaszewski, "Consistent DC and AC models of non-fully depleted SOI MOSFETS in strong inversion", in Proc. 9th Int. Conf. Mix.-Sig. Des. Integr. Cir. Syst. MIXDES, Wrocław, Poland, 2002, pp. 111-114.
4. L. Lemaitre, C. McAndrew, and S. Hamm, "ADMS - automatic device model synthesizer", in Proc. IEEE CICC 2002, Florida, USA, 2002, pp. 27-30.
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[paper] Memory Technology – A Primer for Material Scientists.

Schenk, Tony, Milan Pesic, Stefan Slesazeck, Uwe Schroeder, and Thomas Mikolajick

Memory Technology–A Primer for Material Scientists

Reports on Progress in Physics (2020)

Abstract - From our own experience in the group, we know that there is quite a gap to bridge between scientists focused on basic material research and their counterparts in a close-to-application community focused on identifying and solving final technological and engineering challenges. In this review, we try to provide an easy-to-grasp introduction to the field of memory technology for materials scientists. As an understanding of the big picture is vital, we first provide an overview about the development and architecture of memories as part of a computer and point out some basic limitations that all memories are subject to. As any new technology has to compete with mature existing solutions on the market, today's mainstream memories are explained and the need for future solutions is highlighted. The most prominent contenders in the field of emerging memories are introduced and major challenges on their way to commercialization are elucidated. Based on these discussions, we derive some predictions for the memory market to conclude the paper.

TABLE OF CONTENTS

1. INTRODUCTION
2. OVERVIEW AND BASIC LIMITATIONS
3. COMMERCIALLY AVAILABLE MAINSTREAM MEMORIES

3.1. Static and Dynamic Random Access Memory (SRAM/DRAM)
3.2. Flash Memory and Solid-State Drive (SSD)
3.3. Magnetic Hard Disk Drives (HDD) and Magnetic Tapes
3.4. Outlook: Market Trends and Drivers

4. EMERGING MEMORIES

4.1. Resistance-based Read-out: Memory Concepts and Basic Considerations
4.2. Anion migration or valence change memory (VCM)
4.3. Cation migration or electrochemical metallization memory (ECM)
4.4. Phase change memory (PCM)
4.5. Magnetoresistive memory (MRM)
4.6. Ferroelectric Memory (FEM)
4.7. Miscellaneous

5. SUMMARY AND CONCLUSION

FIG: Evolution of the mainstream solutions for the respective memories classes. The introduction of Flash memory partially bridged a technology gap around the year 2009. Today, two types of so-called storage-class memories – a memory-type SCM (SCM 1) and a storage-type SCM (SCM 2) – were proposed to overcome the memory gap. NAND flash already fulfills the role of a mainstream SCM 2. For SCM 1, 3D XPoint could be a promising candidate, but is not a dominant mainstream memory. In future, we will likely see different types of SCMs and NV-RAM with different specifications as required by the respective application – because in the end, the overall system cost decides about the choice of the memory.