Recent Compact Modeling Papers

[1] Hao Su, Yunfeng Xie, Yuhuan Lin, Haihan Wu, Wenxin Li, Zhizhao Ma, Yiyuan Cai, Xu Si, Shenghua Zhou Guangchong Hu, Yu He Feichi Zhou, Xiaoguang Liu, Longyang Lin, Yida Li, Hongyu Yu, and Kai Chen; "Characterizations and Framework Modeling of Bulk MOSFET Threshold Voltage Based on a Physical Charge-Based Model Down to 4 K." In 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), pp. 733-736. IEEE, 2024. doi: 10.1109/ESSERC62670.2024.10719583

[2] Tung, Chien-Ting, Sayeef Salahuddin, and Chenming Hu; "A SPICE-Compatible Neural Network Compact Model for Efficient IC Simulations." In 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 01-04. IEEE, 2024.

[3] Jana, Koustav, Shuhan Liu, Kasidit Toprasertpong, Qi Jiang, Sumaiya Wahid, Jimin Kang, Jian Chen, Eric Pop, and H-S. Philip Wong; "Modeling and Understanding Threshold Voltage and Subthreshold Swing in Ultrathin Channel Oxide Semiconductor Transistors." In 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 01-04. IEEE, 2024.

[4] Manganaro, Gabriele. "Rethinking mixed-signal IC design." In 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), pp. 552-556. IEEE, 2024

[5] Wager, John F., Jung Bae Kim, Daniel Severin, Zero Hung, Dong Kil Yim, Soo Young Choi, and Marcus Bender; "Dual-Layer Thin-Film Transistor Analysis and Design." IEEE Open Journal on Immersive Displays (2024).