In the last issue of electronics letters (August 2 2007, vol 43, issue 16), there is an interesting paper on statistical simulation of sub-100nm memories. Here you have the link to the abstract, and try to have a look at it. I think that this (I mean: incorporating statistical techniques into the whole model) is an issue for a good compact model to be accepted by the design community.
Otherwise, if there is no way to take into account the huge variations in modern technologies, the model will be quite useless for them.
Aug 22, 2007
Aug 20, 2007
Scaling effects on short-channel organic transistors
If you are interested in organic transistors, perhaps you will appreciate having a look at the paper "Scaling effect on the operation stability of short-channel organic single-crystal transistors", appeared in the Applied Physics Letters of 6 August 2007 (link).
As they say in the abstract: "Organic single-crystal transistors allowed the authors to investigate the essential features of short-channel devices. Rubrene single-crystal transistors with channel lengths of 500 and 100 nm exhibited good field-effect characteristics under extremely low operation voltages, although space charge limited current degrades the subthreshold properties of 100 nm devices. Furthermore, bias-stress measurements revealed the remarkable stability of organic single-crystal transistors regardless of device size. The bias-stress effect was explained by the trapping of gate-induced charges into localized density of states in the single-crystal channel."
As they say in the abstract: "Organic single-crystal transistors allowed the authors to investigate the essential features of short-channel devices. Rubrene single-crystal transistors with channel lengths of 500 and 100 nm exhibited good field-effect characteristics under extremely low operation voltages, although space charge limited current degrades the subthreshold properties of 100 nm devices. Furthermore, bias-stress measurements revealed the remarkable stability of organic single-crystal transistors regardless of device size. The bias-stress effect was explained by the trapping of gate-induced charges into localized density of states in the single-crystal channel."
Jul 25, 2007
ISCAS'08
The 2008 IEEE International Symposium of Circuits and Systems (ISCAS 2008) will be held in Seattle (Washington, USA), on 18-21 May 2008.
ISCAS is the largest conference in the area of Circuits and Systems. It is sponsored by the IEEE Circuits and Systems Society. Prestigeous speakers in this field are always invited.
ISCAS 2008 will focus on the theme "Green Circuits and Systems: Engineering the Environmental Revolution".
The deadline for regular paper submission is October 5 2007. As indicated in the Call for Papers, the scope of ISCAS 2008 includes all topics related to integrated circuits and systems. Papers on compact modeling for circuit design are considered to address some of the topic of the call. In fact, every year a number of interesting papers on compact modeling are presented at ISCAS.
It is important to mention that in ISCAS posters are very well considered, as important as oral presentations. Many authors choose poster as their presentation format.
On the other hand, a "rich and intersting social programme is planned". It still has to be announced. Sounds promising, anyway.
ISCAS is the largest conference in the area of Circuits and Systems. It is sponsored by the IEEE Circuits and Systems Society. Prestigeous speakers in this field are always invited.
ISCAS 2008 will focus on the theme "Green Circuits and Systems: Engineering the Environmental Revolution".
The deadline for regular paper submission is October 5 2007. As indicated in the Call for Papers, the scope of ISCAS 2008 includes all topics related to integrated circuits and systems. Papers on compact modeling for circuit design are considered to address some of the topic of the call. In fact, every year a number of interesting papers on compact modeling are presented at ISCAS.
It is important to mention that in ISCAS posters are very well considered, as important as oral presentations. Many authors choose poster as their presentation format.
On the other hand, a "rich and intersting social programme is planned". It still has to be announced. Sounds promising, anyway.
New papers about compact modeling
A number of interesting papers have been published in the August issue of Transactions on Electron Devices.
In a paper entitled "Accuracy of Surface-Potential-Based Long–Wide-Channel Thick-Base MOS Transistor Models", Bin B. Jie and Chih-Tang Sah (University of Florida, Gainesville) discuss the accuracy of several surface-potential based MOSFET models. They show that the accuracy of the approximations done in these models is not so good in the accumulation and subthreshold regimes, and they propose a new analytical model showing better accuracy in those regimes.
Ananda S. Roy, Christian C. Enz and J. -M. Sallese, researchers from the EKV team at EPFL (Lausanne, Switzerland) present an analytical noise modeling paradingm for lateral nonuniform MOSFETs. They show that in these devices the bias dependence of the noise parameters cannot be predicted by conventional Klaassen-Prins (KP)-based methods.
Modeling of irradiated devices is always a hot topic. H. T. Mebrahtu et al. present SPICE models of Fluorine-Ion irradiated CMOS devices, using the EKV MOSFET model as a basis.
In this issue we also find new modeling work on Double-Gate MOSFETs. Researchers from the University of Thessaloniki (Greece) and MINATEC (Grenoble, France) have presented a paper entitled "Semi-Analytical Modeling of Short-Channel Effects in Si and Ge Symmetrical Double-Gate MOSFETs". The doping is considered in this work. The analysis is carried out in the subthershold regime, and the mobile charge is assumed to be negligible compared to the doping charge. The model shows that Ge Double-Gate MOSFETs are more prone to short-channel effects than Si Double-Gate MOSFETs.
Finally, B. Bindu, N. DasGupta and A. DasGupta (Indian Institute of Technology, Madras) present "A Unified Model for Gate Capacitance–Voltage Characteristics and Extraction of Parameters of Si/SiGe Heterostructure pMOSFETs". This analytical model is physically-based, and shows very good agreement with experimental measurements.
In a paper entitled "Accuracy of Surface-Potential-Based Long–Wide-Channel Thick-Base MOS Transistor Models", Bin B. Jie and Chih-Tang Sah (University of Florida, Gainesville) discuss the accuracy of several surface-potential based MOSFET models. They show that the accuracy of the approximations done in these models is not so good in the accumulation and subthreshold regimes, and they propose a new analytical model showing better accuracy in those regimes.
Ananda S. Roy, Christian C. Enz and J. -M. Sallese, researchers from the EKV team at EPFL (Lausanne, Switzerland) present an analytical noise modeling paradingm for lateral nonuniform MOSFETs. They show that in these devices the bias dependence of the noise parameters cannot be predicted by conventional Klaassen-Prins (KP)-based methods.
Modeling of irradiated devices is always a hot topic. H. T. Mebrahtu et al. present SPICE models of Fluorine-Ion irradiated CMOS devices, using the EKV MOSFET model as a basis.
In this issue we also find new modeling work on Double-Gate MOSFETs. Researchers from the University of Thessaloniki (Greece) and MINATEC (Grenoble, France) have presented a paper entitled "Semi-Analytical Modeling of Short-Channel Effects in Si and Ge Symmetrical Double-Gate MOSFETs". The doping is considered in this work. The analysis is carried out in the subthershold regime, and the mobile charge is assumed to be negligible compared to the doping charge. The model shows that Ge Double-Gate MOSFETs are more prone to short-channel effects than Si Double-Gate MOSFETs.
Finally, B. Bindu, N. DasGupta and A. DasGupta (Indian Institute of Technology, Madras) present "A Unified Model for Gate Capacitance–Voltage Characteristics and Extraction of Parameters of Si/SiGe Heterostructure pMOSFETs". This analytical model is physically-based, and shows very good agreement with experimental measurements.
Jul 24, 2007
Atomistic simulation of Graphene Nanoribbon Field-Effect Transistors
A very interesting paper presenting a 3-D atomistic simulation study of Graphene Nanoribbon Field-Effect Transistors (GNR-FETs) has been published in IEEE Electron Device Letters. The performance observed is comparable to the one of carbon nanotube FETs, but the leakage problems associated to the band-to-band tunneling current are also similar. The authors of this paper are B. Fiori and G. Iannacone, from the University of Pisa, Italy.
The simulations have been based on a self-consistent solution of the 3-D Poisson's and Schrödinger equations with open boundary conditions within the nonequilibrium Green's function formalism. This simulation study can be very helpful to start the development of a compact GNR-FET model, which will be necessary if this novel device becomes successful.
The simulations have been based on a self-consistent solution of the 3-D Poisson's and Schrödinger equations with open boundary conditions within the nonequilibrium Green's function formalism. This simulation study can be very helpful to start the development of a compact GNR-FET model, which will be necessary if this novel device becomes successful.
Jul 20, 2007
MOS-AK'07 Second call for papers
MOS-AK Workshop on compact modeling, organized for fifth subsequent time as an integral part of the ESSDERC/ESSCIRC conference, aims to strengthen a network and discussion forum among experts in the field, create an open platform for information exchange related to compact/Spice modeling, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. The technical program of MOS-AK Workshop consists of one day of tutorials given by noted academic and industry experts, also a posters session is foreseen. The poster session program is open and you are welcome to submit a poster presentation (before Aug.10 deadline): http://www.mos-ak.org/munich/
--- Important dates:
--------------------
* Deadline - Aug. 10
* Final workshop program - Aug.14
* MOS-AK Workshop - Sept.14 at Technische Universität München (TUM)
* after the workshop, selected presentations will be published
in the IJNM - MOS-AK publication partner.
Further information including recommended hotels and driving directions will be posted at the web site, soon; please visit regularly: http://www.mos-ak.org
--- Related Events:
-------------------
* "Industrialization of MEMS"
* ESSDERC/ESSCIRC Tutorial, September 10, 2007 Munich, Germany
* http://www.esscirc2007.org/tutorials.html#MEMS
Jul 3, 2007
WOFE'07
The 2007 Workshop on Frontiers in Electronics (WOFE) will be held in a very beautiful place: Cozumel (Mexico) from December 15 to 19 2007.
WOFE is being held every two years. It is a very special workshop devoted to bring together researchers who work at the frontiers of electronic devices and circuits. Therefore, it facilitates the interaction between researchers from different areas such as emerging nanodevices, bioelectronics, nanotubes, teraherz and infrared electronics and photonics, TFTs and giant area electronics, nanoMEMs, or wide band gap technology, provided their targets are at the frontiers of present electronics. Papers on modelling have also been usually accepted for WOFE, if they address advanced devices, or brand new modeling techniques.
We have to remark that the programme committee encourages to submit papers presenting discussions of controversial issues, rebuttals of theories, provocative or alternative views, and visionary outlooks.
The Chair of WOFE is Professor Michael S Shur, from the Rensselaer Polytechnic Institute (RPI), Troy, NY (USA). Very prestigeous researchers will be invited for plenary talks.
The deadline for abstract submission is October 01 2007.
No doubt it should be very pleasant to spend several days in Cozumel enjoying nice weather in December. Every day the sessions end early in the afternoon, so there is plenty of time to enjoy the beach. As the WOFE schedule say, the afternoon is the time for "break and networking", what means beach, or networking on the beach. Furthermore, there is a wonderful social programme, which includes one very interesting excursion.
I recommend researchers to go to WOFE. It is a very adequate event for networking in a very beautiful and relaxing place.
WOFE is being held every two years. It is a very special workshop devoted to bring together researchers who work at the frontiers of electronic devices and circuits. Therefore, it facilitates the interaction between researchers from different areas such as emerging nanodevices, bioelectronics, nanotubes, teraherz and infrared electronics and photonics, TFTs and giant area electronics, nanoMEMs, or wide band gap technology, provided their targets are at the frontiers of present electronics. Papers on modelling have also been usually accepted for WOFE, if they address advanced devices, or brand new modeling techniques.
We have to remark that the programme committee encourages to submit papers presenting discussions of controversial issues, rebuttals of theories, provocative or alternative views, and visionary outlooks.
The Chair of WOFE is Professor Michael S Shur, from the Rensselaer Polytechnic Institute (RPI), Troy, NY (USA). Very prestigeous researchers will be invited for plenary talks.
The deadline for abstract submission is October 01 2007.
No doubt it should be very pleasant to spend several days in Cozumel enjoying nice weather in December. Every day the sessions end early in the afternoon, so there is plenty of time to enjoy the beach. As the WOFE schedule say, the afternoon is the time for "break and networking", what means beach, or networking on the beach. Furthermore, there is a wonderful social programme, which includes one very interesting excursion.
I recommend researchers to go to WOFE. It is a very adequate event for networking in a very beautiful and relaxing place.
Jun 30, 2007
Experiment on Scientific Communications
Well, today we can celebrate our first six months of existence in this blog. I'd like to take advantage of this fact to propose to all the gentle readers (as the dear old Dr. Isaac Asimov said) to leave a comment on what do you think about the utility of a blog as a method for scientific communication. I mean: there are the traditional ways (Conferences, Workshops, and so on), but the internet offers us many new possibilities, blogging being only one among others. Do you think that blogging can be useful? What do you think about other possibilites? Do you think that you could organize (for instance) a Conference using SecondLife? Do you think that webcasts (either from IEEE or other organizations) are useful or are they somewhat marginal?
Thanks (in advance) for your (kind) comments!
Thanks (in advance) for your (kind) comments!
Jun 29, 2007
Threshold voltage and subthreshold swing models in undoped Double-Gate MOSFETs
Accurate models for the threshold voltage and subthreshold swing in nanoscale MOSFETs should be based forom a 2D electrostatic analysis.
In doped devices, the carrier concentration is usually neglected in such electrostatic analysis, that is carried out in the subthreshold region, where the doping concentration is much higher than the carrier concentration.
However, in the case of undoped DG MOSFETs, the carrier concentration may be not negligible for that electrostatic analysis, in particular in the threshold regime.
A recent paper was presenting the first complete threshold voltage and subthreshold swing models for nanoscale DG MOSFETs, by considering the carrier concentration in Poisson's equation:
El Hamid, H. A.; Roig Guitart, J.; Iniguez, B., "Two-Dimensional Analytical Threshold Voltage and Subthreshold Swing Models of Undoped Symmetric Double-Gate MOSFETs," IEEE Trans. on Electron Devices, vol. 54, no. 6, pp. 1402-1408, June 2007
This model includes the threshold voltage roll-off, the DIBL and the subthreshold swing degradation.
This paper improves the model developed by Qian Chen et al., also published in IEEE Transactions on Electron Devices, in which the carrier concentration was considered, but the model development was done only at low drain voltage; the DIBL and the subthreshold swing degradation with the drain voltage were ignored:
Q. Chen, E. M. Harrell, J. D. Meindl, "A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs," IEEE Transactions on Electron Devices, vol. 50, no. 7, pp. 1631-1637, July 2003
In doped devices, the carrier concentration is usually neglected in such electrostatic analysis, that is carried out in the subthreshold region, where the doping concentration is much higher than the carrier concentration.
However, in the case of undoped DG MOSFETs, the carrier concentration may be not negligible for that electrostatic analysis, in particular in the threshold regime.
A recent paper was presenting the first complete threshold voltage and subthreshold swing models for nanoscale DG MOSFETs, by considering the carrier concentration in Poisson's equation:
El Hamid, H. A.; Roig Guitart, J.; Iniguez, B., "Two-Dimensional Analytical Threshold Voltage and Subthreshold Swing Models of Undoped Symmetric Double-Gate MOSFETs," IEEE Trans. on Electron Devices, vol. 54, no. 6, pp. 1402-1408, June 2007
This model includes the threshold voltage roll-off, the DIBL and the subthreshold swing degradation.
This paper improves the model developed by Qian Chen et al., also published in IEEE Transactions on Electron Devices, in which the carrier concentration was considered, but the model development was done only at low drain voltage; the DIBL and the subthreshold swing degradation with the drain voltage were ignored:
Q. Chen, E. M. Harrell, J. D. Meindl, "A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs," IEEE Transactions on Electron Devices, vol. 50, no. 7, pp. 1631-1637, July 2003
Jun 27, 2007
IEEE papers
Well, another update on some IEEE publications. I've got three papers quite related to compact modeling:
"An analytical Compact Model for Nanowire FET", by B.C. Paul et alter, in IEEE Trans. on Electron Devices.
"Explicit Analytical Charge and Capacitance Models of Undoped Double-Gate MOSFETs", by O. Moldovan et alter, also in IEEE Trans. on Electron Devices.
"Limits of Performance Gain of Aligned CNT Over Randomized Network: Theoretical Predictions and Experimental Validation", by N. Pimparkar et alter, in IEEE Electron Device Letters.
"An analytical Compact Model for Nanowire FET", by B.C. Paul et alter, in IEEE Trans. on Electron Devices.
"Explicit Analytical Charge and Capacitance Models of Undoped Double-Gate MOSFETs", by O. Moldovan et alter, also in IEEE Trans. on Electron Devices.
"Limits of Performance Gain of Aligned CNT Over Randomized Network: Theoretical Predictions and Experimental Validation", by N. Pimparkar et alter, in IEEE Electron Device Letters.
Jun 25, 2007
International Semiconductor Device Research Symposium'07
The biennial International Semiconductor Device Research Symposium will take place on December 12-14, on Maryland, USA.
This Symposium focuses on exploratory research in electronic and photonic materials and devices. Areas such as novel device concepts, processing technologies, advanced modeling, nanotechnology, nanoelectronics, wide band-gap semiconductors, MEMS materials and devices, oxides and dielectrics, magnetic materials and devices, organic and polymer opto-electronic materials and devices, ultra high frequency devices & RF effects, and high power-high temperature devices are included. The Symposium brings together diverse participants in multidisciplinary areas, and provides a forum for extended personal scientific interaction for engineers, scientists, and students working in the field of advanced electronic materials and device technologies.
Moreover, it has a topic dedicated to Compact (and Distributed) Modeling, so I guess it can be interesting to go there and have a look. Another interesting advantage of presenting a paper at ISDRS 2007 is that it is held just after IEDM, and very close to the IEDM venue (Washington DC), so researchers who present papers at ISDRS can attend before IEDM and then go to ISDRS. This is why ISDRS is held every two years, when ISDRS is held at Washington DC.
In fact, ISDRS an alternative to IEDM, especially for university teams, in the sense that IEDM is more industrial oriented, while ISDRS focuses more on device properties research and device modeling.
This Symposium focuses on exploratory research in electronic and photonic materials and devices. Areas such as novel device concepts, processing technologies, advanced modeling, nanotechnology, nanoelectronics, wide band-gap semiconductors, MEMS materials and devices, oxides and dielectrics, magnetic materials and devices, organic and polymer opto-electronic materials and devices, ultra high frequency devices & RF effects, and high power-high temperature devices are included. The Symposium brings together diverse participants in multidisciplinary areas, and provides a forum for extended personal scientific interaction for engineers, scientists, and students working in the field of advanced electronic materials and device technologies.
Moreover, it has a topic dedicated to Compact (and Distributed) Modeling, so I guess it can be interesting to go there and have a look. Another interesting advantage of presenting a paper at ISDRS 2007 is that it is held just after IEDM, and very close to the IEDM venue (Washington DC), so researchers who present papers at ISDRS can attend before IEDM and then go to ISDRS. This is why ISDRS is held every two years, when ISDRS is held at Washington DC.
In fact, ISDRS an alternative to IEDM, especially for university teams, in the sense that IEDM is more industrial oriented, while ISDRS focuses more on device properties research and device modeling.
Jun 20, 2007
CICC'07
The 2007 IEEE Custom Integrated Circuits Conference (CICC) will take place on September 16-19, 2007, at the DoubleTree Hotel in San Jose, California, in the heart of Silicon Valley.
CICC is one of the top conferences on circuit design. The main topics of the conference are Analog Circuit Design, Digital Circuit amd SoC/ASIP/SiP Design and Methodology, Custom Applications and Power Management, Sensors, MEMs, Manufacturing and Test, Wireless Designs, Wireless Communications, Programmable Devices, Embedded Memory, Signal and Data Processing and Simulation and Modeling, including Compact Device Modeling.
CICC 2007 will intend to show the latest developments in Compact Modeling, for the training of designers and to facilitate a close interaction between designers and compact model developers.
I will present an invited paper at CICC 2007, which will present charge based modeling techniques for multiple-gate MOSFETs.
Not all is business in San Jose. It is a wonderful city with many other attractions: golf courses, wineries, and for hikers and nature lovers, the Alum Rock Park. Besides, San Jose, which is called the "Safest Big City in America", has an intense nightlife, with many dance clubs and sports bars.
CICC is one of the top conferences on circuit design. The main topics of the conference are Analog Circuit Design, Digital Circuit amd SoC/ASIP/SiP Design and Methodology, Custom Applications and Power Management, Sensors, MEMs, Manufacturing and Test, Wireless Designs, Wireless Communications, Programmable Devices, Embedded Memory, Signal and Data Processing and Simulation and Modeling, including Compact Device Modeling.
CICC 2007 will intend to show the latest developments in Compact Modeling, for the training of designers and to facilitate a close interaction between designers and compact model developers.
I will present an invited paper at CICC 2007, which will present charge based modeling techniques for multiple-gate MOSFETs.
Not all is business in San Jose. It is a wonderful city with many other attractions: golf courses, wineries, and for hikers and nature lovers, the Alum Rock Park. Besides, San Jose, which is called the "Safest Big City in America", has an intense nightlife, with many dance clubs and sports bars.
ICMTS'08
The 21st IEEE International Conference on Microelectronic Test Structures (ICMTS) will be held in Edinburgh, Scotland, March 24-27 2008.
ICMTS has become a well established conference addressing topics such as test structures, material, process and device characterization techniques, compact device model parameter extraction and reliability analysis.
In 2008 ICMTS will be organized by the University of Edinburgh. Extended abstracts should be submitted by September 14 2007.
From my experience, ICMTS is a very interesting forum to present new methods to extract parameters of compact device models. In the recent times there has been emphasis on parameter extraction from RF measurements. Also ICMTS allows a very useful interaction between researchers coming from characterization teams and compact modeling teams. On the other hand, I want to highlight that ICMTS uses to have a very nice social programme.
ICMTS has become a well established conference addressing topics such as test structures, material, process and device characterization techniques, compact device model parameter extraction and reliability analysis.
In 2008 ICMTS will be organized by the University of Edinburgh. Extended abstracts should be submitted by September 14 2007.
From my experience, ICMTS is a very interesting forum to present new methods to extract parameters of compact device models. In the recent times there has been emphasis on parameter extraction from RF measurements. Also ICMTS allows a very useful interaction between researchers coming from characterization teams and compact modeling teams. On the other hand, I want to highlight that ICMTS uses to have a very nice social programme.
ICOE'07
The third edition of the International Conference on Organic Electronics (ICOE) was held at the High-Tech Campus in Eindhoven, The Netherlands, June 04-07 2007
ICOE arised as an initiative of the European Framework 6 IST Programme through the Integrated Project 'PolyApply'. This conference addresses all issues related to organic electronics, such as materials, manufacture, Organic Thin Film Transistors (OTFTs), OLEDs, PV devices, organic circuit design, and organic device modeling.
Many interesting papers were presented, mostly from Europe. It should be mentioned that there are many European teams currently working on organic electronics.
There were not many paper dealing with device modeling, although there were interesting. We can highlit the papers entitled "Modeling Traps in ultrathin pentacene transistors," by A. D. Geiser, A. von Mühlenen, N. Errien and L. Zuppiroli (EPFL, Lausanne, Switzerland), "Paper Charge Injection Model for Organic Light-emitting Diodes," by L. Li, G. Meller, and H. Kosina (Institute for Microelectronics, TU-Wien, Wien, Austria).
One paper presented a compact model for OTFTs, assuming a transport mechanism based on a quasi-drift-quasi-diffusion theory.. It was entitled "Analytical modelling of TFTs and diodes on small molecule organic semiconductor devices," by S. Prior, D.Donaghy, W.Eccleston (Organic Electronics Group, University of Liverpool, Liverpool, UK), and B. Stablober and A. Haase (Joanneum Research, Austria).
The invited speakers were also top scientists in Organic Electronics. Sergei Baranovski (Philipps-University Marburg, Germany) presented a theory of the charge transport in disordered organic materials. Dan Frisbie (University of Minnesota, USA) made a talk about the Polymer Electrolyte-Gated Organic Field-Effect Transistors. Hagen Klauk (Max Planck Institute for Solid State Research, Stuttgart, Germany) made a very interesting presentation about low voltage organic transistors and circuits. Takao Someya (University of Tokyo, Japan) addressed the printed organic transistors for large-area skin-like sensors and actuators.
Despite PolyApply will end at the end of 2007, it is expected that ICOE will still be held new year, supported by other sponsors.
ICOE arised as an initiative of the European Framework 6 IST Programme through the Integrated Project 'PolyApply'. This conference addresses all issues related to organic electronics, such as materials, manufacture, Organic Thin Film Transistors (OTFTs), OLEDs, PV devices, organic circuit design, and organic device modeling.
Many interesting papers were presented, mostly from Europe. It should be mentioned that there are many European teams currently working on organic electronics.
There were not many paper dealing with device modeling, although there were interesting. We can highlit the papers entitled "Modeling Traps in ultrathin pentacene transistors," by A. D. Geiser, A. von Mühlenen, N. Errien and L. Zuppiroli (EPFL, Lausanne, Switzerland), "Paper Charge Injection Model for Organic Light-emitting Diodes," by L. Li, G. Meller, and H. Kosina (Institute for Microelectronics, TU-Wien, Wien, Austria).
One paper presented a compact model for OTFTs, assuming a transport mechanism based on a quasi-drift-quasi-diffusion theory.. It was entitled "Analytical modelling of TFTs and diodes on small molecule organic semiconductor devices," by S. Prior, D.Donaghy, W.Eccleston (Organic Electronics Group, University of Liverpool, Liverpool, UK), and B. Stablober and A. Haase (Joanneum Research, Austria).
The invited speakers were also top scientists in Organic Electronics. Sergei Baranovski (Philipps-University Marburg, Germany) presented a theory of the charge transport in disordered organic materials. Dan Frisbie (University of Minnesota, USA) made a talk about the Polymer Electrolyte-Gated Organic Field-Effect Transistors. Hagen Klauk (Max Planck Institute for Solid State Research, Stuttgart, Germany) made a very interesting presentation about low voltage organic transistors and circuits. Takao Someya (University of Tokyo, Japan) addressed the printed organic transistors for large-area skin-like sensors and actuators.
Despite PolyApply will end at the end of 2007, it is expected that ICOE will still be held new year, supported by other sponsors.
MOS-AK at ESSDERC/ESSCIRC'07
MOS-AK Workshop on compact modeling will be held on Friday, 14 September 2007 in Munich, and it is organized for fifth subsequent time as an integral part of the ESSDERC/ESSCIRC conference, aims to strengthen a network and discussion forum among experts in the field, create an open platform for information exchange related to compact/Spice modeling, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors.
The topics cover all important aspects of compact model development, implementation, deployment and standardization within the main theme - compact models for mainstream CMOS/SOI circuit simulation. The specific workshop goal will be to classify the most important directions for the future development of the compact models and to clearly identify areas that need further research.
This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe) who are interested in device modeling; ICs designers (RF/IF/Analog/Mixed-Signal/SoC) and those starting in that area as well as device characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind IC simulation in modern device models. The technical program of MOS-AK Workshop consists of one day of tutorials given by noted academic and industry experts, also a posters session is foreseen.
More information on http://www.mos-ak.org/munich/
The topics cover all important aspects of compact model development, implementation, deployment and standardization within the main theme - compact models for mainstream CMOS/SOI circuit simulation. The specific workshop goal will be to classify the most important directions for the future development of the compact models and to clearly identify areas that need further research.
This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe) who are interested in device modeling; ICs designers (RF/IF/Analog/Mixed-Signal/SoC) and those starting in that area as well as device characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind IC simulation in modern device models. The technical program of MOS-AK Workshop consists of one day of tutorials given by noted academic and industry experts, also a posters session is foreseen.
More information on http://www.mos-ak.org/munich/
Jun 19, 2007
CMOS at 60GHz
It is not Compact Modelling, but it is interesting enough. It seems that toshiba has developed a CMOS (yes, CMOS) technology able to run at 60GHz... See yourself the press release here.
May 22, 2007
Spintronics
Some news in the papers. It seems that someone has succeeded in controlling spin properties inside a semiconductor... You can get more info following the link.
May 12, 2007
New simulator with HiSIM
Simucad has announced (see the press note) the release of a new version of their simulator supporting HiSIM. Well, that's another point for HiSIM, and another drawback for PSP.
May 9, 2007
WCM'07
The 2007 Workshop on Compact Modeling (WCM) will take place in Santa Clara (Silicon Valley, California) from May 20 to 24 2007.
WCM'07 is part of the NSTI Nanotech 2007 Conference, and is held in association with the Tenth International Conference on Modeling and Simulation of Microsystems (MSM 2007).
WCM is the main symposium devoted to the field of compact modeling of semiconductor devices. The WCM Workshop was created in 2002, thanks, especially, to Professor Xing Zhou, from Nanyang Technological University (Singapore), who has always been the WCM Chair.
The technical program of WCM is especially interesting this year. Some of the invited speakers are really big authorities in the field of semiconductor device modelling: Jerry Fossum, Chenming Hu, Narain Arora, Mark Lundstrom, Jamal Deen, Tor Fjeldly, Yuan Taur, Colin McAndrew, Mitiko Miura-Mattausch, Dirk Klaassen,...
There will be sessions devoted to different types of devices. Multiple Gate MOSFET modeling is certainly a very hot topic: there will be two sessions adressing these devices, and another session will also include papers on single and double gate SOI MOSFETs.
Among the papers to be presented regarding the modeling of Multiple Gate MOSFET modeling, we can highlight the presentation of a PSP-based scalable model for FinFETs, a work made by the PSP team.
On the other hand, WCM will include one interesting session focusing on statistical/process-based models.
I truly recommend all compact modeling developers to attend WCM'07. It is the workshop where the new ideas on compact modeling are first presented.
WCM'07 is part of the NSTI Nanotech 2007 Conference, and is held in association with the Tenth International Conference on Modeling and Simulation of Microsystems (MSM 2007).
WCM is the main symposium devoted to the field of compact modeling of semiconductor devices. The WCM Workshop was created in 2002, thanks, especially, to Professor Xing Zhou, from Nanyang Technological University (Singapore), who has always been the WCM Chair.
The technical program of WCM is especially interesting this year. Some of the invited speakers are really big authorities in the field of semiconductor device modelling: Jerry Fossum, Chenming Hu, Narain Arora, Mark Lundstrom, Jamal Deen, Tor Fjeldly, Yuan Taur, Colin McAndrew, Mitiko Miura-Mattausch, Dirk Klaassen,...
There will be sessions devoted to different types of devices. Multiple Gate MOSFET modeling is certainly a very hot topic: there will be two sessions adressing these devices, and another session will also include papers on single and double gate SOI MOSFETs.
Among the papers to be presented regarding the modeling of Multiple Gate MOSFET modeling, we can highlight the presentation of a PSP-based scalable model for FinFETs, a work made by the PSP team.
On the other hand, WCM will include one interesting session focusing on statistical/process-based models.
I truly recommend all compact modeling developers to attend WCM'07. It is the workshop where the new ideas on compact modeling are first presented.
May 7, 2007
Spintronics
Have you ever wondered what is that thing people call 'spintronics'? If so, here you have the link to a very good review on that, beginning at the basis. It has been published at this month's issue of IEEE Transactions on Electron Devices (as an Invited Paper), an it has been written by Michael E. Flatté, from the University of Iowa. I strongly recommend having a look at it. This way, at least, you will be able to answer some more questions when playing trivial pursuit....
May 2, 2007
Another Blog
Here you have a list of other blogs. It is interesting to have a look at them, because there is interesting info there, though not all of them are updated often.
http://semiweb.blogspot.com/
http://semiconductorglossary.com/
http://ece-www.colorado.edu/~bart/book/book/contents.htm
http://semiweb.blogspot.com/
http://semiconductorglossary.com/
http://ece-www.colorado.edu/~bart/book/book/contents.htm
Apr 27, 2007
International Microwave Symposium'07
The 2007 International Microwave Symposium is a little over a month away. It will be held in Honolulu, Hawaii, between 3-8 June. And, as predicted, they are hosting some sessions on modeling. In fact, as reflected in the technical program, they will host two short courses on device modeling and characterization, plus another in noise. In addition, there will be four different sessions dedicated to models. A nice opportunity to visit Hawaii...
Apr 25, 2007
Biosensors and CNTs
A brief comment on a brief news appeared in the SPIE newsroom: Joe Shapter and Jamie Quinton, from the Finders University, Australia, explain how to ease the integration of biosensors into silicon, thanks to the use of carbon nanotubes. It's ok, but we still do not have any compact model for a carbon nanotube, so simulation of this kind of sensors is not feasible in a conventional simulator. It's a pity.
Apr 23, 2007
MOS-AK Meeting in Graz
The Spring MOS-AK meeting was held on April 30 in Premstraetten (very close to Graz), Austria
The scope of Spring Meeting was noise compact modeling, but also included contributions on noise measurement and characterization. Different devices were considered: conventional bulk MOSFETs, lateral MOSFETs, multiple-gate MOSFETs.
It was a very interesting meeting, with the participation of top researchers in the field of noise and compact modeling, such as Christoph Jungemann or Mitiko Miura-Mattausch (who explained the implementation of noise modelling in the HiSIM bulk MOSFET model).
Furthermore, it was a very nice oportunity to visit the beautiful city of Graz, and to taste the delicious pumkin-based Styrian specialties as well as the great local wines.
The scope of Spring Meeting was noise compact modeling, but also included contributions on noise measurement and characterization. Different devices were considered: conventional bulk MOSFETs, lateral MOSFETs, multiple-gate MOSFETs.
It was a very interesting meeting, with the participation of top researchers in the field of noise and compact modeling, such as Christoph Jungemann or Mitiko Miura-Mattausch (who explained the implementation of noise modelling in the HiSIM bulk MOSFET model).
Furthermore, it was a very nice oportunity to visit the beautiful city of Graz, and to taste the delicious pumkin-based Styrian specialties as well as the great local wines.
New issue of the IEEE Trans. on Electron Devices
Some new papers from quite important people in this month's issue of the IEEE Trans. on Electron Devices:
First, A Compact Model for Valence-Band Electron Tunneling Current in Partially Depleted SOI MOSFETs From Gildenblat, McAndrew,... etc...
Second, Depletion-All-Around Operation of the SOI Four-Gate Transistor from Cristoloveanu et alter.
First, A Compact Model for Valence-Band Electron Tunneling Current in Partially Depleted SOI MOSFETs From Gildenblat, McAndrew,... etc...
Second, Depletion-All-Around Operation of the SOI Four-Gate Transistor from Cristoloveanu et alter.
Apr 20, 2007
More statistical modelling
Have a look at this paper from Samsudin et al. in the Solid-State Journal. If you are interested in statistical variations (and perhaps you should...), it is a nice reading.
Apr 18, 2007
BSIM5
I've been having a look at the Solid-State Journal, and I've found a very interesting paper from Jin He et al. They present a charge based model: BSIM5. I strongly recommend having a look at the paper, since it is from a quite good guy and the topic is, at least, important.
Apr 17, 2007
MOS-AK meeting
By the way, this Friday the Spring Meeting of the MOS-AK will be held in Graz, Austria, with very interesting talks, including one on Verilog-AMS and GNU software. If there is anyone going there, please send some comments....
So long....
It has been a long time since the last entry in the blog... I regret (I mean: I'm happy...) that we've had too much work. Well, here you have a very interesting link. It is not very related to Compact Modelling, but it is VERY related to scientific communication. It is an article in the Sydney Herald Tribune reporting an study about powerpoint(tm) presentations... You should read it (it quite short)...
Mar 28, 2007
HiSIM model included in another simlator
Magma FineSim SPICE Supports STARC HiSIM Model with Proven 20x Faster Circuit Simulation and Nearly Exact Correlation to Silicon. Or so they say in their web. See the full press release for more details. However, I love one of the sentences: "STARC's mission is to contribute to the growth of the Japanese semiconductor industry by developing leading-edge system-on-a-chip (SoC) design technologies.". Well, I would think that their primary mission is creating value for they investors, but one never knows. Now seriously, it is good to see that people is beginning to provide support (or implementations) of HiSIM. I only hope that foundries will follow the path, instead of being stuck with good (well, perhaps not so much), old (yes it is) BSIM3.1. I know this is a version of many years ago, but I can promise you that I've been playing with a 120nm technology using it.
By the way, by the moment it seems that more people is implementing HiSIM than PSP... curious, isn't it?
By the way, by the moment it seems that more people is implementing HiSIM than PSP... curious, isn't it?
Mar 27, 2007
Call for Grant applications at SRC
SRC-GRC is calling for grant applications in Cross-disciplinary Semiconductor Research. The role of this program is to stimulate non-traditional thinking about the issues facing the semiconductor industry. It is intended to seed new research and programs for the SRC-GRC and SRC-FCRP. Consistent with the incubator role of the initiative, these will be 1 year non-overhead bearing grants at a funding level of $40K.
The scope of this solicitation is Nanoscale CMOS-Based Architectures. The challenge: Sustaining CMOS value progression through functional scaling and system design. The deadline: may, 1st. In principle, this is not for compact models, but I think that a good proposal including compact modeling could be redacted. Why? Because new devices are required to address the challenges of the next years and there is no way to do it without good compact models. So, at least a part of a sensible proposal should include some compact modeling (if nothing more, some way to go from compact device models to compact functional models... otherwise no real achivements will be obtained but only some old techniques re-edited)
By the way, IBM India is looking for Compact Model Engineers. Have a look at their web.
The scope of this solicitation is Nanoscale CMOS-Based Architectures. The challenge: Sustaining CMOS value progression through functional scaling and system design. The deadline: may, 1st. In principle, this is not for compact models, but I think that a good proposal including compact modeling could be redacted. Why? Because new devices are required to address the challenges of the next years and there is no way to do it without good compact models. So, at least a part of a sensible proposal should include some compact modeling (if nothing more, some way to go from compact device models to compact functional models... otherwise no real achivements will be obtained but only some old techniques re-edited)
By the way, IBM India is looking for Compact Model Engineers. Have a look at their web.
Mar 23, 2007
Another blog
I've found another blog about semiconductors. It is basically about technology news, but it is quite interesting to look at. You can reach it here (by the way, the name is Semiconductor Highlights). It is not frequentely updated, but it has a long history. In any case, if any of you, dear hipothetical readers, feels like suggesting another blog, don't hesitate to post it here...
Mar 20, 2007
DCIS'07
The last call for papers has been issued for the DCIS'07. This conference has evolved from its origins, more than two decades ago, into an important international meeting for researches in the highly active fields of micro and nano electronics circuits and integrated systems. It provides an excellent forum to present and investigate the emerging challenges in modelling, design, implementation and test of circuits and systems. Experts from both industry and academia have the chance to discuss the demands and solutions for current applications. Strong scientific, technical and personal relationships have been developed in the frame of this event. Moreover, there will be at least one session dedicated to modelling. So, it is a very good opportunity to visit Sevilla!
Mar 16, 2007
MIGAS'07 Summer School will focus on Multi-Physics and Multi-Scale Simulation
The International Summer School on Advanced Microelectronics (MIGAS) has become probably the top summer school held in Europe in the field of semiconductor devices. MIGAS is organized by the Institut National Polytechnique de Grenoble (INPG) and the Center for Innovation in Micro & NanoTechnology (MINATEC). The venue is always a beautiful town or resort in the Alps close to Grenoble. This year MIGAS'07 (June 24-29) will take place in Autrans, a well-known alpine resort, offering many kind of outdoor opportunities: hiking, mountain climbing, mountain-biking,...
Every year MIGAS addresses a different topic. This year, MIGAS'07 (10th Session) will be devoted to Multi-Physics and Multi-Scale Simulation for NanoElectronics.
It is well known that traditional modeling tools are not suitable to simulate the behaviour of nanoelectronic devices. The invited lecturers will explain new methods to model nanoscale devices:
-Non-equilibrium Green's functions methods (M.P. Anantram, Waterloo, Canada)
-Ab-initio methods (X. Blase, Lyon, France)
-Wigner functions methods (P. Dollfus, Paris, France)
-Monte Carlo methods (D. Esseni, Udine, Italy)
-Kp methods (F. Michelini, Marseille, France)
-Tight-binding methods (Y.M. Niquet, Grenoble, France)
-Deterministic solution of the Boltzmann Transport Equation (C. Jungemann, Munich, Germany)
In addition, there will be lectures on nanoscale device process simulation (M. Jaraiz, Valladolid, Spain), quantum transport theory (D.K. Ferry, Arizona, USA) , noise in nanoelectronics (G. Iannaccone, Pisa, Italy), and also characterisation techniques (S. Cristoloveanu, Grenoble, France) . Finally, I will conduct a lecture on the compact modeling of nanoscale MOSFETs.
No doubt MIGAS'07 will be a very interesting opportunity for students and researchers to become familiar with the new modeling methods proposed for the novel nanoelectronic devices.
Every year MIGAS addresses a different topic. This year, MIGAS'07 (10th Session) will be devoted to Multi-Physics and Multi-Scale Simulation for NanoElectronics.
It is well known that traditional modeling tools are not suitable to simulate the behaviour of nanoelectronic devices. The invited lecturers will explain new methods to model nanoscale devices:
-Non-equilibrium Green's functions methods (M.P. Anantram, Waterloo, Canada)
-Ab-initio methods (X. Blase, Lyon, France)
-Wigner functions methods (P. Dollfus, Paris, France)
-Monte Carlo methods (D. Esseni, Udine, Italy)
-Kp methods (F. Michelini, Marseille, France)
-Tight-binding methods (Y.M. Niquet, Grenoble, France)
-Deterministic solution of the Boltzmann Transport Equation (C. Jungemann, Munich, Germany)
In addition, there will be lectures on nanoscale device process simulation (M. Jaraiz, Valladolid, Spain), quantum transport theory (D.K. Ferry, Arizona, USA) , noise in nanoelectronics (G. Iannaccone, Pisa, Italy), and also characterisation techniques (S. Cristoloveanu, Grenoble, France) . Finally, I will conduct a lecture on the compact modeling of nanoscale MOSFETs.
No doubt MIGAS'07 will be a very interesting opportunity for students and researchers to become familiar with the new modeling methods proposed for the novel nanoelectronic devices.
Mar 14, 2007
Technology news
I've found a curious article at the EE Times Europe (a nice journal, by the way). The title is "Graphene transistor to rival silicon, say researchers". Some researchers at the University of Manchester and at the Max Planck Institute claim that they have developed a transistor that is 1 atom thin. Read the full story at the link above, but I've loved the last sentence: "Professor Geim indicated graphene based circuits would not come of age before 2025 and till then silicon based devices would predominate.". This is long-term research... Now, seriously, what they are developing, if it can be used industrialy, will be a revolution, bringing single electron devices to life. However, we shall have to wait 18 years more.
Mar 13, 2007
Links
I've found some interesting links about Compact Modeling. The first one is the homepage of Dr. Zhou Xing, at the Nanyang Technological University (Singapore). A quite interesting page, with links to many of his papers and works.
The second link is more educational, and contains the material of a course in the "Grupo de Electrónica del Estado Sólido de la Universidad Simón Bolívar" (Caracas, VENEZUELA). The only drawback of this excellent page is that it is in a mixture of Spanish and English. However, the completeness of the page fully justifies a visit.
The second link is more educational, and contains the material of a course in the "Grupo de Electrónica del Estado Sólido de la Universidad Simón Bolívar" (Caracas, VENEZUELA). The only drawback of this excellent page is that it is in a mixture of Spanish and English. However, the completeness of the page fully justifies a visit.
Mar 9, 2007
Carbon Nanotubes
I've been informed that the Journal of Semiconductor Science and Technology freely distributes (up to april, 18th) its special issue on charge and transport on Carbon Nanotubes. It is a very interesting topic, and the papers are both reviews and original research. I think it is an opportunity not to be missed.
Mar 8, 2007
Compact charge and capacitance models of nanowire MOSFETs
The compact modeling of nanowire MOSFETs (also called surrounding gate MOSFETs or Gate All Around MOSFETs) is a hot topic. The first compact drain current models were published in 2004:
Researchers are now addressing the compact modeling of charges and capacitances. In January 2007, in IEEE Transactions on Electron Devices, the first compact model for charges and capacitances of surrounding gate MOSFETs was published: Analytical Charge and Capacitance Models of Undoped Cylindrical Surrounding-Gate MOSFETs, by Moldovan O., Jiménez D., Roig J. and Iñiguez B.
In March 2007, a new charge model for surrounding gate MOSFETs has been published in IEEE Transactions on Electron Devices: Analytic Charge Model for Surrounding-Gate MOSFETs, by Yu B., Lu W.-Y., Lu H. and Taur, Y.
Both models are based on the electrostatic potential soultion obtained by D. Jimenez et al. (Continuous analytic I-V model for surrounding-gate MOSFETs, IEEE Electron Device Letters, August 2005)
from the 1-D Poisson's equation in the radial direction (neglecting the effect of the lateral field). B. yu et al use the initial formulation proposed by Jimenez; charge and capacitances are written in terms of a variable which depends on the surface potential, and is calculated iteratively at the source and drain ends of the channel. Moldovan uses a charge-based formulation: from a charge control model, developed by B. Iñiguez et al. (Explicit continuous model for long-channel undoped surrounding gate MOSFETs, IEEE Transactions on Electron Devices, August 2005)
from the analysis of D. Jimenez et al, analytical expressions of charges and capacitances are obtained in terms of the mobile charge sheet densities at the source and drain ends of the channel; explicit expressions of the mobile charge sheet denisities are finally used.
Researchers are now addressing the compact modeling of charges and capacitances. In January 2007, in IEEE Transactions on Electron Devices, the first compact model for charges and capacitances of surrounding gate MOSFETs was published: Analytical Charge and Capacitance Models of Undoped Cylindrical Surrounding-Gate MOSFETs, by Moldovan O., Jiménez D., Roig J. and Iñiguez B.
In March 2007, a new charge model for surrounding gate MOSFETs has been published in IEEE Transactions on Electron Devices: Analytic Charge Model for Surrounding-Gate MOSFETs, by Yu B., Lu W.-Y., Lu H. and Taur, Y.
Both models are based on the electrostatic potential soultion obtained by D. Jimenez et al. (Continuous analytic I-V model for surrounding-gate MOSFETs, IEEE Electron Device Letters, August 2005)
from the 1-D Poisson's equation in the radial direction (neglecting the effect of the lateral field). B. yu et al use the initial formulation proposed by Jimenez; charge and capacitances are written in terms of a variable which depends on the surface potential, and is calculated iteratively at the source and drain ends of the channel. Moldovan uses a charge-based formulation: from a charge control model, developed by B. Iñiguez et al. (Explicit continuous model for long-channel undoped surrounding gate MOSFETs, IEEE Transactions on Electron Devices, August 2005)
from the analysis of D. Jimenez et al, analytical expressions of charges and capacitances are obtained in terms of the mobile charge sheet densities at the source and drain ends of the channel; explicit expressions of the mobile charge sheet denisities are finally used.
Mar 6, 2007
Special Compact Modeling Session in the MIXDES'07 Conference
Dr Wladek Grabinski, chair of the MOS-AK Group (MOS Modeling and Parameter Extraction Working Group), is organizing, as in the last years, a Special Compact Modeling Session in the frame of the 14th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES'07).
MIXDES'07 is held in the beautiful town of Ciechocinek (a renowned spa in Poland), 21-23 June 2007. The deadline for regular paper submission is March 12 2007. Prospective authors for the Special Compact Modeling Session should contact Dr. Wladek Grabinski.
MIXDES has become one of the most important microelectronics conferences in Central Europe. Every year an important number of very relevant contributions from all around the world (of course, the majority from Europe) are presented at MIXDES. Prestigeous researchers are invited to give talks for the plenary session and also for the special sessions.
This year, one of the invited presentations, given by myself, will be devoted to the TFT Compact Modeling. It is entitled: "Modeling of Thin Film Transistors for Circuit Simulation"
The Special Compact Modeling Session, held every year under the umbrella of MIXDES, has become a very interesting forum for the discussion and the exchange of information regarding compact modeling issues.
I recommend compact modeling researchers to participate in the MIXDES Special Compact Modeling Session. Contributions are always of very high quality. And I wish to mention that MIXDES has always a superb social programme.
MIXDES'07 is held in the beautiful town of Ciechocinek (a renowned spa in Poland), 21-23 June 2007. The deadline for regular paper submission is March 12 2007. Prospective authors for the Special Compact Modeling Session should contact Dr. Wladek Grabinski.
MIXDES has become one of the most important microelectronics conferences in Central Europe. Every year an important number of very relevant contributions from all around the world (of course, the majority from Europe) are presented at MIXDES. Prestigeous researchers are invited to give talks for the plenary session and also for the special sessions.
This year, one of the invited presentations, given by myself, will be devoted to the TFT Compact Modeling. It is entitled: "Modeling of Thin Film Transistors for Circuit Simulation"
The Special Compact Modeling Session, held every year under the umbrella of MIXDES, has become a very interesting forum for the discussion and the exchange of information regarding compact modeling issues.
I recommend compact modeling researchers to participate in the MIXDES Special Compact Modeling Session. Contributions are always of very high quality. And I wish to mention that MIXDES has always a superb social programme.
Threshold voltage models
As each month, I've been performing a review of some of the more interesting literature. Today, I'll point out three papers, all of them in the current issue of IEEE Trans. El. Devices, and all three of them dedicated to threshold voltage modeling.
The first one is Threshold-Voltage Modeling of Body-Tied FinFETs (Bulk FinFETs), by Choi, B.-K. Han, K.-R. Kim, Y. M. Park, Y. J. Lee, J.-H. Someday I shall comment something about threshold voltage extraction methods, because it is quite interesting. However, this will not be today.
The second paper is Compact Analytical Threshold-Voltage Model of Nanoscale Fully Depleted Strained-Si on Silicon–Germanium-on-Insulator (SGOI) MOSFETs by Venkataraman, V.; Nawal, S.; Kumar, M. J. I think that the title is quite self-explanatory.
Finally, the third one is Analytical Model of the Threshold Voltage and Subthreshold Swing of Undoped Cylindrical Gate-All-Around-Based MOSFETs, by some friends: Hamdy El Hamid; Iniguez, B.; Roig Guitart, J.
There is a point I'd like to make: all of them are dedicated to different devices, using different technologies. This is a demostration that Iroshi Iwai is right when he says that we've got work for still some fourty or fifty years more, and that it will be possible to evade the classic Moore's Law (perhaps it should be called Moore's Guideline).
The first one is Threshold-Voltage Modeling of Body-Tied FinFETs (Bulk FinFETs), by Choi, B.-K. Han, K.-R. Kim, Y. M. Park, Y. J. Lee, J.-H. Someday I shall comment something about threshold voltage extraction methods, because it is quite interesting. However, this will not be today.
The second paper is Compact Analytical Threshold-Voltage Model of Nanoscale Fully Depleted Strained-Si on Silicon–Germanium-on-Insulator (SGOI) MOSFETs by Venkataraman, V.; Nawal, S.; Kumar, M. J. I think that the title is quite self-explanatory.
Finally, the third one is Analytical Model of the Threshold Voltage and Subthreshold Swing of Undoped Cylindrical Gate-All-Around-Based MOSFETs, by some friends: Hamdy El Hamid; Iniguez, B.; Roig Guitart, J.
There is a point I'd like to make: all of them are dedicated to different devices, using different technologies. This is a demostration that Iroshi Iwai is right when he says that we've got work for still some fourty or fifty years more, and that it will be possible to evade the classic Moore's Law (perhaps it should be called Moore's Guideline).
Mar 5, 2007
ESSDERC'07
The 2007 European Solid-State Device Research Conference (ESSDERC) and European Solid-State Circuits Conference (ESSCIRC) will be held in Munich from 11 - 13 September 2007 (about one week before Oktoberfest).
As you may know, ESSDERC is the most prestigeous European conference on electron devices. The acceptance rate is usually less than 50%.
The deadline for paper submissions is April 7 2007.
This year compact modeling appears explicitly as one of the themes for papers to be submitted to ESSDERC:
"Compact, numerical, and physical modeling; device simulation; behavior models; quantum mechanical and non-stationary transport phenomena; ballistic transport; scattering models; process dispersions, parameter fluctuations, variability; TCAD; mixed electrical-thermal modeling and simulation."
Furthermore, on September 14 2007, one day after the end of ESSDERC and ESSCIRC, the MOS-AK Workshop on Compact Modeling will take place.
As you may know, ESSDERC is the most prestigeous European conference on electron devices. The acceptance rate is usually less than 50%.
The deadline for paper submissions is April 7 2007.
This year compact modeling appears explicitly as one of the themes for papers to be submitted to ESSDERC:
"Compact, numerical, and physical modeling; device simulation; behavior models; quantum mechanical and non-stationary transport phenomena; ballistic transport; scattering models; process dispersions, parameter fluctuations, variability; TCAD; mixed electrical-thermal modeling and simulation."
Furthermore, on September 14 2007, one day after the end of ESSDERC and ESSCIRC, the MOS-AK Workshop on Compact Modeling will take place.
Mar 2, 2007
A friend of mine (Oana Moldovan) has sent me a very interesting website: the NanoHUB. As they say: " The nanoHUB, a web-based resource for research, education, and collaboration in nanotechnology, is an initiative of the NSF-funded Network for Computational Nanotechnology (NCN). The NCN is a network of universities with a vision to pioneer the development of nanotechnology from science to manufacturing through innovative theory, exploratory simulation, and novel cyberinfrastructure. NCN students, staff, and faculty are developing the nanoHUB science gateway while making use of it in their own research and education. Collaborators and partners across the world have joined the NCN in this effort."
Great for you! My congratulations for a so nice site!
Great for you! My congratulations for a so nice site!
Feb 28, 2007
David M. Cardamone, from the Department of Physics, Simon Fraser University, and Charles A. Stafford and Sumit Mazumdar Department of Physics, from the Department of Optical Sciences, University of Arizona talk in the SPIE Newsroom about a novel kind of transistor. They claim that their device is not based on field-effect, but on quantum interference. They show some results obtained using a benzene molecule as device, and, frankly, the results are not bad at all. However, I have my doubts that this can be practical in a medium range, because many problems (mainly the interconnections, from my point of view) are left open. Moreover, I'd like to see a digital gate made using these devices. Or, better, an analog amplifier. That could be a real test.
S-Parameters
I've been sent a white paper from RF-globalnet on S-parameter extraction. For those of you who do not know what a S-parameter is, I shall recommend to read it. For the rest, it can be interesting reading another point of view. The paper is from Richard Wang, Applications Engineering Manager, RF Micro Devices, Inc., and Ming-Hsiang Cho, Ph.D. Candidate, National Chiao-Tung University (Taiwan). You can download it from this link (it's free!).
Hint: S-parameters are used in RF circuits...
Hint: S-parameters are used in RF circuits...
Feb 26, 2007
Thin-film design guidelines
Did you ever wondered how thin-film transistors are made or what are the design rules you should use? I'm asking because, in order to get a proper model or to explain it to a designer (the final user of our models, let me remind you), you should be aware of all these things and how they affect to your model, because they are important. Diablo Industries, Inc. now has made available on-line a set of design rules and material description that is very interesting to read, even it you only perform a quick lecture.
Feb 23, 2007
Reliability
Another not-quite-in-topic entry. Today I was looking for information on a kind of defects (GOS) to get some information on how people do model them. I know this is not quite compact modeling, but you would be surprised on how much related they are. In fact, a GOS defect is usually modeled using a parasitic transistor. However, this is only an approximation, and a true physical model is still to come. I won't be the one developing it, though. I was only looking for some model that I could use with my transistor models. And, then, I found a gem. I've found a review paper (more than 20 pages!) about reliability. I think I'm going to use it as a textbook. You can access it here. The paper is:
Electronic circuit reliability modeling
Pages 1957-1979
J.B. Bernstein, M. Gurfinkel, X. Li, J. Walters, Y. Shapira and M. Talmor
Electronic circuit reliability modeling
Pages 1957-1979
J.B. Bernstein, M. Gurfinkel, X. Li, J. Walters, Y. Shapira and M. Talmor
Feb 22, 2007
European Microwave Week 2007 (EMW 2007) just after Oktoberfest!
This year the European Microwave Week (EMW) will take place in Munich, from October 8 to 12,...just after Oktoberfest!
The European Microwave Week is the main Microwave symposium in Europe. Besides, the European Microwave Exhibition constitutes the largest trade show on RF and microwaves in Europe.
EMW 2007 is composed of four conferences: the European Microwave Conference (EuMC), the European Conference on Wireless Technology (ECWT), the European Radar Conference (EuRAD), and the European Microwave Integrated Circuits (EuMIC).
EuMIC 2007 will be a very interesting conference and forum to present results on high-frequency compact modelling of semiconductor devices. Many of the indicated EuMIC topics can be related to compact modelling: Physics Based Device Modelling and Simulation, CAD Oriented Device Modelling, Noise Modelling, Linear and Non-linear CAD Techniques for Devices, Circuits & Systems (incl. Behavioural Modelling) (common Topic with EuMC), Linear CAD Techniques, Non-Linear CAD Techniques, Mixed-Signal Modelling.
Important: the deadline to submit summaries to EuMIC 2007 is February 25 2007!
I suggest high frequency compact model researchers to come one week earlier to Munich and start the compact modelling discussions while enjoying at the same time the Oktoberfest! For sure nice ideas can come then...
The European Microwave Week is the main Microwave symposium in Europe. Besides, the European Microwave Exhibition constitutes the largest trade show on RF and microwaves in Europe.
EMW 2007 is composed of four conferences: the European Microwave Conference (EuMC), the European Conference on Wireless Technology (ECWT), the European Radar Conference (EuRAD), and the European Microwave Integrated Circuits (EuMIC).
EuMIC 2007 will be a very interesting conference and forum to present results on high-frequency compact modelling of semiconductor devices. Many of the indicated EuMIC topics can be related to compact modelling: Physics Based Device Modelling and Simulation, CAD Oriented Device Modelling, Noise Modelling, Linear and Non-linear CAD Techniques for Devices, Circuits & Systems (incl. Behavioural Modelling) (common Topic with EuMC), Linear CAD Techniques, Non-Linear CAD Techniques, Mixed-Signal Modelling.
Important: the deadline to submit summaries to EuMIC 2007 is February 25 2007!
I suggest high frequency compact model researchers to come one week earlier to Munich and start the compact modelling discussions while enjoying at the same time the Oktoberfest! For sure nice ideas can come then...
Feb 19, 2007
Monte Carlo or Montecarlo?
I've had some nomenclature problems with this. To solve them, I've recurred to the easiest solution: I've 'googled' for it...
I've found a very interesting page at riskglossary. It seems that the first time it was cited explicitely was in this paper:
Metropolis, Nicholas and Stanislaw Ulam (1949). The Monte Carlo method, Journal of the American Statistical Association, 44 (247), 335-341
So, following the criteria that the first one to use it has the right to name it, I'll use "Monte Carlo" from now on.
I've found a very interesting page at riskglossary. It seems that the first time it was cited explicitely was in this paper:
Metropolis, Nicholas and Stanislaw Ulam (1949). The Monte Carlo method, Journal of the American Statistical Association, 44 (247), 335-341
So, following the criteria that the first one to use it has the right to name it, I'll use "Monte Carlo" from now on.
Feb 16, 2007
And more papers
It seems that this is my week to read papers. Well, it's a good exercise... I strongly recommend it!
Another quite interesting paper: Analytical Charge and Capacitance Models of Undoped Cylindrical Surrounding-Gate MOSFETs. This time, it is from Oana Moldovan et al. This is a quite good paper, that continues their work on DG MOSFETs.
Another one from the same journal: Modeling of Surrounding Gate MOSFETs With Bulk Trap States. It is also interesting to read. Anyway, the approach is different to the previous one, and it is good to keep an open mind.
And the last one from this journal: Surface-Potential Solution for Generic Undoped MOSFETs With Two Gates. The topic has been discussed before, and I still think that the approach by Francisco and Adelmo is easier to understand. However, this is only an opinion.
Another quite interesting paper: Analytical Charge and Capacitance Models of Undoped Cylindrical Surrounding-Gate MOSFETs. This time, it is from Oana Moldovan et al. This is a quite good paper, that continues their work on DG MOSFETs.
Another one from the same journal: Modeling of Surrounding Gate MOSFETs With Bulk Trap States. It is also interesting to read. Anyway, the approach is different to the previous one, and it is good to keep an open mind.
And the last one from this journal: Surface-Potential Solution for Generic Undoped MOSFETs With Two Gates. The topic has been discussed before, and I still think that the approach by Francisco and Adelmo is easier to understand. However, this is only an opinion.
Miscellanea
More of my personal obsession: plastic electronics. This week, in the 3GSM Conference, in Barcelona, Polymer Vision has presented (some people would say 'again') the Readius, which is a mobile phone with an integrated roll-up display. It seems that this time they are serious, thanks to Plastic Logic....
Another curious thing: for all those of you that love playing sudoku, you now may have a hard competitor: a quantum computer. I don't know how actually serious this is. However, I think that it may be indicative that people is starting to crave for quantum computers. The first step to be able to produce them should be letting people (engineers) how they work. So we need compact models for that. Anyway, I think that we're still a long way from the point where computers designers can actually use this.
Another curious thing: for all those of you that love playing sudoku, you now may have a hard competitor: a quantum computer. I don't know how actually serious this is. However, I think that it may be indicative that people is starting to crave for quantum computers. The first step to be able to produce them should be letting people (engineers) how they work. So we need compact models for that. Anyway, I think that we're still a long way from the point where computers designers can actually use this.
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