Well, another update on some IEEE publications. I've got three papers quite related to compact modeling:
"An analytical Compact Model for Nanowire FET", by B.C. Paul et alter, in IEEE Trans. on Electron Devices.
"Explicit Analytical Charge and Capacitance Models of Undoped Double-Gate MOSFETs", by O. Moldovan et alter, also in IEEE Trans. on Electron Devices.
"Limits of Performance Gain of Aligned CNT Over Randomized Network: Theoretical Predictions and Experimental Validation", by N. Pimparkar et alter, in IEEE Electron Device Letters.