Tuesday, 6 March 2007

Threshold voltage models

As each month, I've been performing a review of some of the more interesting literature. Today, I'll point out three papers, all of them in the current issue of IEEE Trans. El. Devices, and all three of them dedicated to threshold voltage modeling.
The first one is Threshold-Voltage Modeling of Body-Tied FinFETs (Bulk FinFETs), by Choi, B.-K. Han, K.-R. Kim, Y. M. Park, Y. J. Lee, J.-H. Someday I shall comment something about threshold voltage extraction methods, because it is quite interesting. However, this will not be today.
The second paper is
Compact Analytical Threshold-Voltage Model of Nanoscale Fully Depleted Strained-Si on Silicon–Germanium-on-Insulator (SGOI) MOSFETs by Venkataraman, V.; Nawal, S.; Kumar, M. J. I think that the title is quite self-explanatory.
Finally, the third one is Analytical Model of the Threshold Voltage and Subthreshold Swing of Undoped Cylindrical Gate-All-Around-Based MOSFETs, by some friends: Hamdy El Hamid; Iniguez, B.; Roig Guitart, J.
There is a point I'd like to make: all of them are dedicated to different devices, using different technologies. This is a demostration that Iroshi Iwai is right when he says that we've got work for still some fourty or fifty years more, and that it will be possible to evade the classic Moore's Law (perhaps it should be called Moore's Guideline).

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