Friday, 23 February 2007


Another not-quite-in-topic entry. Today I was looking for information on a kind of defects (GOS) to get some information on how people do model them. I know this is not quite compact modeling, but you would be surprised on how much related they are. In fact, a GOS defect is usually modeled using a parasitic transistor. However, this is only an approximation, and a true physical model is still to come. I won't be the one developing it, though. I was only looking for some model that I could use with my transistor models. And, then, I found a gem. I've found a review paper (more than 20 pages!) about reliability. I think I'm going to use it as a textbook. You can access it here. The paper is:

Electronic circuit reliability modeling

Pages 1957-1979
J.B. Bernstein, M. Gurfinkel, X. Li, J. Walters, Y. Shapira and M. Talmor

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