Semiconductor Devices Characterization Seminar

Technical Seminars addressing the challenges of CMOS, Power and RF

semiconductor device measurement and modeling 

Agilent and it´s 25 collaborative partners invite you to attend this complimentary technical seminar on characterization and modeling of semiconductor devices. Two tracks in parallel will address the needs for:

• Small scale silicon industry
• Power silicon industry and RF Power

Common topics to both Tracks:

• Live demonstration of GaN device characterization flow: DC I-V characteristic extraction, RF Power measurement, Spice models creation for further usage in design stage.

CMOS Track:

• Accurate and repeatable on-the-wafer device extraction – Cascade Microtech
• DC characterization for emerging nano-technologies
• Flicker Noise and Random Telegraph Noise
• Spice model libraries optimization for dedicated application

Power & RF Power Track:

• High Power Devices measurement
• III-V devices spice model (DynaFET)
• Nonlinear Component characterization
• Non-50ohm Load Pull solution – Maury

Where/when:
To obtain the detail agenda of the nearest session, please select one of the locations below.

Country	City	Date	More Information
FR	Grenoble	18 September 2014	Register here
FI	Helsinki	23 September 2014	Register here
DE	Munich	30 September 2014	Register here
DE	Dresden	2 October 2014	Register here
CH	Lausanne	14 October 2014	Register here
BE	Leuven	16 October 2014	Register here
NL	Eindhoven	17 October 2014	Register here
SW	Goteborg	28 October 2014	Register here
UK	Cambridge	30 October 2014	Register here
FR	Les Ulis	6 November 2014	Register here

 

 

i-MOS version 201407 release

 The i-MOS team has announced new release of the interactive Modeling and On-line Simulation Platform (i-MOS), version 201407. Through the Developer module launched in April, the UMEM model for organic thin film transistors has been integrated with i-MOS for users' evaluations and applications. Another model implemented is the BSIM4 (version 4.0.0), together with model collections from the Predictive Technology Models.  

Any comments and other equerries can be addressed to
Lining Zhang,
PhD i-MOS Project Manager
The Hong Kong University of Science & Technology

[SISPAD] Compact Modeling Worksops - Enabling Better Insight of Device Features - Monday, September 8, 2014

 SISPAD Compact Modeling Workshop
 Enabling Better Insight of Device Features 

 Monday, September 8, 2014

 Workshop Program

09:15 - 09:20: Opening 

09:20 - 10:00: J. Takeya (University of Tokyo, Japan): invited Physics of Charge Transport in Organic Field-Effect Transistors
10:00 - 10:40: C. Jungemann (RWTH Aachen University, Germany): invited Validity of Macroscopic Noise Models in the Case of High-Frequency Bipolar Transistors

10:40 - 11:00: break

11:00 - 11:40: N. Goldsman (University of Maryland, USA): invited Key Issues in the Modeling of SiC Electronic Devices
11:40 - 12:10: C. Ma (Hiroshima University, Japan): invited Universal Model of the Negative Bias Temperature Instability (NBTI) Effect for Circuit Aging Simulation

12:10 - 12:30: poster presentations

• P. X. Tran (International University, Vietnam) A Comprehensive Model for the Changing I-V Characteristics of raphene Transistors 
• M. Ghittorelli, F. Torricelli, Z. M. Kovacs-Vajna, and L. Calalongo (University of Brescia, Italy) Accurate Modeling of Amorphous Indium-Gallium-Zinc-Oxide TFTs Deposited on Plastic Foil 
• S. Sato, Y. Omura, and A. Mallik (Kansai University, Japan) Proposal of Simple Channel-Length-Dependent Current Model for Subthreshold Region of Nano-Wire Tunnel FET 
• H. Miyamoto, H. Zenitani, H. Kikuchihara, H. J. Mattausch, M. Miura-Mattausch, and T. Nakagawa (HU & AIST, Japan) Consistent Compact Modeling of MOSFETs from Bulk to Double-Gate Structures

12:30 - 13:50: lunch

13:50 - 14:30: D. Warning (Creative Chips GmbH, Germany): invited NGSPICE – an Open Platform for Modeling and Simulation
14:30 - 15:00: A. Schaldenbrand (Cadence Design Systems, Japan): invited Benefits of Verilog-A for Behavioral Modeling and Compact Modeling
15:00 - 15:30: P. Lee (Micron Memory Japan, Inc.): invited Compact Model Coalition: World-Wide Model Standardization for an Expanding Industry

15:30 - 15:40: break

15:40 - 16:00: F. Torricelli, M. Ghittorelli, M. Rapisarda, L. Mariucci, S. Jacob, R. Coppard, E. Cantatore, Z. M. Kovacs-Vajna, and L. Colalongo (Unviersity of Brescia, Italy) Analytical Drain Current Model of Both p- and n-Channel OTFTs for Circuit Simulation
16:00 - 16:20: T. Nakagawa, T. Sekigawa, M. Hioki, Y. Ogasahara, H. Koike, H. Zenitani, H. Miyamoto, H. Kikuchihara, H. J. Mattausch, M. Miura-Mattausch, H. Oda, and N. Sugii (AIST, HU, LEAP, Japan) Parameter-Extraction Strategy of Ultra-Thin Silicon and BOX Layer MOSFETs for Low Voltage Applications
16:20 - 16:40: T. Mizoguchi, T. Naito, Y. Kawaguchi, and W. Hatano (Toshiba, Japan) Compact Modeling of GaN-MISFET for Power Applications
16:40 - 17:00: T. Yamamoto and H. Kato (Denso, Japan) Analysis and Modeling of Injection Enhanced Insulated Gate Bipolar Transistor

17:00: Closing

ESSDERC/ESSCIRC 2014 - Full conference program is now available

The technical program, tutorial program, and workshop program of ESSDERC/ESSCIRC 2014
are now available at  ESSDERC/ESSCIRC 2014  website: http://www.esscirc-essderc2014.org 

Please remember to register to the conference and book a hotel room at before June 20, after 
which we cannot guarantee that you will find a hotel room at our rebated prices.

The event is technically co-sponsored by the
    IEEE Electron Device Society,
    IEEE Solid-State Circuit Society
    IEEE Circuits and Systems Society

We hope to see you in Venice

Best Regards  Gaudenzio Meneghesso
ESSDERC/ESSCIRC 2014  General Chair

Roberto Bez and Paolo Pavan
ESSDERC 2014 TPC Chairs

Pietro Andreani and Andrea Bevilacqua 
ESSCIRC 2014 TPC Chairs


JOINT PLENARY TALKS 
Scott DeBoer, Micron, ID, USA, A Semiconductor Memory Manufacturing and Development Perspective
Thomas H. Lee, Stanford University, CA, USA Terahertz Electronics: The Last Frontier 
Fabio Marchiò, STMicroelectronics, Italy, Automotive Electronics: Application & Technology Megatrends
Walter Snoeys, CERN, Switzerland, How Chips Helped Discover the Higgs Boson at CERN
An Steegen, IMEC, Belgium, Logic Scaling Beyond 10nm, a Power-Performance-Area-Cost Trade-off 
Sehat Sutardja, Marvell Semiconductor, CA, USA Tremendous Benefits of Moore’s Law Have Yet to Come

ESSCIRC PLENARY TALKS
Hooman Darabi, Broadcom Corporation, CA, USA Blocker Tolerant Software Defined Receivers

Un-Ku Moon, Oregon State University, OR, USA Emerging ADCs
Kathleen Philips, IMEC-Holst Centre, The Netherlands Ultra-Low Power Short Range Radios

ESSDERC PLENARY TALKS
Umesh Mishra, UCSB and TRanphorm, CA, USA,  GaN-based solutions from KHz to THz 

Eric Pop, Stanford University, CA, USA, Energy Efficiency and Conversion in 1D and 2D Electronics
Takao Someya, University of Tokyo, Japan Bionic Skins Using Flexible Organic Devices

ESSCIRC TUTORIALS

Power Management for SoCs (Full Day), Organizer: Christoph Sandner, Infineon, Austria
High Performance Amplifiers (Half Day), Organizer: Angelo Nagari, STMicroelectronics, France
Phase Noise: from Fundamentals to Circuit Aspects (Half Day) Organizer: Christian Enz, EPFL, Switzerland

ESSDERC TUTORIALS
CMOS Technology at the nm Scale Era (Full Day) Organizer: Maud Vinet, CEA LETI, France

RRAM: from Technology to Applications (Half Day) Organizer: Bogdan Govoreanu, IMEC, Belgium 
3D: from Technology to Applications (Half Day) Organizer: Pascal Vivet, CEA LETI, France

ESSDERC/ESSCIRC Workshops
Beyond-CMOS for advanced More Moore and More than Moore applications 
Organizers: Francis Balestra and Enrico Sangiorgi, Sinano Institute - Grenoble INP/CNRS, France
MOS-AK: Over Two Decades of Enabling Compact Modeling R&D Exchange   
Organizer: Wladek Grabinski, MOS-AK Group (EU),
Status of the GaN and SiC based device development   
Organizer: Enrico Zanoni, University of Padova, DEI, Italy
THz-Workshop: Millimeter- and Sub-Millimeter-Wave circuit design and characterization   
Organizer: Thomas Zimmer, University Bordeaux, France
Marie Curie ATWC   
Organizer: Rinaldo Castello, University of Pavia and Marvell, Italy

[mos-ak] 12th MOS-AK Workshop at the ESSDERC/ESSCIRC Conference in Venice

 Autumn MOS-AK Workshop in Venice 

 

Together with the MOS-AK Workshop Scientific Program Coordinators Larry Nagel and Andrei Vladimirescu as well as Extended MOS-AK TPC Committee, we have pleasure to invite to the 12th consecutive MOS-AK at the ESSDERC/ESSCIRC Conference.

Venue:

Palazzo del Casinò

Lungomare Marconi, 30

30126 Venice Lido, Italy

Important Dates:

Call for Papers - May 2013
2nd Announcement - June 2014
Final Workshop Program - Aug. 2014
MOS-AK Workshop - Friday, Sept. 26, 2014

 8:30 -  9:00 - On Site Registration

 9:00 - 12:00 - Morning MOS-AK Session

12:00 - 13:00 - Buffet Lunch  

13:00 - 16:00 - Afternoon MOS-AK Session

Topics to be covered include the following:

Advances in semiconductor technologies and processing

Compact Modeling (CM) of the electron devices

Verilog-A language for CM standardization

New CM techniques and extraction software

Open Source TCAD/EDA modeling and simulation

CM of passive, active, sensors and actuators

Emerging Devices, CMOS and SOI-based memory cells

Microwave, RF device modeling, high voltage device modeling

Nanoscale CMOS devices and circuits

Technology R&D, DFY, DFT and IC Designs

Foundry/Fabless Interface Strategies

Abstract Submission:

Authors should submit an abstract using on-line MOS-AK submission form (any related enquiries can be sent to abstracts@mos-ak.org)

Postworkshop publications:

selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK/GSA Committee

[WG 052014]

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IJNM Call for Papers

Advances in simulation-driven modeling and optimization of microwave/RF circuits

IJNM Call for Papers

Computer-aided modeling and design of microwave/radio frequency (RF) devices and circuits have undergone tremendous developments in the past decade. The complexity of today's devices and circuits renders electromagnetic (EM) simulation a sine qua non in the microwave design process. That said, EM-driven design poses significant challenges, mostly due to the high computational cost of accurate, high-fidelity simulation. The availability of massive computational resources does not always translate into design speedup because of the need to account for interactions between devices and their surroundings as well as multi-physics (e.g., EM-thermal) effects. Not surprisingly, traditional design optimization procedures that directly utilize EM-simulated responses typically fail or are impractical. As a consequence, there is growing interest in alternative optimization and modeling methodologies, especially ones that exploit computationally cheap surrogate models.

This Special Issue focuses on the current state of the art and future directions in microwave and RF design. Papers on software engineering and practical applications aspects are also encouraged. Suitable topics for this Special Issue therefore include but are not limited to

• surrogate-based modeling and optimization methods including space mapping;
• knowledge-based and tuning methodologies;
• global optimization, evolutionary algorithms, particle swarm optimization, and so on;
• multi-objective optimization;
• adjoint-sensitivities for efficient gradient-based optimizers;
• optimization techniques for nonlinear circuits;
• software architectures for optimization-oriented design;
• automated design optimization using EM simulators;
• optimization for inverse EM problems;
• neural network approaches; and
• optimization for discrete problems.

Manuscripts for this Special Issue should adhere to the requirements for regular papers of the IJNM as specified in the Author Guidelines at http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1099-1204/homepage/ForAuthors.html

Potential contributors may contact the guest editor to determine the suitability of their contribution to the Special Issue. All manuscripts should be submitted via the IJNM's manuscript website http://mc.manuscriptcentral.com/ijnm, with a statement that they are intended for this Special Issue.

Manuscript submission deadline: January 31, 2015

Prof. Slawomir Koziel
Engineering Optimization and Modeling Center, 
School of Science and Engineering, 
Reykjavik University, Reykjavik, Iceland

1. 
   

[mos-ak] [Summary] Spring MOS-AK Workshop in London

 MOS-AK Compact Modeling Workshop

 London Metropolitan University

 March 28-29, 2014 London

 

The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, delivered its annual spring compact modeling workshop on March 28-29, 2014 at London Metropolitan University. The event received full sponsorship from leading industrial partners including Agilent Technologies, MOSIS Services and Tanner EDA. The technical MOS-AK program promoters included Eurotraining, IET, IEEE UKRI Section as well as EDA Solutions. More than 40 registered academic researchers and modeling engineers attended two sessions to hear 9 technical compact modeling presentations including the QUCS Tutorial by Prof. Mike Brinson.

 

The workshop summary has been posted thru the semiwiki.com blog and all the MOS-AK presentations are available for downloads here.

 

The MOS-AK/GSA Modeling Working Group is coordinating several upcoming modeling events to focus on the Verilog-A compact model standardization as well as open source circuit simulation tool developments: 

• 3rd Training Course on Compact Modelling, TCCM, Lublin (PL), June 18, 2014
  
• a special compact modeling session at the MIXDES'14 Conference in Lublin (PL), June 19-21, 2014
  
• an autumn MOS-AK/ESSDERC/ESSCIRC workshop in Venice (I), Sept. 26, 2014
  
• MOS-AK Q4 Workshop San Francisco (US), Dec. 2014

In the meantime, please also visit www.mos-ak.org where we will continue the discussions of all compact/SPICE modeling topics and its Verilog-A standardization.

--WG--V2014

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[mos-ak] CUSPICE: CUDA-accelerated NGSPICE release available immediately

 Recently, Francesco Lannutti, NGSPICE lead developer, has announced the CUSPICE: CUDA-accelerated NGSPICE release. The NVIDIA has recognised importance of the open source CAD/EDA tools and gave the permission to release CUSPICE as an integral part of the NGSPICE simulation platform. New NGSPICE extension is available immediately on the NGSPICE repository, in the branch named 'CUSPICE'. 

 At the moment only BSIM4v7, CAP, IND, ISRC, RES and VSRC device models are supported by the CUSPICE simulator. With broad acceptance of the NGSPICE simulation platform, we can expect other standard models and new extensions developed, soon. 

[read more...]

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[Abstracts Due Extended] 2014 NanoTech Workshop on Compact Modeling

 NanoTech Workshop on Compact Modeling Important Dates:

• Late Poster Abstracts Due: Rolling Submissions - May 15
• Notification: Rolling Notification Date

Authors of research submissions, upon acceptance, must register for the conference. [read more...]

Devices That You Definitely Will (and Just Might) Use: Emerging Transistor Technologies for the Near-and Long-Term

 WEDNESDAY June 04, 4:00pm - 6:00pm | Room 302 

 TRACK: EDA

 TOPIC AREA: EMERGING TECHNOLOGIES

 SPECIAL DAC SESSION 63: Devices That You Definitely Will (and Just Might) Use: Emerging Transistor Technologies for the Near-and Long-Term

Chair:  Michael Niemier; Univ. of Notre Dame, IN
Organizers:  Michael Niemier; Univ. of Notre Dame, IN
Xiaobo Sharon Hu; Univ. of Notre Dame, IN

Want to learn about the latest developments in FinFET-based processor design? What other transistor technologies might follow FinFETs and would they bring new design and modeling challenges? Come to this session to hear about both near- and long-term transistor technologies and their prospects for continuing Moore’s Law-based performance scaling trends. The session will begin with a discussion of FinFET technology; subsequent presentations will discuss tunnel transistors (TFETs) as well as other emerging FET technologies that could reenable voltage scaling. The session will conclude with a discussion of modeling efforts that consider the impact of new device technologies on von Neumann architectures as well as hybrid analog/digital circuits and architectures.

63.1 FinFET's and Their Implications for Design Now and in the Future

• Speaker: Rob Aitken; ARM Ltd., San Jose, CA
  Greg Yeric; ARM Ltd., Austin, TX
  Brian Cline; ARM Ltd., Austin, TX
  Lucian Shifren; ARM Ltd., San Jose, CA

63.2 Emerging Devices for Logic: Can a Low-Power Switch Be Fast?

• Speaker: Thomas Theis; IBM T.J. Watson Research Center, Yorktown Heights, NY

63.3 Energy Efficient Tunnel-FET Transistors for Beyond CMOS Logic

• Speaker: Uygar Avci; Intel Corp., Portland, OR
  Daniel Morris; Intel Corp., Portland, OR
  Ian Young; Intel Corp., Hillsboro, OR

63.4 Steep Slope Devices: Enabling New Architectural Paradigms

• Speaker: Vijaykrishnan Narayanan; Pennsylvania State Univ., State College, PA
  Karthik Swaminathan; Pennsylvania State Univ., State College, PA
  Huichu Liu; Pennsylvania State Univ., State College, PA
  Moon Seok Kim; Pennsylvania State Univ., State College, PA
  Xueqing Li; Pennsylvania State Univ., State College, PA
  Jack Sampson; Pennsylvania State Univ., University Park, PA

[more about the DAC Conference]

[mos-ak] [on-line publications] Spring MOS-AK Workshop in London

  

Recent, Spring MOS-AK Workshop at the London Metropolitan University was organized to discuss SPICE/compact modeling and its standardization with following Qucs GPL circuit simulation tutorial. The workshop's presentations are available on-line at <http://www.mos-ak.org/london_2014/>.

   

Please also distribute further information about next MOS-AK related events among all who are interested in the SPICE/compact modeling and its Verilog-A standardization:

• 3rd International Training Course on Compact Modelling (TCCM) Lublin (PL) June 18, 2014
• http://compactmodelling.eu/tccm3_about.php
• MIXDES Special Compact Modeling Session, Lublin (PL) June 19-21, 2014
• http://www.mixdes.org/Mixdes3/tekst/view/special
• 12th MOS-AK ESSDERC/ESSCIRC Workshop, Venice (I) Sept. 26, 2014
• http://www.mos-ak.org/venice_2014/
• 7th International MOS-AK Workshop San Francisco (US) Dec. 2014
• http://www.mos-ak.org/

Already now, I am looking forward to meet you at one of our MOS-AK modeling events, soon.

-- with regards - wladek for the Extended MOS-AK/GSA Committee;

--

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

--

Over two decades of Enabling Compact Modeling R&D Exchange

--

http://www.mos-ak.org

-- 

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i-MOS version 201404 release

The i-MOS Team has announced  new release of the interactive Modeling and On-line Simulation
Platform (i-MOS), version 201404. In this release, there are several new services listed as follows:

• Integrating the model benchmark testing suites in Model page
• Including first three benchmark tests for model evaluations
• Constructing the Developer page for device model submissions
• Implementing one industry standard MOSFET model HiSIM2
• Uploading presentation files from IWCM 2014 for your references

For more details, please visit the i-MOS website.

ESSDERC/ESSCIRC 2014 - Paper submission deadline extension

the Organizing Committee decided to extend the paper submission deadline of the 44th ESSDERC and 40th ESSCIRC to:

April 16th, 2014 23:59 (GMT - 07:00 am)

This is a hard deadline and no further extensions will be granted. After the deadline is elapsed, further paper submissions will not be accepted. The notification of paper acceptance, May 27, 2014, has not changed. Detailed information about the conferences is provided at the ESSCIRC/ESSDERC 2014 website.

[read more...]

VI Regional Seminar MNE & MS 2014

VI Regional Seminar on Computer Modeling and Designing in Micro- and Nanoelectronics and in Microelectromechanical Systems (MNE & MS 2014),

Orel, Russia, March 28 2014

1. С.И. Матюхин¹, Welcome and Seminar Openning,
   ¹Госуниверситет-УНПК
2. Турин В.О.¹, Кильчицкая М.В.², Герасимов К.А.², Simulation of power bipolar transistor,
   ¹Госуниверситет-УНПК, ²БГТУ, г. Брянск
3. Ващенко В.А., The physical ESD design for integrated circuits and electronic devices,
   Maxim Integrated Corp., г. Сан Хосе, Калифорния, США
4. Цырлов А.М., Development of CMOS optocoupler,
   ОАО «Протон», г. Орёл
5. Студенников А.С., Development of CMOS ICs,
   ОАО «Протон», г. Орёл
6. Малый Д.О.¹, Матюхин С.И.², Ставцев А.В.¹, "Proton-Elektroteks" IGBT-devices JSC: basic approaches of production and quality assurance,
   ¹ЗАО «Протон-Электротекс», г. Орёл, ²Госуниверситет-УНПК
7. Макулевский Г.Р., Матюхин С.И., Current-voltage characteristics of laser diodes based on AlGaAs,
   Госуниверситет-УНПК
8. Матюхин С.И., Гришин В.О., Radiation effects of on the current-voltage characteristic of power diodes and thyristors,
   Госуниверситет-УНПК
9. Писарев А.А.¹, Матюхин С.И.², Сурма А.М.¹, Черников А.А.¹, Electrical characteristics of fast diodes with soft recovery,
   ¹ЗАО «Протон-Электротекс», г. Орёл, ²Госуниверситет-УНПК
10. Koziol Z., Aestimo quantum mechanical software for modeling quantum wells in nanoelectronics,
    TU Rzeszow, Polska

The ITRS, 2013 Edition is now online.

 The link below will take you to the site for the summary information
http://www.itrs.net/Links/2013ITRS/Summary2013.htm

 For the full edition details, follow this link
http://www.itrs.net/Links/2013ITRS/Home2013.htm

[read more...]

Possible VTH Variation Sources

with 16 nm FinFET devices, the nature of the VTH variation changes.  On planar CMOS, random dopant fluctuations (RDFs) had the biggest influence. 

Possible VTH Variations

Ideal FinFETs have no doping, and therefore no RDFs.  However, this only works for low voltage operation.  We also need high-speed devices, which requires multiple threshold voltages (Vth's).  For FinFETs, this requires doping leading to RDF variation.  

[read more at DeepChip ...]

New IJNM Paper

 
Open-source circuit simulation tools for RF compact semiconductor device modelling (Invited Paper)
 
Wladek Grabinski (Editor), Mike Brinson, Paolo Nenzi, Francesco Lannutti, Nikolaos Makris, Angelos Antonopoulos and Matthias Bucher
 
Keywords:
CAD; GNU; Qucs; QucsStudio; ngspice; compact modelling; EKV3; RF; MOSFET; Verilog-A
 
Article first published online: 18 MAR 2014 DOI: 10.1002/jnm.1973

website http://www.tcad.com is up and running

The www.tcad.com website promoting open source Technology Computer Aided Design and posting related news is up and running. Among other news there is also update of the DEVSIM Open Source TCAD Simulator which is available for download at SourceForge, now.  Packages are available for:

• Mac OS X Mavericks
• Red Hat 6.5
• Ubuntu 12.04

For more information about the project, including source code availability, please visit DEVSIM webpage. Additional resource are also available at the TCADCentral 

[source]

Free And Open Source Simulator Software For Engineers

Free And Open Source Simulator Software For Engineers

0. Qucs
Download Link: http://qucs.sourceforge.net/download.html
Supported OS: Windows, Linux, Mac OSX
License:  Qucs is released under the GPL license and so it is free for free programmers and users !
Qucs stands for Quite Universal Circuit Simulator. So far Qucs is not yet finished, but it is already packed with features. Take a look at the screenshots to get a feel for what it can do.

1. CEDAR
Download Link: http://sourceforge.net/projects/cedarlogic/files/latest/download
Supported OS: Windows
License: Freeware
CEDAR LS is an interactive digital logic simulator to be used for teaching of logic design or testing simple digital designs. It features both low-level logic gates as well as high-level components, including registers and a Z80 microprocessor emulater

2. Logisim
Download Link: http://sourceforge.net/projects/circuit/files/latest/download
Supported OS: Windows, Linux
License: Freeware
Logisim is an educational tool for designing and simulating digital logic circuits. With its simple toolbar interface and simulation of circuits as you build them, it is simple enough to facilitate learning the most basic concepts related to logic circuits.

3. FreeMat
Download Link: http://sourceforge.net/projects/freemat/files/latest/download?source=files
Supported OS: Windows, Linux
License: GPL
FreeMat is a free environment for rapid engineering and scientific prototyping and data processing. It is similar to commercial systems such as MATLAB from Mathworks, and IDL from Research Systems, but is Open Source. FreeMat is available under the GPL license.

4. Logic Gate Simulator
Download Link: http://sourceforge.net/projects/gatesim/files/latest/download
Supported OS: Windows
License: GPL
Logic Gate Simulator is an open-source tool for experimenting with and learning about logic gates. Features include drag-and-drop gate layout and wiring, and user created "integrated circuits".

5. Maxima
Download Link: http://sourceforge.net/projects/maxima/files/latest/download?source=recommended
Supported OS: Windows
License: GPL
Maxima is a fairly complete computer algebra system written in Common Lisp with an emphasis on symbolic computation.

6. Ngspice
Download Link: http://sourceforge.net/project/showfiles.php?group_id=38962
Supported OS: Windows, Linux
License: GPL
Ngspice is a mixed-level/mixed-signal circuit simulator. Its code is based on three open source software packages: Spice3f5, Cider1b1 and Xspice. Ngspice is part of gEDA project, a full GPL'd suite of Electronic Design Automation tools.

7. Qfsm
Download Link: http://sourceforge.net/projects/qfsm/files/latest/download
Supported OS: Windows, Linux
License: GPL
A graphical tool for designing finite state machines

8. QSapecNG
Download Link: http://sourceforge.net/projects/qsapecng/files/latest/download?source=directory
Supported OS: Windows
License: GPL
QSapecNG is a Qt-based symbolic analysis program for linear analog circuits. In fact, it consists of two indipendently parts: the SapecNG framework engine, and the application gui QSapecNG.

[source for 1-8]

SISPAD2014: 2nd Call for Papers

Second Call for Papers

SISPAD2014

September 9 – 11, 2014

Workshop, September 8, 2014

Mielparque Yokohama, Yokohama, JAPAN

Co-sponsored by Japan Society of Applied Physics Technical 

Co-sponsored by IEEE Electron Devices Society

This conference provides an opportunity for the presentation and discussion of the latest advances in modeling and simulation of semiconductor devices, processes, and equipment for integrated circuits.

Topics:

• Modeling and simulation of all sorts of semiconductor devices, including FinFETs, ultra-thin SOI devices, emerging memory devices, optoelectronic devices, TFTs, sensors, power electronic device, widegap semiconductor devices, spintronic devices, tunnel FETs, SETs, carbon-based nanodevices, organic electronic devices, and bioelectronic devices
• Modeling and simulation of all sorts of semiconductor processes, including first-principles material design and growth simulation of nano-scale fabrication
• Fundamental aspects of device modeling and simulation, including quantum transport, thermal transport, fluctuation, noise, and reliability
• Compact modeling for circuit simulation, including low-power, high frequency, and power electronics applications
• Process/device/circuit co-simulation in context with system design and verification
• Equipment, topography, lithography modeling
• Interconnect modeling, including noise and parasitic effects
• Numerical methods and algorithms, including grid generation, user-interface, and visualization
• Metrology for the modeling of semiconductor devices and processes

Plenary Speakers:

• Augusto Benvenuti, Micron Technology,
  “Current status and future prospects of non-volatile memory modeling”
• Massimo V. Fischetti, University of Texas at Dallas,
  “Physics of electronic transport in low-dimensionality materials for future FETs”
• Kimimori Hamada, Toyota Motor Corporation,
  “TCAD challenge on development of power semiconductor devices for automotive applications”

Invited Speakers:

• Mario Ancona, Naval Research Laboratory,
  “Nonlinear thermoelectroelastic simulation of III-N devices”
• Asen Asenov, University of Glasgow,
  “Progress in the simulation of time dependent statistical variability in nano CMOS transistors”
• Jean-Pierre Colinge, Taiwan Semiconductor Manufacturing Company,
  “Nanowire transistors: pushing Moore's law to the limit”
• Tibor Grasser, Vienna University of Technology,
  “Advanced modeling of charge trapping: RTN, 1/f noise, SILC, and BTI”
• Kohji Mitsubayashi, Tokyo Medical and Dental University,
  “Novel biosensing devices for medical applications”
• Christian Sandow, Infineon Technologies,
  “Exploring the limits of the safe operation area of power semiconductor devices”
• Mark Stettler, Intel Corporation,
  “Device and process modeling: 20 years at Intel's other fab”

Workshops:

Two companion workshops will run concurrently prior to the start of the conference on Monday September 8, 2014:

• Compact Modeling "Enabling Better Insight of Device Features"
  Organizer: Mitiko Miura-Mattausch (Hiroshima University)
• Carrier Transport in Nano-Transistors: Theory and Experiments
  Organizer: Hideaki Tsuchiya (Kobe University) and Yoshinari Kamakura (Osaka University)

Abstract Submission: 

Authors are invited to submit a two-page abstract (A4 or 22×28cm) including figures. Full submission information is available at the ing web page: <https://sites.google.com/site/sispad2014/>. Authors of accepted papers will be notified by May 15, 2014. Camera-ready copy of a four-page manuscript will be required from the authors for inclusion in the Conference Proceedings by June 30, 2014.

Deadline for submission of abstract: March 31, 2014

Chip in Aracaju 2014 - Call for Papers

27th SBCCI 2014 29th SBMICRO 2014 4th WCAS 2014
September 1st to 5th 2014, Aracaju (SE), Brazil         

http://www.chip-in-aracaju.ufs.br

CHIP IN ARACAJU 2014 Conference to be held in the city of Aracaju, Brazil, from September 1^st to 5^th 2014. The conference co-locates two main symposia (SBCCI, SBMicro), one student forum (SFORUM), one workshop (WCAS) and the industrial exhibition.

27^th SBCCI (Symposium on Integrated Circuits and Systems Design) is an international symposium with an estimated attendance of about 200 experts from academia and industry. Among those 25% are expected to come from outside Brazil. This symposium represents the main event in chip design and design automation in Brazil. It is co-sponsored by the Brazilian Computing Society (SBC), the Brazilian Microelectronics Society (SBMicro), ACM SigDA and, the IEEE Circuits and Systems Society (CASS), and IFIP W 10. The proceedings will be published by the IEEE and will remain available at the IEEE Xplore and ACM Digital Library. 

Abstract Submission: March 23^th 2014          

Paper Submission Deadline: March 30^th 2014

Call for papers: 

http://www.chip-in-aracaju.ufs.br/archives/CFP%20-%20SBCCI2014.pdf

SBMicro 2014 (29^th Symposium on Microelectronics Technology and Devices) is an international symposium that usually counts with about 100 attendees focusing on process technologies. It is co-sponsored by the Brazilian Microelectronics Society (SBMicro), the Brazilian Computing Society (SBC), the Electrochemical Society (ECS) and, the IEEE Electron Devices Society (EDS). The proceedings will be published by the IEEE and ECS Digital Library.

Submission Deadline: March 31^th 2014        

Notification of Acceptance: May 18^th, 2014

Call for papers: 

http://www.chip-in-aracaju.ufs.br/archives/CFP%20-%20SBMICRO2014.pdf

WCAS 2014 (4th Workshop on Circuits and System Design) is devoted to the presentation and discussion of design experiences with a high degree of relevance in industrial and educational contexts, as well as innovative design methodologies and applications of specific design technologies in an industrial context. The main idea of the workshop is to offer the chance (primarily to industry) of pointing out to the community real-life design and technology challenges that should be addressed in the short-to-medium term.

Submission deadline (2 to 4 pages): June 1^st 2014        

Acceptance notification: July 13^th

Call for papers: http://www.chip-in-aracaju.ufs.br/archives/CFP%20WCAS2014.pdf

SFORUM 2014 (14th Microeletronics Students Forum) is an event promoted by the Brazilian Microelectronics Society (SBMicro) and the Brazilian Computer Society (SBC).

Paper Submission Deadline:June 2^nd 2014         

Notification of Acceptance: July 16^th, 2014

Call for papers: 

http://www.chip-in-aracaju.ufs.br/archives/SFORUM2014CFP.pdf

Companies and Industries: In addition to the technical sessions associated with the regular papers, each symposium normally invites 6 distinguished speakers to present tutorials and invited talks on state-of-the art topics. Furthermore, traditionally, the conference includes an exhibition with stands for microelectronics and

electronic vendors.

[mos-ak] [Final Program] Spring MOS-AK Workshop in London

Spring MOS-AK Workshop in London

Together with the workshop host, Prof. Bal Virdee, Londonmet, FIET MIEEE, and Prof. Mike Brinson, Londonmet, as well as Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the spring MOS-AK Workshop in London

Venue:

London Metropolitan University 

Graduate Centre

166-220 Holloway Road

London N7 8DB

Workshop Agenda <http://www.mos-ak.org/london_2014/>: 

with On-line Free Registration 

• March 28, 2013
  
• 9:00-9:30 Open On-site Registration 
• 9:30-12:00 Morning Session
  
• 13:00-16:00 Afternoon Session
• 17:00-19:00 Welcome Reception and Networking
• March 29, 2013
  
• 9:00-12:00 Qucs and ngspice GPL circuit simulation session

Extended MOS-AK/GSA Committee

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14 Free Resources To Learn About MOSFETs

Metal Oxide Field Effect Transistors (MOSFET) are commonly used for amplifying or switching electronic signals. They have a wide usage in the field and learning about these is crucial for any electronic engineer. So, with that in mind, here are 14 resources that will get you up and running!

[Tutorials, Videos, Free Reference Materials at efytimes.com]

Custom IC Design & Device Modeling - Tools and Technologies

Synopsys University Symposium

Friday, March 7; 9:00 a.m. to 5:30 p.m; The Lalit New Delhi Hotel

The Synopsys University Symposiums are for members of the academic community to get the latest information on design automation solutions, methodologies and standards. These FREE technical seminars are a resource to help accelerate innovation. Join us at this symposium to learn how you can achieve the highest value and productivity from your Synopsys tool investment.

Device Modeling

With growing device and design complexity, device-circuit co-design is becoming an increasingly important area of research. Today, devices and circuits are designed and optimized together for superior performance, yield and reliability. Synopsys TCAD tools are indispensable for device design and optimization.

[Agenda on-line]

postdoc position in Spain related to semiconductor device modeling

As Professor in the Universitat Rovira i Virgili (Tarragona, Catalonia, , Spain), I am going to apply for a postdoctoral position (funded by the Spanish Ministry) related to modeling (in particular compact modeling) and/or parameter extraction of emerging devices we are targeting, such as Multi-Gate MOSFETs, junctionless nanowires, III-V MOSFETs, GaN HEMTs, Tunnel FETs, and also organic and metal oxide TFTs.

The candidate should be a person who holds a PhD as awarded after September 1 2009, or who is committed to defend his Ph D thesis in the coming months (before the start of the contract).

Contracts are expected to start after September 2014.
The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile.

The work may continue the work we did in the framework of some EU-funded projects, such as COMON (about Multi-Gate MOSFETs, GaN HEMTs, and High Voltage MOSFETs), SQWIRE (junctionless Si nanowires) and FlexNET (organic TFTs) . Our contribution in these projects was the physics and modeling (in particular compact modeling) of the novel devices addressed by these European projects.

The postdoc position, which will be a contract, will have a duration of up to 2 years. The net salary will be around 1900 Euro/months.

Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: February 24 2014

MY E-MAIL ADDRESS IS: benjamin.iniguez@urv.cat

Address:
Benjamin Iñiguez
Nanoelectronics and Photonics Systrems Group (NEPHOS)
Department of Electronic Engineering
Universitat Rovira i Virgili (URV)
Avinguda dels Paisos Catalans 26
43007 Tarragona, Catalonia
SPAIN.

Standards For FinFETs

   http://electronicdesign.com/eda/synopsys-rich-goldman-explains-effects-standards-2014s-semiconductor-trends 

Rich Goldman, VP of corporate marketing and strategic alliances at Synopsys, recently predicted the top five trends that are likely to drive the global semiconductor industry in 2014. Standards will help, or hurt, each of these trends.

The ever-changing semiconductor industry has experienced and will continue to experience megatrends like no other industry. Recently, Rich Goldman, vice president of corporate marketing and strategic alliances at Synopsys, made his predictions about the top five trends that are likely to drive the global semiconductor industry in 2014. Each of these trends can be helped, or hurt, by the domain of standards.

Standards For FinFETs

Karen: You predict that FinFETs will be one of the top five trends in 2014. FinFETs promise lower power consumption and higher performance. Designing and manufacturing FinFETs involve a slew of challenges. How can standards help overcome some of them?

Rich: EDA tools and models are advancing to handle the unique properties and behaviors of FinFETs. For each step in the design cycle, data is transferred from one tool to another. Enabling interoperability and modeling are obvious roles for standards to play and there are already several standards in use today. For example, the Liberty library modeling standard is used to develop FinFET libraries that feed logic synthesis and other advanced tools. Standards for describing low-power design intent are also important. Because low power consumption is a key feature of FinFETs, designers can benefit from using these during the power planning stage. The Unified Power Format (UPF) (IEEE Std. 1801) is effective in capturing the low-power design intent and directing the EDA tools to implement it. The biggest advancements in standards for FinFETs are in the Interconnect Technology Format (ITF) standardized by the IEEE-ISTO and in the new BSIM-CMG (CMOS Multi-Gate) SPICE model.

Karen: Are these standards sufficient for FinFETs today?

Rich: Standards for advanced semiconductor design, including FinFETs, should always evolve. While the standards may suffice for a given technology or geometry node, design and EDA engineers are constantly inventing more effective ways of overcoming challenges. As these engineers learn new techniques, the standards for interoperability and modeling need to be enhanced. It’s a cyclical situation. The standards enable new designs that can render the standards obsolete unless the standards are updated to include new methods and technology. Thus, standards working groups, comprised of tech-savvy engineers and experts in standards development, are part of the overall success of new technologies such as FinFETs.

[continue reading...]

New i-MOS Release

http://i-mos.org/
A new release of the interactive Modeling and On-line Simulation Platform (i-MOS), version 201401 is available online. In this release, the i-MOS team launched several new services, as well as improved some modules in previous versions. A list of these new features follows:

• Evaluative support for BSIM3 with newly designed interfaces;
• A collection of model parameter cards for your applications;
• A newly implemented double-gate/FinFET model SDDGM; 
• Parameter searching function for all the device models;
• Integrated text editor for composing netlists in circuit simulations;
• Easier entry for your posting of news and events, etc.

For more details and an updated user manual, please see http://i-mos.org

Other related compact/SPICE modeling events and news are listed at:
http://i-mos.org/imos/resources

[Call for Papers] SISPAD2014

https://sites.google.com/site/sispad2014/

This is a call for papers for the 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD2014), to be held September 9-11, 2014, in Yokohama, Japan. This conference provides an opportunity for the presentation and discussion of the latest advances in modeling and simulation of semiconductor devices, processes, and equipment for integrated circuits.

Abstract submission deadline is March 31, 2014.

Workshops:
Two companion workshops will run concurrently prior to the start of the conference on Monday 8th September 2014:

• Workshop 1: Compact Modeling -Enabling Better Insight of Device Features-
  Organizer: Mitiko Miura-Mattausch (Hiroshima University)
• Workshop 2: Carrier Transport in Nano-MOS Transistors: Theory and Experiments(tentative)
  Organizer: Hideaki Tsuchiya (Kobe University) and Yoshinari Kamakura (Osaka University)

Plenary Speakers:

• Augusto Benvenuti (Micron Technology)
  Current status and future prospects of non-volatile memory modeling
• Massimo V. Fischetti (University of Texas at Dallas)
  Physics of electronic transport in low-dimensionality materials forfuture FETs
• Kimimori Hamada (Toyota Motor Corporation)
  TCAD challenge on development of power semiconductor devices for automotive applications

Invited Speakers:

• Mario Ancona (Naval Research Laboratory)
  Nonlinear thermoelectroelastic simulation of III-N devices
• Asen Asenov (University of Glasgow)
  Progress in the simulation of time dependent statistical variability in nano CMOS transistors
• Jean-Pierre Colinge (Taiwan Semiconductor Manufacturing Company)
  Nanowire transistors: pushing Moore's law to the limit
• Tibor Grasser (Vienna University of Technology)
  Advanced modeling of charge trapping: RTN, 1/f noise, SILC, and BTI
• Kohji Mitsubayashi (Tokyo Medical and Dental University)
  Novel biosensing devices for medical applications
• Christian Sandow (Infineon Technologies)
  Exploring the limits of the safe operation area of power semiconductor devices
• Mark Stettler (Intel Corporation)
  Device and process modeling: 20 years at Intel's other fab