Friday, March 7, 2014

SISPAD2014: 2nd Call for Papers

Second Call for Papers
September 9 – 11, 2014
Workshop, September 8, 2014
Mielparque Yokohama, Yokohama, JAPAN
Co-sponsored by Japan Society of Applied Physics Technical 
Co-sponsored by IEEE Electron Devices Society

This conference provides an opportunity for the presentation and discussion of the latest advances in modeling and simulation of semiconductor devices, processes, and equipment for integrated circuits.

  • Modeling and simulation of all sorts of semiconductor devices, including FinFETs, ultra-thin SOI devices, emerging memory devices, optoelectronic devices, TFTs, sensors, power electronic device, widegap semiconductor devices, spintronic devices, tunnel FETs, SETs, carbon-based nanodevices, organic electronic devices, and bioelectronic devices
  • Modeling and simulation of all sorts of semiconductor processes, including first-principles material design and growth simulation of nano-scale fabrication
  • Fundamental aspects of device modeling and simulation, including quantum transport, thermal transport, fluctuation, noise, and reliability
  • Compact modeling for circuit simulation, including low-power, high frequency, and power electronics applications
  • Process/device/circuit co-simulation in context with system design and verification
  • Equipment, topography, lithography modeling
  • Interconnect modeling, including noise and parasitic effects
  • Numerical methods and algorithms, including grid generation, user-interface, and visualization
  • Metrology for the modeling of semiconductor devices and processes
Plenary Speakers:
  • Augusto Benvenuti, Micron Technology,
    “Current status and future prospects of non-volatile memory modeling”
  • Massimo V. Fischetti, University of Texas at Dallas,
    “Physics of electronic transport in low-dimensionality materials for future FETs”
  • Kimimori Hamada, Toyota Motor Corporation,
    “TCAD challenge on development of power semiconductor devices for automotive applications”
Invited Speakers:
  • Mario Ancona, Naval Research Laboratory,
    “Nonlinear thermoelectroelastic simulation of III-N devices”
  • Asen Asenov, University of Glasgow,
    “Progress in the simulation of time dependent statistical variability in nano CMOS transistors”
  • Jean-Pierre Colinge, Taiwan Semiconductor Manufacturing Company,
    “Nanowire transistors: pushing Moore's law to the limit”
  • Tibor Grasser, Vienna University of Technology,
    “Advanced modeling of charge trapping: RTN, 1/f noise, SILC, and BTI”
  • Kohji Mitsubayashi, Tokyo Medical and Dental University,
    “Novel biosensing devices for medical applications”
  • Christian Sandow, Infineon Technologies,
    “Exploring the limits of the safe operation area of power semiconductor devices”
  • Mark Stettler, Intel Corporation,
    “Device and process modeling: 20 years at Intel's other fab”
Two companion workshops will run concurrently prior to the start of the conference on Monday September 8, 2014:
  • Compact Modeling "Enabling Better Insight of Device Features"
    Organizer: Mitiko Miura-Mattausch (Hiroshima University)
  • Carrier Transport in Nano-Transistors: Theory and Experiments
    Organizer: Hideaki Tsuchiya (Kobe University) and Yoshinari Kamakura (Osaka University)
Abstract Submission: 
Authors are invited to submit a two-page abstract (A4 or 22×28cm) including figures. Full submission information is available at the ing web page: <>. Authors of accepted papers will be notified by May 15, 2014. Camera-ready copy of a four-page manuscript will be required from the authors for inclusion in the Conference Proceedings by June 30, 2014.

Deadline for submission of abstract: March 31, 2014

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