[paper] NCFET CMOS Logic

Reinaldo Vega, Senior Member, IEEE, Takashi Ando*, Senior Member, IEEE,  

Timothy Philip, Member, IEEE

Junction Design and Complementary Capacitance Matching 

for NCFET CMOS Logic 

IEEE J-EDS 2021

DOI 10.1109/JEDS.2021.3095923

IBM Research, Albany, NY 12203

* IBM T.J. Watson Research Center, Yorktown Heights, NY 10598

Abstract: Negative capacitance field effect transistors (NCFETs) are modeled in this study, with an emphasis on junction design, implications of complementary logic, and device Vt menu enablement. Contrary to conventional MOSFET design, increased junction overlap is beneficial to NCFETs, provided the remnant polarization (Pr) is high enough. Combining broad junctions with complementary capacitance matching (CCM) in MFMIS (metal/ ferroelectric/ metal/ insulator/ semiconductor) NCFETs, it is shown that super-steep and non-hysteretic switching are not mutually exclusive, and that it is theoretically possible to achieve non-hysteretic sub-5 mV/dec SS over > 6 decades. In a CMOS circuit, due to CCM, low-Vt pairs provide steeper subthreshold swing (SS) than high-Vt pairs. Transient power/performance is also modeled, and it is shown that a DC optimal NCFET design, employing broad junctions, CCM, and a low-Vt NFET/PFET pair, does not translate to improved AC power/performance in unloaded circuits compared to a conventional FET reference. It is also shown that the same non-hysteretic DC design point is hysteretic in AC and may also lead to full polarization switching at higher voltages. Thus, a usable voltage window for AC NCFET operation forces a retreat from the DC-optimal design point.

Fig: Equivalent capacitance network and illustrative C-V curve showing NMOS and NC curves. CNC > CINV results in non-hysteretic switching, but low voltage gain in the off-state due to CNC >> COV. Setting CNC to CNC2, which is matched more closely to COV, results in very low SS, but also hysteretic switching as CNC2 < CINV. 

Acknowledgment: The authors would like to thank Paul Solomon and Prof. Sayeef Salahuddin for insightful discussions, as well as Synopsys for technical support.

[Final Program] 18th MOS-AK ESSDERC/ESSCIRC Workshop Grenoble; Sept. 6, 2021

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

18th MOS-AK ESSDERC/ESSCIRC Workshop

Grenoble, Sept. 6, 2021

Together with local Host and MOS-AK Organizers as well as all the Extended MOS-AK TPC Committee, we invite you to the consecutive 18th MOS-AK ESSDERC/ESSCIRC Workshop. Scheduled Virtual/Online MOS-AK event aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors.

The MOS-AK Workshop Program is available online: 

https://www.mos-ak.org/grenoble_2021/

Venue: Online MOS-AK Webinar;

use the online form/link below to register.

Online Registration is open

any related enquiries can be sent to registration@mos-ak.org

Post-workshop publications, selected, the best papers will be recommended for further publication in the special compact/SPICE modeling issue of the Solid State Electronics.

-- W.Grabinski; MOS-AK (EU)

---

Enabling Compact Modeling R&D Exchange

www.mos-ak.org

---

WG210721

[paper] Compact Analytical Modeling of FD Dual Material DG MOSFET

Shahana Akter1, Md. Mirazur Rahman1 and Md. Arif Abdulla Samy2

Compact Analytical Modeling of Surface Potential 

of a fully depleted Dual Material Double Gate MOSFET

Materials Mechatronics and Systems Engineering 2021, 1, 1. https://citescript.com/Journals/index.php/mmsj/

1 Department of EEE, Primeasia University
2 ATLAS Experiment, CERN

Abstract: Scaling transistors to gain speed while reducing capacitance and cost, is a key topic of today’s semiconductor industry, which is widely affected by Short-Channel Effects, the phenomenon that reduces efficiency. To dominate that unwanted effect, a 2-dimensional electrostatic potential modeling of the fully depleted channel, with high-k based dual material double gate (DMDG) MOSFET, has been developed in this paper. The expression for the electrostatic potential of DMDG has beendeveloped using 2-D Poisson’s equation with appropriate device boundary conditions. The device performance has been analyzed with the variation in device parameters, such as channel length, channel thickness, oxide thickness, and other key parameters. For authenticating, results have also been compared with state-of-the-art published results. This research was successful to exhibit that the proposed model could overcome Drain-induced Barrier Lowering, enhancing mobility carrier resulting to optimize short channel effect, which can bring a revolutionary change in transistor industry as well as in low power VLSI applications.

Fig: Device structure for the 2D double gate MOSFET

Acknowledgment: Authors would like to thank Professor Dr. Quazi Deen Mohd Khosru for his guidance in every step of this research. Without his valuable and persistent help, it would not be possible to conclude this project. The project has no external funding.

[paper] 11.8 GHz Fin Resonant Body Transistor

Analysis and Modeling of an 11.8 GHz Fin Resonant Body Transistor 

in a 14nm FinFET CMOS Process 

Udit Rawat, Student Member, IEEE, Bichoy Bahr*, Member, IEEE, 

and Dana Weinstein, Senior Member, IEEE

arXiv:2107.04502v1 [physics.app-ph] 9 Jul 2021

 

Department of Electrical Engineering, Purdue University, West Lafayette USA

*Kilby Labs - Texas Instruments, Dallas, TX, USA.

Abstract: In this work, a compact model is presented for a 14 nm CMOS-based FinFET Resonant Body Transistor (fRBT) operating at a frequency of 11.8 GHz and targeting RF frequency generation/filtering for next generation radio communication, clocking, and sensing applications. Analysis of the phononic dispersion characteristics of the device, which informs the model development, shows the presence of polarization exchange due to the periodic nature of the back-end-of-line (BEOL) metal PnC. An eigenfrequency-based extraction process, applicable to resonators based on electrostatic force transduction, has been used to model the resonance cavity. Augmented forms of the BSIM-CMG (Common Multi-Gate) model for FinFETs are used to model the drive and sense transistors in the fRBT. This model framework allows easy integration with the foundry-supplied process design kits (PDKs) and circuit simulators while being flexible towards change in transduction mechanisms and device architecture. Ultimately, the behaviour is validated against RF measured data for the fabricated fRBT device under different operating conditions, leading to the demonstration of the first complete model for this class of resonant device integrated seamlessly in the CMOS stack.

Fig: Complete 3D FEM Simulation model depicting two adjoining fRBT unit cells. Mx (x=1-3) and Cy (y=4-6) represent the first 6 metal levels that form a part of the BEOL PnC.

Acknowledgement: This work was supported in part by the DARPA MIDAS Program.

 

#MEMS becoming more #human

#MEMS becoming more #human https://t.co/aPG0GWl0Yq #semi https://t.co/kkUyTs4HN7

— Wladek Grabinski (@wladek60) Jul 21, 2021

---

from Twitter https://twitter.com/wladek60

July 21, 2021 at 10:22AM
via IFTTT

VSD Free Webinar - Mixed-signal RISC-V based SoC on FPGA - 23rd July, 7pm IST

 

This 60-min webinar helps you get started with a basic mixed-signal FPGA flow, which can be extended to any complex SoC.VSD and RedwoodEDA conducts 5-day RISC-V based MYTH (Microprocessors for You in Thirty Hours) workshop using transaction level Verilog on Makerchip platform. For people who have done this workshop can use this webinar as an extension to the 5th Day, where RISC-V pipe-lined CPU coded in TL-Verilog is now converted to Verilog language and is a part of a mixed-signal SoC

If you are from ASIC/Physical design back-ground, this webinar will complement your existing work, and you would really get to know similarities and differences between ASIC and FPGA flow, which one is preferred under what conditions and why is it preferred

This single webinar connects VLSI students, analog designers, FPGA designers and ASIC designers. It is also an attempt to bring everyone on the same platform, and serves as a starting point for design verification

Stay tuned for follow-up series of FPGA webinars and 5-day hands-on high intensity FPGA workshop, which will be built around OpenFPGA framework and Makerchip visualization software, that enables the whole community to learn FPGA fundamentals along with labs, without actually having a physical FPGA board.

Agenda:

1. "FPGA on eSim"
   Guest Speaker - Prof. Kannan M Moudgalya, IIT Bombay
2. "chipIgnite Program"
   Guest Speaker - Mike Wishart, CEO eFabless
3. "Tapeout World Program"
   Guest Speaker - Naveed Sherwani, Chairman, OSFPGA
4. "Mixed-signal RISC-V based SoC on FPGA"
   Webinar Instructor - Shivani Shah

Webinar Curriculum:
1) Introduction
2) RVMYTH RISC-V Core
3) Why FPGAs ?
4) TL - Verilog to RTL verilog using Makerchip
5) Functional Simulation using iverilog
6) FPGA - Steps to create project
7) FPGA - Steps to generate IPs
8) FPGA - RTL simulation
9) FPGA - Synthesis
10) FPGA - Implementation and timing analysis
11) FPGA - Bit-stream generation, FPGA programming and ILA
12) Conclusion

Register here (if you don't see the form, please refresh page):
https://lnkd.in/gByg6fZ

[Announcement] ToM 2021/2 online on September 21st-23rd

ToM2021/2 course will be held online on September 21st-23rd, 2021 with the following program:

September 21 2021
    14:00 – 17:30 Jussi Jansson (Oulu University, Finland) - "Time-to-digital converters and related applications"
September 22 2021
    09:00 – 12:30 Luca Scandola (Infineon Technologies, Italy), "Introduction to DC-DC conversion suitable for automotive application: from the theory to the modelization with practical examples"
    14:00 – 17:30 Benoit Bakeroot (Ghent University, Belgium), "GaN semiconductor devices for power electronics: overview, status and future perspectives"
September 23 2021
    09.00 – 12:30 Qiang Li (UETSC, China), "Subthreshold and near-threshold ADC techniques"
    14:00 – 17:30 Andrea Mazzanti (University of Pavia, Italy) and Enrico Monaco (Inphi, Italy), "Introduction and advances in serial links"

=============================================

Registration is mandatory to attend the course:
http://www.innotechevents.com/index.php?page=ToM/RegistrationForm.html

Registered participants will receive:
- on-line attendance to all lectures
- pdf material for all lectures
- certificate of participation
- final exam with certificate (if needed)

We look forward to virtually meeting you !!!!

More information at:
http://www.innotechevents.com/index.php?page=ToM/ToM.html

Best regards
Andrea Baschirotto