[linux] Conferences and Events

Python Web Conf

- March 22 - 26, 2021

The 3rd annual Python Web Conf is a virtual event designed to promote best practices for hard web production problems. It features international experts presenting on 48 topics such as Django, Flask, Pyramid, Tornado, Plone, CI/CD, Containers, Serverless, REST APIs, web security, microservices, websockets, etc.

DrupalCon

- April 12 - 16, 2021

The open source digital experience conference for Drupal.

Black Hat Asia 2021 -

May 4-7, 2021

During this week, information security experts will teach interactive, online Trainings, innovative research will be presented at Briefings, the latest open-source tools will be showcased at Arsenal, and the Business Hall will feature top-tier security solutions and service providers, plus ample networking events and opportunities.

#SIA has sent a letter to President Biden

#SIA has sent a letter to President Biden urging him to include in his recovery and infrastructure plan substantial funding for incentives for #semi manufacturing https://t.co/Jwgxro85Qu pic.twitter.com/lgMZbTczbN

— Wladek Grabinski (@wladek60) February 17, 2021

---

from Twitter https://twitter.com/wladek60

February 17, 2021 at 03:39PM
via IFTTT

Top #banks join #Linux and #opensource patent #protection group https://t.co/5d9B4a3ysh #semi https://t.co/XKGg4ioc9p

Top #banks join #Linux and #opensource patent #protection group https://t.co/5d9B4a3ysh #semi pic.twitter.com/XKGg4ioc9p

— Wladek Grabinski (@wladek60) February 17, 2021

---

from Twitter https://twitter.com/wladek60

February 17, 2021 at 03:21PM
via IFTTT

[Semiconductor Engineering by B.Moyer] #3D #FTJ stack for use in in-memory computing [Source: #IEDM/#Kioxia] https://t.co/oeNFCdXZTj #semi https://t.co/koAXAIKK03

[Semiconductor Engineering by B.Moyer] #3D #FTJ stack for use in in-memory computing [Source: #IEDM/#Kioxia] https://t.co/oeNFCdXZTj #semi pic.twitter.com/koAXAIKK03

— Wladek Grabinski (@wladek60) February 17, 2021

---

from Twitter https://twitter.com/wladek60

February 17, 2021 at 09:22AM
via IFTTT

[s3.i-micronews] NVIDIA Tesla P100 GPU with HBM2 2.5D & 3D Packaging https://t.co/1vs2c4qtvA #semi https://t.co/Z7vaqr8GGr

[s3.i-micronews] NVIDIA Tesla P100 GPU with HBM2
2.5D & 3D Packaging https://t.co/1vs2c4qtvA #semi pic.twitter.com/Z7vaqr8GGr

— Wladek Grabinski (@wladek60) February 17, 2021

---

from Twitter https://twitter.com/wladek60

February 17, 2021 at 09:14AM
via IFTTT

[papers] Compact/SPICE Modeling

[1] Peled, A, Amrani, O, Rosenwaks, Y.; DC and transient models of the MSET device; Int J Numer Model. 2021;e2869. https://doi.org/10.1002/jnm.2869

Abstract: As a multigate device, the multiple‐state electrostatically formed nanowire transistor (MSET) exhibits a rather complex characteristic on account of the coupling between each of its two adjacent terminals. The MSET has shown promise across a steadily growing range of applications and integrated circuit components. However, an analytical model of the MSET has not been formulated. The objective of this work was to develop practical DC and transient models of the MSET. The modeling approach comprises two stages: the first stage consists of a bottom‐up derivation of the I–V characteristics from the fundamental physical level using the physical processes within the device to derive equations that describe its steady‐state behavior; the second stage proposes a set of analytical equations more applicable to simulation environments. A transient model that considers device parasitic capacitance is also established. The models are validated against robust model simulations in TCAD Sentaurus and Cadence Virtuoso.

[2] Ciou, Jhang-Yan, Sourav De, Wallace Lin, Yao-Jen Lee, and Darsen Lu. "Analytical Modelling of Ferroelectricity Instigated Enhanced Electrostatic Control in Short-Channel FinFETs." arXiv e-prints (2020): arXiv-2007.

Abstract: This study simulated negative-capacitance double gate FinFETs with channel lengths ranging from 25nm to 100nm using TCAD. The results show that negative capacitance significantly reduces subthreshold swing as well as drain induced barrier lowering effects. The improvement is found to be significantly more prominent for short channel devices than long ones, which demonstrates the tremendous advantage of negative capacitance gate stack for scaled MOSFETs. A compact analytical formulation is developed to quantify sub-threshold swing improvement for short channel devices.

Fig: (a) Three-dimensional NC FinFET structure studied insimulation. (b) List of nominal device parameters used in TCAD simulation.

[3] Ahmed, Sheikh Z., Samiran Ganguly, Yuan Yuan, Jiyuan Zheng, Yaohua Tan, Joe C. Campbell, and Avik W. Ghosh. "A Physics Based Multiscale Compact Model of pin Avalanche Photodiodes." arXiv preprint arXiv:2102.04647 (2021).

Abstract: III-V material based digital alloy Avalanche Photodiodes (APDs) have recently been found to exhibit low noise similar to Silicon APDs. The III-V materials can be chosen to operate at any wavelength in the infrared spectrum. In this work, we present a physics-based SPICE compatible compact model for APDs built from parameters extracted from an Environment-Dependent Tight Binding (EDTB) model calibrated to ab-initio Density Functional Theory (DFT) and Monte Carlo (MC) methods. Using this approach, we can accurately capture the physical characteristics of these APDs in integrated photonics circuit simulations.

Fig: Schematic diagram of avalanche photodiode model and testbench used in the SPICE simulations.

#Fab For Europe

#Fab For Europe - The #EU’s iffy decision-making has been nowhere more apparent than in its dealings with the #semi industry. https://t.co/lH87b7UnUO pic.twitter.com/OkrGE907K6

— Wladek Grabinski (@wladek60) February 16, 2021

---

from Twitter https://twitter.com/wladek60

February 17, 2021 at 12:32AM
via IFTTT

[EETimes] #ISSCC Plenary: A Bright #Foundry Future, according to #TSMC chairman Mark Liu https://t.co/NaPLNoyLhH #semi #3nm https://t.co/YPQgs1YLDp

[EETimes] #ISSCC Plenary: A Bright #Foundry Future, according to #TSMC chairman Mark Liu https://t.co/NaPLNoyLhH #semi #3nm pic.twitter.com/YPQgs1YLDp

— Wladek Grabinski (@wladek60) February 16, 2021

---

from Twitter https://twitter.com/wladek60

February 16, 2021 at 11:14AM
via IFTTT

First #opensource smartphone #ophthalmoscope: oDocs sets world record https://t.co/qcGFsogcyc #semi https://t.co/E8sj2P4req

First #opensource smartphone #ophthalmoscope: oDocs sets world record https://t.co/qcGFsogcyc #semi pic.twitter.com/E8sj2P4req

— Wladek Grabinski (@wladek60) February 15, 2021

---

from Twitter https://twitter.com/wladek60

February 15, 2021 at 09:44AM
via IFTTT

[book] Moore's Law: The Untold Story

Daniel Foty 

Moore's Law: The Untold Story 

CreateSpace Independent Publishing Platform 

August 18, 2017; pp. 400; ISBN: 978-1974698431 

 

“Moore's Law' has entered popular parlance in a variety of ways. But what exactly is "Moore‘s Law?" And how did it happen?

In this book. Daniel Foty - a PhD. engineer and commercial-grade veteran of more than twenty-f‌ive years in the semiconductor industry and allied f‌ields - takes the reader through the tangled and bizarre sequence of events that eventually led to ‘Moore’s Law” and the ubiquitous silicon technology which has resulted. The deep roots of this remarkable story go back some twenty centuries, and that story involves an unlikely collection of happenstances. Gifts of nature, and totally unexpected developments. Along the way, the reader meets many of the players in that story - from the well-known (such as Benjamin Franklin and Gordon Moore) to the (unfortunately) less—well-known (such as Jack Kilby and Robert Noyce). In the f‌inal analysis, “Moore's Law" was neither imposed nor discovered - but instead represents a remarkable concatenation of a series of natural flukes that compounded into a juggernaut. 

Written for the non-specialist, the untold story of “Moore's Law" is told here with fresh depth and proper historical insight.

[paper] ACM) Model in VHDL-AMS

A. S. Kumar, Ch. Rekha, Y. D. S. Raju 

Behavioral Modeling of the Advanced Compact MOSFET (ACM) Model with VHDL-AMS 

OAIJSE, Vol. 6, Issue 1, January 2021 

ISSN (Online) 2456-3293 

*Holymary Institute Of Technology And Science, Bogaram(V), Keesara (M), Hyderabad

Abstract: This paper reports a VHDL-AMS implementation of the Advanced Compact MOSFET (ACM) model. This behavioral model aims at being a reference model for ACM code developers, helping to implement and maintain simulators specic code. Simulation results from classical testbenches are presented and con_rm the correctness of the proposed model.

Fig: The used methodology propose this testbench [ref]

[ref] A. L. T. B. da Fonseca and F. R. de Sousa, "Behavioral modeling of the Advanced Compact MOSFET (ACM) model with VHDL-AMS," 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference, Montreal, QC, 2008, pp. 169-172

doi: 10.1109/NEWCAS.2008.4606348.

Abstract: This paper reports a VHDL-AMS implementation of the Advanced Compact MOSFET (ACM) model. This behavioral model aims at being a reference model for ACM code developers, helping to implement and maintain simulators specific code. Simulation results from classical testbenches are presented and confirm the correctness of the proposed model.

[symposium] ISDCS 2021 Hiroshima University

ISDCS 2021

3-5, March 2021

Hiroshima University, Higashi-Hiroshima, Japan

The ISDCS is a premium international forum for scholars, scientists, educators, students and engineers to exchange their latest findings and technological advances in the field of devices, circuits and systems.

Keynote Speakers

• Prof. Parthasarathi Chakrabarti, Director, IIEST Shibpur and Department of Electronics Engineering, IIT(BHU), India
  "Advanced Materials and Methods for Fabrication of Thin-film Transistor (TFT)-based Sensors"
• Prof. Shinji Kaneko, Hiroshima University, Japan
  "SDGs Initiatives at Hiroshima University: Integrating Global Strategy and Regional Vitalization"

Invited Speakers

• Prof. Sanatan Chattopadhyay, University of Calcutta, India
  "Voltage Assisted Quantum Dot Based MOS Devices for Electronic and Optoelectronic Applications"
• Prof. Partha Bhattacharya, IIEST Shibpur, India
  "Performance Improvement of Graphene Derivative based Gas sensors: Role of Functional Group Tuning and Ternary Junction Formation"
• Prof. Hafizur Rahaman, IIEST Shibpur, India
  "Tunnel Field Effect Transistors: Challenges and Opportunities"
• Prof. Nillohit Mukherjee, IIEST Shibpur, India
  "Metal Oxide Semiconductors with Carbon Nanomaterials for Efficient Supercapacitive Type Energy Storage Devices"
• Prof. Shigeyasu Uno, Ritsumeikan University, Japan
  "Electrochemical Impedance Sensor for Non-invasive Living Cell Monitoring toward CMOS Cell Culture Monitoring Platform"
• Mr. Shigeru Shiratake, Corporate Vice President, DRAM, Emerging Memory Process Integration and Device Technology Micron Technology, Inc., USA
  "Challenges for DRAM scaling and performance enhancement"
• Prof. Rihito Kuroda, Tohoku University, Japan
  TBD

Previous Conference:

• ISDCS 2020, Kolkata, India
• ISDCS 2019, Higashi-hiroshima, Japan
• ISDCS 2018, Kolkata, India

[PhD Thesis] Chiara ROSSI; A novel approach for SPICE modeling of light and radiation effects in ICs; Présentée le 29 janvier 2021 à EPFL Lausanne pour l’obtention du grade de Docteur ès Sciences; DOI:10.5075/epfl-thesis-8422 https://t.co/nKSO7dyI1I #semi https://t.co/ruaQTavMH1

[PhD Thesis] Chiara ROSSI; A novel approach for SPICE modeling of light and radiation effects in ICs; Présentée le 29 janvier 2021 à EPFL Lausanne pour l’obtention du grade de Docteur ès Sciences; DOI:10.5075/epfl-thesis-8422https://t.co/nKSO7dyI1I #semi pic.twitter.com/ruaQTavMH1

— Wladek Grabinski (@wladek60) February 11, 2021

---

from Twitter https://twitter.com/wladek60

February 11, 2021 at 03:56PM
via IFTTT

[thesis] SPICE modeling of light and radiation effects in ICs

A novel approach for SPICE modeling of light and radiation effects in ICs

Chiara ROSSI

Présentée le 29 janvier 2021

à la Faculté des sciences et techniques de l’ingénieur Groupe de scientifiques IEL

Programme doctoral en microsystèmes et microélectronique

pour l’obtention du grade de Docteur ès Sciences

DOI:10.5075/epfl-thesis-8422

Modeling the interaction of ionizing radiation, either light or ions, in integrated circuits is essential for the development and optimization of optoelectronic devices and of radiation-tolerant circuits. Whereas for optical sensors photogenerated carriers play an essential role, high energy ionizing particles can be a severe issue for circuits, as they create high density of excess carriers in ICs substrate, causing parasitic signals. In particular, recent advances in CMOS scaling have made circuits more sensitive to errors and dysfunctions caused by radiation-induced currents, even at the ground level. TCAD simulations of excess carriers generated by light or radiation are not dedicated to large scale circuit simulations since only few devices can be simulated at a time and computation times are too long. Conversely, SPICE simulations are faster, but their accuracy is strictly dependent on the correctness of the compact models used to describe the devices, especially when dealing with photocurrents and parasitic radiation-induced currents.

The objective of this thesis is to develop a novel modeling approach for SPICE compatible simulations of electron-hole pairs generated by light and by high energy particles. The approach proposed in this work is based on the Generalized Lumped Devices, previously developed to simulate parasitic signals in High Voltage MOSFET ICs. Here, the model is extended to include excess carriers generation. The developed approach allows physics-based simulations of semiconductor structures, hit by light or radiation, that can be run in standard circuit simulators without the need for any empirical parameter, only relying on the technological and geometrical parameters of the structure, and without any predefined compact model. The model is based on a coarse mesh of the device to obtain an equivalent network of Generalized Lumped Devices. The latter predicts generation of excess carriers and their propagation, recombination and collection at circuit nodes through the definition of equivalent voltages, proportional to the excess carrier concentrations, and equivalent currents, proportional to the excess carrier gradients. The model is validated with commercial TCAD numerical simulations for different scenarios. Regarding light effects, the proposed strategy is applied to simulate various optoelectronic devices. Complete DC I-V characteristics of a solar cell and transient response of a photodiode are studied. Next, phototransistors are considered. After, a full pixel of a 3T-APS CMOS image sensor is analyzed. The photosensing device, described with Generalized Devices, is co-simulated with the in-pixel circuit, described with compact models. The impact of semiconductor parameters on pixel output and on crosstalk between adjacent pixels is predicted. Finally, radiation-induced soft errors in ICs are examined. Alpha particles at different energies hitting the substrate are simulated. Parasitic currents collected at contacts are studied as a function of particles position and energy. Funneling effect, which is a phenomenon specific to high injection, is also included in the model.

This work shows that the Generalized Lumped Devices approach can be successfully used for SPICE simulations of optoelectronic devices and for prediction of radiationinduced parasitic currents in ICs substrate. This thesis is a first step towards a complete and flexible tool for excess carriers modeling in standard circuit simulators.

Fig: Layout, mesh (gray dashed lines) and equivalent network of Generalized Lumped Devices (Generalized Homojunctions, Resistors and Diodes). The structure is uniformly illuminated from the left side, justifying a 1D discretization scheme.

[papers] Compact/SPICE Modeling

[1] Kotecha, Ramachandra M., Md Maksudul Hossain, Arman Rashid, Asif Emon, Yuzhi Zhang, and Homer Ei C. Alan Mantooth. "Compact Modeling of High-Voltage Gallium Nitride Power Semiconductor Devices for Advanced Power Electronics Design." IEEE Open Journal of Power Electronics (2021)

Fig: (a) Structure of field-plated GaN transistor (b) Equivalent sub-circuit topology

---

[2] Sengupta, Sarmista, and Soumya Pandit. "A Unified Model of Drain Current Local Variability due to Channel Length Fluctuation for an n-Channel EδDC MOS Transistor." (researchsquare.com 2021).

Fig: Schematic diagram of an Epitaxial δ doped n-channel MOS transistor used for design purpose and the graded retrograde approximation of the channel profile of EδDC transistor.

---

[3] Patil, C.V., Suma, M.S. Compact modeling of through silicon vias for thermal analysis in 3-D IC structures. Sādhanā 46, 35 (2021). https://doi.org/10.1007/s12046-020-01549-1

Fig: Through Silicon Via 2D representation and its equivalent subcircuit.

[TechCrunch] CHIPS Alliance hires new director to push #opensource #chips ecosystem into next gear https://t.co/hAWwzdXknn #semi https://t.co/xHgTbWv2kU

[TechCrunch] CHIPS Alliance <https://t.co/Dj8XJ6nQo2> hires new director to push #opensource #chips ecosystem into next gear https://t.co/hAWwzdXknn #semi pic.twitter.com/xHgTbWv2kU

— Wladek Grabinski (@wladek60) February 9, 2021

---

from Twitter https://twitter.com/wladek60

February 09, 2021 at 02:00PM
via IFTTT

[paper] On-Chip Coplanar Waveguides

José Valdés-Rayón, Roberto S. Murphy-Arteaga and Reydezel Torres-Torres; 

Determination of the Contribution of the Ground-Shield Losses 

to the Microwave Performance of On-Chip Coplanar Waveguides 

IEEE Transactions on MTT; Feb.3, 2021 

DOI: 10.1109/TMTT.2021.3053548 

* National Institute of Astrophysics, Optics and Electronics (INAOE), Department of Electronics, Tonantzintla, Puebla 72840, Mexico.

Abstract: In this article, we characterize and model two parasitic effects that become apparent in the performance of coplanar waveguide interconnects in CMOS. One is the transverse resistance introduced by a patterned ground shield in coplanar waveguide interconnects, which significantly contributes to the shunt losses. The other one is the parasitic coupling between the input and output ports through the ground shield. The latter effect is particularly accentuated in relatively short lines and complicates the determination of the propagation constant using line-line algorithms at several tens of gigahertz. We demonstrate that using the proposed methodology, excellent model-experiment correlation can be achieved in the modeling of these types of interconnects up to at least 60 GHz.

Funding: CONACyT-Mexico

#Fraunhofer Institutes kicks off #6G research project in #Germany https://t.co/djljw87w42 #semi https://t.co/noOrjd4Ikf

#Fraunhofer Institutes kicks off #6G research project in #Germany https://t.co/djljw87w42 #semi pic.twitter.com/noOrjd4Ikf

— Wladek Grabinski (@wladek60) February 8, 2021

---

from Twitter https://twitter.com/wladek60

February 08, 2021 at 11:34PM
via IFTTT

Researchers review advancements in the development of #stretchable #transistors https://t.co/kQmvJGyMy4 #semi https://t.co/7sVc9uHZCR

Researchers review advancements in the development of #stretchable #transistors https://t.co/kQmvJGyMy4 #semi pic.twitter.com/7sVc9uHZCR

— Wladek Grabinski (@wladek60) February 8, 2021

---

from Twitter https://twitter.com/wladek60

February 08, 2021 at 06:36PM
via IFTTT

[C4P] MIXDES 2021 Paper Submission Deadline: 15 March 2021

MIXDES 2021 regular paper submission deadline is upcoming . As current COVID pandemic situation is still uncertain, the conference will be organized in hybrid mode or fully online. To help you with preparation of excellent papers, we have decided to move the submission deadline to 15 March 2021. As in previous year we are going to give you an opportunity to publish extended versions of your conference papers in Energies Journal. The information about the postMIXDES publication will be provided soon at the conference site (www.mixdes.org).

Important dates:

Conference days: 24-26 June 2021

Paper submission deadline: 15 March 2021

Notification of acceptance: 26 April 2021

Final paper versions: 17 May 2021

Mariusz Orlikowski - MIXDES 2021 Conference Secretary

Thanks to @johndmcmaster, we're in business again for the CPS-A-01 (DL-0311) Ok hand #CPS1 #CPS2 https://t.co/JqPzNlOUBy #semi https://t.co/VUxxNz2vHS

Thanks to @johndmcmaster, we're in business again for the CPS-A-01 (DL-0311) Ok hand #CPS1 #CPS2 https://t.co/JqPzNlOUBy #semi pic.twitter.com/VUxxNz2vHS

— Wladek Grabinski (@wladek60) February 8, 2021

---

from Twitter https://twitter.com/wladek60

February 08, 2021 at 03:41PM
via IFTTT

#Metamaterials’ potential for transforming #electronics https://t.co/uHlxv7C5M4 #semi https://t.co/6Yc9TxD82f

#Metamaterials’ potential for transforming #electronics https://t.co/uHlxv7C5M4 #semi pic.twitter.com/6Yc9TxD82f

— Wladek Grabinski (@wladek60) February 8, 2021

---

from Twitter https://twitter.com/wladek60

February 08, 2021 at 03:18PM
via IFTTT

[IEEE Spectrum] New Type of #DRAM Could Accelerate #AI https://t.co/QWucai2xJX #semi https://t.co/KtNPpyw4Cj

[IEEE Spectrum] New Type of #DRAM Could Accelerate #AI https://t.co/QWucai2xJX #semi pic.twitter.com/KtNPpyw4Cj

— Wladek Grabinski (@wladek60) February 8, 2021

---

from Twitter https://twitter.com/wladek60

February 08, 2021 at 02:58PM
via IFTTT

[paper] Simulations of transient processes in the nc-MOS structures

D. Tanous, A. Mazurak and B. Majkusiak 

Simulations of transient processes and characteristics of the nc-MOS structures 

Microelectronic Engineering, 

Volume 178, 2017, pp/ 173-177, 

DOI: 10.1016/j.mee.2017.05.013 

Abstract: Experimentally measured capacitance-voltage and current-voltage characteristics of the metal-insulator-semiconductor structures with nanocrystals embedded in the insulator often exhibit formations which result from charging/discharging processes of the nanocrystals and are difficult to explain and predict intuitively. Time dependent simulations as presented in this paper can be helpful in their analysis. The paper presents a study of the impact of selected geometrical parameters on their characteristics with the bias voltage ramp rate as a parameter.

FIG: a.) nc-MIS Structure; b.) Bias voltage ramp stimulation; c.)  CV and IV Simulations results

[C4P] 32nd IEEE MIEL 2021

32nd IEEE International Conference on Microelectronics 

MIEL 2021 

from September 12th-14th, 2021 in Niš, Serbia  

Due to the unprecedented health, travel and social distance restrictions imposed in Serbia and all over the world as a result of the COVID-19 pandemic, all participants will be invited to join a virtual MIEL 2021.

Accepted papers will be published in the Proceedings of the MIEL 2021 Conference, and included in IEEE Xplore database, subject to regular registration of at least one of the authors before July 16th, 2021. We are pleased to invite you, as an expert in the field of microelectronics, to submit paper to MIEL 2021 Conference and to encourage colleagues to do it. The deadline for the submission of two page-extended summaries (including figures, tables, and references) is May 7th, 2021. Looking forward to receiving your abstract for MIEL 2021 Conference

MIEL 2021 Program Committee

• Vojkan Davidović
• Danijel Danković

[AppleInsider] Apple nears '#Apple #Car' deal with #Kia, first model might be fully autonomous enterprise vehicle https://t.co/BM73nxSbe4 #semi https://t.co/dJmNqir0iv

[AppleInsider] Apple nears '#Apple #Car' deal with #Kia, first model might be fully autonomous enterprise vehicle https://t.co/BM73nxSbe4 #semi pic.twitter.com/dJmNqir0iv

— Wladek Grabinski (@wladek60) February 7, 2021

---

from Twitter https://twitter.com/wladek60

February 07, 2021 at 11:14AM
via IFTTT

[Watchy by SQFMI] A fully open source & customizable E-Ink watch https://t.co/za6CFZIOr9 #semi https://t.co/VS1C92jwmV

[Watchy by SQFMI] A fully open source & customizable E-Ink watch https://t.co/za6CFZIOr9 #semi pic.twitter.com/VS1C92jwmV

— Wladek Grabinski (@wladek60) February 5, 2021

---

from Twitter https://twitter.com/wladek60

February 05, 2021 at 11:46AM
via IFTTT

#IBM turns to #opensource software to build #quantum ecosystem https://t.co/FtYZ8sAY7A #semi https://t.co/ge7VMhfwR2

#IBM turns to #opensource software to build #quantum ecosystem https://t.co/FtYZ8sAY7A #semi pic.twitter.com/ge7VMhfwR2

— Wladek Grabinski (@wladek60) February 5, 2021

---

from Twitter https://twitter.com/wladek60

February 05, 2021 at 09:25AM
via IFTTT

Virtual Si Museum /2105/ IBM components from 1948 to 1986

Let's visit a partner's museum to discover IBM components from 1948 to 1986. Recently, Ken Shirriff /semiwiki.org/ has received a vintage display box used by IBM to illustrate the progress of computer technology. This display case, created by IBM Germany1 in 1986 included technologies ranging from vacuum tubes and magnetic core memory to IBM’s latest (at the time) memory chips and processor modules. In his semiwiki.org blog post, he describes these items in detail and how they fit into IBM’s history [read mode...]

#European #2nm project includes no chip companies https://t.co/h6VGpQMRC6 #semi https://t.co/SfmbI52Yyn

#European #2nm project includes no chip companies https://t.co/h6VGpQMRC6 #semi pic.twitter.com/SfmbI52Yyn

— Wladek Grabinski (@wladek60) February 4, 2021

---

from Twitter https://twitter.com/wladek60

February 04, 2021 at 04:09PM
via IFTTT

[#imec hires] Senior Device Pathfinding Engineer https://t.co/xHDSxt57aA #semi #compact #SPICE https://t.co/tNzgG2UtEk

[#imec hires] Senior Device Pathfinding Engineer https://t.co/xHDSxt57aA #semi #compact #SPICE pic.twitter.com/tNzgG2UtEk

— Wladek Grabinski (@wladek60) February 4, 2021

---

from Twitter https://twitter.com/wladek60

February 04, 2021 at 02:00PM
via IFTTT

FOSSEE 3-Day workshop on eSim

eSim (previously known as Oscad / FreeEDA) is a free/libre and open source EDA tool for circuit design, simulation, analysis and PCB design. It is an integrated tool built using free/libre and open source software such as KiCad, Ngspice and GHDL. eSim is released under GPL.

These workshops are being conducted by the expert faculty members of Indian Institute of Technology, Bombay. For registration and more details, visit our webpage. Participation certificate will be awarded to all the people who attend this workshop.

Time	Session
11 Feb 2021 (Installation and Simulation):
10:00 AM - 10:30 AM	Introductory Talk by Prof. Kannan Moudgalya
10:30 AM - 10:45 AM	Explaining the Workshop Procedure
10:45 AM - 11:05 AM	Basics of circuit simulation by Prof. Mahesh Patil, IIT Bombay
11:05 AM - 12:00 Noon	Installation and system check for the installed software
12:00 Noon - 1:00 PM	Spoken Tutorial session: Schematic Creation and Simulation
Lunch Break
2:00 PM - 3:00 PM	Spoken Tutorial session: Simulating an Astable Multivibrator
3:00 PM - 4:00 PM	Practice problem on Circuit Simulation
4:00 PM - 4:15 PM	Overview of eSim - FOSSEE Team
4:15 PM - 4:45 PM	Demo on PSpice to KiCad Converter - Sumanto, FOSSEE Fellow 2020 and FOSSEE Team
4:45 PM - 5:00 PM	eSim on cloud - FOSSEE Team
5:00 PM - 5:30 PM	FOSSEE activities under eSim
Overnight	Complete the practice problems
12 Feb 2021 (PCB design and device modelling in eSim):
9:30 AM - 10:00 AM	Discussion of practice problems (Optional)
10:00 AM - 10:40 AM	Spoken Tutorial session: Mapping Components with Footprints
10:40 AM - 11:20 AM	Spoken Tutorial session: Setting Parameters for PCB designing
11:20 AM - 11:50 Noon	eSim software development: how it will benefit students, faculty and professionals? - FOSSEE Team
11:50 AM - 12:40 PM	Spoken Tutorial session: Laying Tracks on PCB
12:40 PM to 1:00 PM	Spoken Tutorial session: PCB Layout for Astable Multivibrator
Lunch Break
2:00 PM- 3:00 PM	Practice problem: PCB design for a small circuit - 1 hour
3:00 PM - 4:00 PM	Live session on Device modelling - FOSSEE Team
4:00 PM - 4:15 PM	Invited talk: Prof. Sebin, Sreepathy Institute of Technology
4:15 PM - 4:30 PM	Invited talk: Prof. Maheshwari, VIT Chennai
4:30 PM - 5:00 PM	Invited talk: Wladek Grabinski, MOS-AK: FOSSS TCAD/EDA Tools
Overnight	Complete the practice problems
13 Feb 2021 (Subcircuit builder and Introduction to NGHDL)
9:30 AM - 10:00 AM	Discussion of practice problems (Optional)
10:00 AM - 10:50 AM	Spoken Tutorial session: Subcircuit Builder
10:50 AM - 11:40 AM	Spoken Tutorial session: Editing a Subcircuit
11:40 AM - 12:30 PM	Spoken Tutorial session: Uploading a spice Subcircuit file
12:30 PM - 1:00 PM	Mixed-signal simulation talk and demo: FOSSEE team
Lunch Break
2:00 PM - 3:00 PM	Practice problem on Mixed-Signal circuit simulation using NGHDL
3:00 PM - 3:20PM	How NGHDL is extended for microcontrollers: Ashutosh Jha, FOSSEE Intern 2020
3:20 PM - 3:40 PM	Expert Talk: Prof Madhav Desai, IIT Bombay
3:40 PM - 4:00 PM	Q&A
4:00 PM - 4:15 PM	Expert talk: Prof Kimberly Moraes
4:15 PM - 4:30 PM	Benefits of contribution to FOSSEE's eSim efforts
4:30 PM - 5:00 PM	Feedback and valedictory

Kannan Moudgalya 

Pramod Murali 

Mohamed Kasim Khan 

Usha Viswanathan 

Saurabh Bansode 

Smita Wangikar

#XFAB Makes Major Enhancements to its 180 nm #APD and #SPAD

#XFAB Makes Major Enhancements to its 180 nm #APD and #SPAD Devices with Boosted Photon Detection Performance and Increased Active Area https://t.co/fbW2O3cpws #semi pic.twitter.com/sZbwRNtowm

— Wladek Grabinski (@wladek60) February 4, 2021

---

from Twitter https://twitter.com/wladek60

February 04, 2021 at 09:28AM
via IFTTT