Showing posts with label structures. Show all posts
Showing posts with label structures. Show all posts

Sep 28, 2023

[C4P] 36th ICMTS 2024

36th International Conference on Microelectronic Test Structures
April 15-18, 2024, Edinburgh, Scotland

Looking for the best opportunity to present and discuss your ideas and results about test structures, measurements and characterization? This is your chance! Join the 36th ICMTS conference. A Tutorial Short Course will precede the main conference. Several of the best measurement, equipment design, and manufacturing experts, will participate in the equipment exhibition and presentations. The conference will bring together designers and users of test structures to discuss recent developments and future directions, in a one-track program, with convivial breaks allowing attendees to discuss and exchange viewpoints and challenges.

A Best Paper award will be presented by the Technical Program Committee. The conference is co-sponsored by the IEEE Electron Devices Society and all accepted papers, if presented, will be submitted for possible inclusion on IEEEXplore®. Original papers are solicited presenting new developments in topics relevant to ICMTS, including but not limited to, test structures, measurements, and results, in the following areas:
  • Design
    • Methodologies, Verification
    • Within-die circuits for process characterization/monitoring
    • Design enablement – Characterization and validation of digital and analog libraries
    • Devices and Circuit Modelling
  • Measurement techniques
    • DC, AC and RF measurements: setup, test and analysis
    • Reliability test - including thermal stability, failure analysis etc.
    • Statistical analysis, variability, throughput increase, smart test strategies
    • Use of machine learning and AI in analysis of data sets - parameter extraction etc.
    • Wafer probing, within-die measurements, in-line metrology
    • Throughput, testing strategies, yield enhancement and process control tests
  • Applications
    • Emerging memory technologies (single cell, arrays, and application in neural networks)
    • Emerging transistor technologies for digital/analog/power applications
    • Photonic devices - silicon integration, new displays (OLED, μ-displays)
    • Flexible electronics and sensors (organic and inorganic materials)
    • M(N)EMS, actuators, sensors, PV cells and other emerging devices
The author’s abstract submission consists of up to four pages in PDF format (font-embedded). The first page should include a title, a 50-word summary, author name(s), full address, contact number and e-mail of the lead author, and any preference for oral or poster session presentation. The body of the abstract should consist of one page of text (800 to 1000 words) and up to two pages of major figures and tables. The selection process will be based on the technical merit and will be highly weighted in favour of abstracts with high test structure content, giving a clear illustration of the test structure and including measurements and data analysis.

The abstract submission deadline is October 27th, 2023.

Abstracts can be submitted via the ICMTS 2024 website www.icmts.net using the “Abstract Submission” link on the front page. Notice of paper acceptance will be sent to the selected authors by 12th January 2024, with instructions for the expanded manuscript preparation for the conference proceedings. The deadline for submission of the final paper will be Early March, 2024 (TBC).

Please join the ICMTS LI group, if you have interest in all things test and measurement.

Details of the venue, hotel, registration, etc. will be posted when available at the ICMTS 2024 official website.

For further technical information, please contact the technical program chair:
Francesco Driussi, Università di Udine

Feb 8, 2021

[paper] Simulations of transient processes in the nc-MOS structures

D. Tanous, A. Mazurak and B. Majkusiak 
Simulations of transient processes and characteristics of the nc-MOS structures 
Microelectronic Engineering, 
Volume 178, 2017, pp/ 173-177, 
DOI: 10.1016/j.mee.2017.05.013 

Abstract: Experimentally measured capacitance-voltage and current-voltage characteristics of the metal-insulator-semiconductor structures with nanocrystals embedded in the insulator often exhibit formations which result from charging/discharging processes of the nanocrystals and are difficult to explain and predict intuitively. Time dependent simulations as presented in this paper can be helpful in their analysis. The paper presents a study of the impact of selected geometrical parameters on their characteristics with the bias voltage ramp rate as a parameter.
FIG: a.) nc-MIS Structure; b.) Bias voltage ramp stimulation; c.)  CV and IV Simulations results