| ||||||||||||||||||||||||||||||||||||||||||||
Sep 17, 2020
Fwd: September 2020 Newsletter: Planet-Scale Processing of Silicates
[paper] Low-voltage, Non-volatile, Compound-semiconductor Memory Cell
Room-temperature Operation of Low-voltage, Non-volatile, Compound-semiconductor Memory Cell
Ofogh Tizno, Andrew R. J. Marshall, Natalia Fernández-Delgado, Miriam Herrera, Sergio I. Molina
and Manus Hayne
and Manus Hayne
Scientific Reports volume 9, Article number: 8950 (2019)
DOI: 10.1038/s41598-019-45370-1
Abstract: Whilst the different forms of conventional (charge-based) memories are well suited to their individual roles in computers and other electronic devices, flaws in their properties mean that intensive research into alternative, or emerging, memories continues. In particular, the goal of simultaneously achieving the contradictory requirements of non-volatility and fast, low-voltage (low-energy) switching has proved challenging. Here, we report an oxide-free, floating-gate memory cell based on III-V semiconductor heterostructures with a junctionless channel and non-destructive read of the stored data. Non-volatile data retention of at least 10000s in combination with switching at ≤2.6 V is achieved by use of the extraordinary 2.1 eV conduction band offsets of InAs/AlSb and a triple-barrier resonant tunnelling structure. The combination of low-voltage operation and small capacitance implies intrinsic switching energy per unit area that is 100 and 1000 times smaller than dynamic random access memory and Flash respectively. The device may thus be considered as a new emerging memory with considerable potential.
FIG: Device structure a) Schematic of the processed device with control gate (CG), source (S) and drain (D) contacts (gold). The red spheres represent stored charge in the floating gate (FG). b) Cross-sectional scanning transmission electron microscopy image showing the high quality of the epitaxial material, the individual layers and their heterointerfaces.
Simulation Methods: The nextnano software package was utilised for mathematically modelling the energy band diagram of the memory device structure reported here, taking into account strain and piezoelectricity. Within this work, a self-consistent Schrödinger solver was used along with the Poisson and drift–diffusion equations to calculate the electron densities at equilibrium and under bias.
Sep 16, 2020
The Industry’s First SoC FPGA Development Kit Based on the #RISC-V Instruction Set Architecture is Now Available | Microchip Technology https://t.co/1CCwP6GR3h #semi https://t.co/TKw7mFqOcC
The Industry’s First SoC FPGA Development Kit Based on the #RISC-V Instruction Set Architecture is Now Available | Microchip Technology https://t.co/1CCwP6GR3h #semi pic.twitter.com/TKw7mFqOcC
— Wladek Grabinski (@wladek60) September 16, 2020
from Twitter https://twitter.com/wladek60
September 16, 2020 at 04:32PM
via IFTTT
Sep 15, 2020
FreePDK15: Process Design kit for 15-nm FinFETs
Development of a Predictive Process Design kit for 15-nm FinFETs: FreePDK15
Kirti Bhanushali, Chinmay Tembe, and W. Rhett Davis
arXiv:2009.04600v1 [cs.AR] 9 Sep 2020
Abstract: FinFETs are predicted to advance semiconductor scaling for sub-20nm devices. In order to support their introduction into research and universities it is crucial to develop an open source predictive process design kit. This paper discusses in detail the design process for such a kit for 15nm FinFET devices, called the FreePDK15. The kit consists of a layer stack with thirteen-metal layers based on hierarchical-scaling used in ASIC architecture, Middle-of-Line local interconnect layers and a set of Front-End-of-Line layers. The physical and geometrical properties of these layers are defined and these properties determine the density and parasitics of the design. The design rules are laid down considering additional guidelines for process variability, challenges involved in FinFET fabrication and a unique set of design rules are developed for critical dimensions. Layout extraction including modified rules for determining the geometrical characteristics of FinFET layouts are implemented and discussed to obtain successful Layout Versus Schematic checks for a set of layouts. Moreover, additional parasitic components of a standard FinFET device are analyzed and the parasitic extraction of sample layouts is performed. These extraction results are then compared and assessed against the validation models.
FIG: Middle-of-Line layers used as interconnects
Acknowledgment: The authors would like to thank Paul Franzon at NC State University. The authors would like to thank Mentor Graphics, since this project would not have been possible without their generous gift of supporting funds and Calibre licenses. The authors would also like to thank Tarek Ramadan, Ahmed Hammed Fathy, Omar El-Sewefy, Ahmed El-Kordy, Hend Wagieh and the team at Mentor Graphics for development of the first set of design rules and their constant support.In addition, the authors would like to thank and acknowledge Alexandre Toniolo at Nangate for clarifying the vision of MOL layers. We would also like to thank Cadence designsystems for use of the virtuoso software and Synopsys Inc.for use of Pycell studio. The authors would also like to thanks Vikas Sharma for P-Cells, Vidyanandgouda Patil for design rule fixes and Namrata Sampat for help cleaning up the distribution.
Online Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates (Sept 14-19, 2020)
Respected All
On behalf of the organizing committee of the Science Academies Online Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates (Sept 14-19, 2020),
I am sharing separate Zoom Links for each day.
You are requested to register yourself for one or more sessions by registering separately.
Kindly forward this email to your friends, students and colleagues from all branches of science and engineering.
- Kindly join at least 15 minutes before the session.
- Letter of attendance for each day will be provided at the end of the session.
September 15, 2020 (Zoom Link: https://zoom.us/webinar/register/WN_JF5EVXqsTBCcHLIuL2e7dA)
- 04:00 pm – 05:00 pm - The Lead Halide Perovskites: Photoluminescence and Charge Carrier Dynamics - Professor Anunay Samanta, FASc, FNASc, FNA, Sr. Professor and J.C. Bose National Fellow (DST), School of Chemistry, University of Hyderabad
- 05:00 pm – 06:00 pm - Interdisciplinary Education for Science and Innovation - Professor Sourav Pal, FASc, FNASc, FNA, Director, Indian Institute of Science Education & Research, West Bengal
September 16, 2020 (Zoom Link: https://zoom.us/webinar/register/WN_hbdn7CqUQMqWUeyaW7qJTA)
- 06:00 pm – 07:00 pm Electronic Cash, Cryptocurrencies and Smart Contracts - Professor Rudrapatna Kallikote Shyamasundar, FASc, FNA, FNASc, FNAE, FIEEE, FTWAS, Distinguished V Professor, Computer Science & Engineering Department, IIT Powai
- 06:00 pm – 07:00 pm - Indian Healthcare, Digital Transformation, and COVID-19 - Dr Anurag Agrawal, FNA, Director, CSIR-Institute of Genomics and Integrative Biology, Mall Road, Delhi University
- 07:00 pm – 08:00 pm - Responsibilities and opportunities for academics in the context of current pandemic - Dr. Rakesh K Mishra, FASc, FNASc, FNA, Director, CSIR-Centre for Cellular & Molecular Biology, Hyderabad
- 06:00 pm – 07:00 pm - Continued fraction expansions of complex numbers - Prof. Shrikrishna Gopalrao Dani, FASc, FNA, FNASc, Distinguished Professor, Centre for Excellence in Basic Sciences, University of Mumbai, Maharashtra
- 07:00 pm – 08:00 pm - C.R.Rao and Mahalanobis' Distance - Prof. Probal Chaudhuri, FASc, FNA, FNASc, Theoretical Statistics and Mathematics Unit, Indian Statistical Institute, Kolkata
- 06:00 pm – 07:00 pm - Future Geosciences and Opportunities - Prof. Ashok Kumar Singhvi, FASc, FNA, FNASc, FTWAS, Honorary Scientist, Atmospheric, Molecular & Optical Physics Divn., PRL, Gujarat
- 07:00 pm – 08:00 pm - Glasses and other amorphous solids - Professor Srikanth Sastry, FASc, FNASc, FNA, Theoretical Sciences Unit, JNCASR, Bangalore, Karnataka
with regards
Dr. Manoj Saxena | डॉ मनोज सक्सेना
Associate Professor | सह - आचार्य
Department of Electronics | इलेक्ट्रॉनिक्स विà¤ाग
Deen Dayal Upadhyaya College | दीन दयाल उपाध्याय कॉलेज
University of Delhi | दिल्ली विश्वविद्यालय
Dwarka Sector-3, New Delhi-110078 | द्वारका क्षेत्र -३, नई दिल्ली -११००à¥à¥®
India | à¤ारत
Official Homepage: https://dducollegedu.ac.in/ViewProfile.aspx?fId=saxenamanoj77@gmail.com
ORCID Webpage : http://orcid.org/0000-0002-9368-4194
Scopus Webpage : http://www.scopus.com/authid/detail.url?authorId=35480023200
ResearcherID-Thomson Reuters : http://www.researcherid.com/rid/K-3863-2015
Publons Profile: https://publons.com/researcher/1341187/manoj-saxena
Please do not print this email unless it is absolutely necessary. Spread environmental awareness.
Sep 14, 2020
[mos-ak] Fwd: ESSCIRC ESSDERC 2020 Virtual Educational Events | IMPORTANT MESSAGE
|
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/mos-ak/CALp-Rj_4EzeNd1cNwE-Jfx8nsGBrcSH3vN3KTxttAX2enMx96g%40mail.gmail.com.
2020 IEEE #IEDM To Highlight Innovative Devices for a #Better #Future
2020 IEEE #IEDM To Highlight Innovative Devices for a #Better #future https://t.co/8m1toPqhfI #paper pic.twitter.com/3FlTSlo3Id
— Wladek Grabinski (@wladek60) September 14, 2020
from Twitter https://twitter.com/wladek60
September 14, 2020 at 10:25AM
via IFTTT
Sep 9, 2020
[paper] Analogue 2D Semiconductor Electronics
Analogue two-dimensional semiconductor electronics
Dmitry K. Polyushkin1, Stefan Wachter1, Lukas Mennel1, Matthias Paur1, Maksym Paliy2, Giuseppe Iannaccone2, Gianluca Fiori2, Daniel Neumaier3,4, Barbara Canto3,4
and Thomas Mueller1
Nat Electron 3, 486–491 (2020)
DOI: 10.1038/s41928-020-0460-6
2Dipartimento di Ingegneria dell’Informazione, Università di Pisa, Pisa, Italy.
3AMO GmbH, Aachen, Germany.
4Bergische Universität Wuppertal, Wuppertal, Germany
Abstract: Digital electronics are ubiquitous in the modern world, but analogue electronics also play a crucial role in many devices and applications. Analogue circuits are typically manufactured using silicon as the active material. However, the desire for improved performance, new devices and flexible integration has—as for their digital counterparts—led to research into alternative materials, including the use of two-dimensional (2D) materials. Here, we show that operational amplifiers—a basic building block of analogue electronics—can be created using the 2D semiconductor molybdenum disulfide (MoS2) as the active material. The device is capable of stable operation with good performance, and we demonstrate its use in feedback circuits including inverting amplifiers, integrators, log amplifiers and transimpedance amplifiers. We also show that our 2D platform can be used to monolithically integrate an analogue signal preconditioning circuit with a MoS2 photodetector.
Fig: a) Schematic of the back-gated transistor architecture;
b) Transfer characteristics of a typical transistor on the chip (W/L = 4);
c) View of a single OPA showing the pinout and transistor labelling
Circuit design and modelling: Because a complete model of back-gated 2D semiconductor FETs is still not readily available, we fitted the experimental results with an Enz–Krummenacher– Vittoz (EKV) model in both, the subthreshold and inversion, regimes. All the transistors operate in the inversion regime, we used the inversion model to simulate the OPA, obtaining a nominal low-frequency Atot gain value.
Acknowledgements: We thank A.J. Molina-Mendoza for technical assistance and N. Schaefer and J.A. Garrido for providing a polyimide substrate. We acknowledge financial support by the European Union (grant agreements 785219 Graphene Flagship, 796388 ECOMAT and 828901 ORIGENAL), the Austrian Science Fund FWF (START Y 539-N16) and the Italian MIUR (FIVE 2D).
Electronic Frontier Foundation Turns 30 This Year! Learn More About #EFF, and How You Can Help. https://t.co/jDPakWReaO #OpenSource https://t.co/7bDPyRYenl
Electronic Frontier Foundation Turns 30 This Year! Learn More About #EFF, and How You Can Help. https://t.co/jDPakWReaO #OpenSource pic.twitter.com/7bDPyRYenl
— Wladek Grabinski (@wladek60) September 9, 2020
from Twitter https://twitter.com/wladek60
September 09, 2020 at 09:15AM
via IFTTT
Sep 8, 2020
#India now ranks among the #Top10 countries in terms of the number of #opensource projects [https://t.co/5VnCn8CErA] https://t.co/v2IsUB9ZZL https://t.co/ScATobwByx
#India now ranks among the #Top10 countries in terms of the number of #opensource projects [https://t.co/5VnCn8CErA] https://t.co/v2IsUB9ZZL pic.twitter.com/ScATobwByx
— Wladek Grabinski (@wladek60) September 8, 2020
from Twitter https://twitter.com/wladek60
September 08, 2020 at 03:27PM
via IFTTT
[paper] RF Small-Signal Model for Four-Port Network MOSFETs
A High-Frequency Small-Signal Model for Four-Port Network MOSFETs
Alejandro Roman-Loera1, Member, IEEE, Anurag Veerabathini2, Member, IEEE, Luis A.Flores-Oropeza1, Member, IEEE, and Jaime Ramirez-Angulo3, Life Fellow, IEEE
IEEE 63rd IMWSCAS 2020
DOI:10.1109/mwscas48704.2020.9184475
2Maxim Integrated, Chandler, AZ, USA.
3Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM, USA.
Abstract: A high-frequency small-signal model for a MOSFET is proposed considering the parasitic capacitances associated with each terminal that is critical in the design of high-frequency amplifiers. The proposed model allows in obtaining a closed form expression for poles and zeros due to parasitic elements along with the conventional poles and zeros. This model gives an additional degree of freedom in choosing the location of poles and zeros to improve the frequency response. The proposed high-frequency small-signal model for MOSFET is validated in simulation by implementing a high-frequency voltage follower in 0.18µm CMOS process. The proposed model shows the existence of a zero in a voltage follower that is introduced by the parasitic elements at high-frequencies and it is validated with implementation.
 |
Acknowledgment: This work has been supported by PRODEP program from SEP (Secretariat of Public Education, Mexico) and Universidad Autonoma de Aguascalientes, Aguascalientes, Mexico.
Sep 7, 2020
#25 #Microchips That Shook the #World - IEEE Spectrum https://t.co/XCdh3S0ClW #semi https://t.co/JFWuLICVDT
1968 Fairchild Semiconductor μA741 Op-Amp#25 #Microchips That Shook the #World - IEEE Spectrum https://t.co/XCdh3S0ClW #semi pic.twitter.com/JFWuLICVDT
1971 Signetics NE555 Timer
1971 Western Digital WD1402A UART
1973 Mostek MK4096 4-Kilobit DRAM
1975 MOS Technology 6502 Microprocessor
1976 Zilog Z80 Microprocessor
1978 Texas Instruments TMC0281 Speech Synthesizer
1979 Intel 8088 Microprocessor
1979 Motorola MC68000 Microprocessor
1983 Intersil ICL8038 Waveform Generator
1983 Texas Instruments TMS32010 Digital Signal Processor
1985 Acorn Computers ARM1 Processor
1985 Chips & Technologies AT Chip Set
1985 Xilinx XC2064 FPGA
1986 Kodak KAF-1300 Image Sensor
1987 Sun Microsystems SPARC Processor
1987 Texas Instruments Digital Micromirror Device
1988 Computer Cowboys Sh-Boom Processor
1989 Toshiba NAND Flash Memory
1993 Microchip Technology PIC 16C84 Microcontroller
1994 Amati Communications Overture ADSL Chip Set
1997 IBM Deep Blue 2 Chess Chip
1997 Micronas Semiconductor MAS3507 MP3 Decoder
1998 Tripath Technology TA2020 AudioAmplifier
2000 Transmeta Corp. Crusoe
— Wladek Grabinski (@wladek60) September 7, 2020
from Twitter https://twitter.com/wladek60
September 07, 2020 at 03:57PM
via IFTTT
[paper] Vertical Graphene–hBCN Heterostructure TFETs
A comparative computational study of tunneling transistors
based on vertical graphene–hBCN heterostructures
Mahsa Ebrahimi1, Ashkan Horri1, Majid Sanaeepur2, and Mohammad Bagher Tavakoli1
J. Appl. Phys. 127, 084504 (2020); DOI: 10.1063/1.5130777
Published Online: 28 February 2020
1Department of Electrical Engineering, Arak Branch, Islamic Azad University, Arak, Iran
2Department of Electrical Engineering, Faculty of Engineering, Arak, Iran
ABSTRACT In this paper, the electrical characteristics of tunneling transistors based on vertical graphene and a hexagonal boron-carbon-nitrogen (hBCN) heterostructure are studied and compared theoretically. We have considered three different types of hBCN, i.e., BC2N, BC2N0, and BC6N as a tunneling barrier. Our simulation is based on the nonequilibrium Green’s function formalism along with an atomistic tightbinding (TB) model. The TB parameters are obtained by fitting the band structure to first-principles results. By using this method, electrical characteristics of the device, such as the ION=IOFF ratio, subthreshold swing, and intrinsic gate-delay time, are investigated. For a fair comparison, the effects of geometrical variations and number of tunneling barrier layers on the electrical parameters of the device are simulated and investigated. We show that, by an appropriate design, the device can be used for low-power or high-performance applications. The device allows current modulation exceeding 106 at room temperature for a 0.6 V bias voltage.
FIG. DFT Band structure for (a) graphene - hBC2N0 - graphene (b) graphene - hBC2N - graphene and (c) graphene - hBC6N - graphene supercell. BC and BV represent barrier height in the conduction band and valence band, respectively, all simulated with QUANTUM ESPRESSO: A modular and opensource software for quantum simulations of materials
OFETs Compact Modeling
Advances in Compact Modeling of Organic Field-Effect Transistors
Sungyeop Jung1, Member, IEEE, Yvan Bonnassieux2, Gilles Horowitz2, Sungjune Jung1, Member, IEEE, Benjamin Iñiguez3, Fellow, IEEE, and Chang-Hyun Kim4, Senior Member, IEEE
IEEE J-EDS (Early Access)
DOI: 10.1109/JEDS.2020.3020312
1Future IT Innovation Laboratory and Department of Creative IT Engineering, Pohang University of Science and Technology, Pohang 37673, South Korea.
2LPICM, Ecole Polytechinque, CNRS, 91128 Palaiseau, France.
3DEEEA, Universitat Rovira i Virgili, Tarragona 43007, Spain.
4Department of Electronic Engineering, Gachon University, Seongnam 13120, South Korea
Abstract: In this review, recent advances in compact modeling of organic field-effect transistors (OFETs) are presented. Despite the inherent strength for printed flexible electronics and the extremely aggressive research conducted over more than three decades, the OFET technology still seems to remain at a relatively low technological readiness level. Among various possible reasons for that, the lack of a standard compact model, which effectively bridges the device- and system-level development, is clearly one of the most critical issues. This paper broadly discusses the essential requirements, up-to-date progresses, and imminent challenges for the OFET compact device modeling toward a universal, physically valid, and applicable description of this fast-developing technology.
Figure (a) Cross-sectional illustration and (b) circuit diagram with multi-component overlap capacitances of the printed 3-D organic complementary inverter, and (c) measured and simulated transient output voltage of an 11-stage ring oscillator.
Sep 4, 2020
#Special Issue: The 11th International Symposium on Electric and Magnetic Fields (#EMF 2018) https://t.co/pVDWOoLXC4 #paper https://t.co/HqmYxemttD
#Special Issue: The 11th International Symposium on Electric and Magnetic Fields (#EMF 2018) https://t.co/pVDWOoLXC4 #paper pic.twitter.com/HqmYxemttD
— Wladek Grabinski (@wladek60) September 4, 2020
from Twitter https://twitter.com/wladek60
September 04, 2020 at 10:39AM
via IFTTT
Startups encouraged to get busy with #opensource 32-bit #Shakti, 64-bit Vega. #India selects RISC-V for semiconductor self-sufficiency contest: Use these #homegrown cores to build kit https://t.co/HUbXBJHILM https://t.co/yTs6D904JK
Startups encouraged to get busy with #opensource 32-bit #Shakti, 64-bit Vega. #India selects RISC-V for semiconductor self-sufficiency contest: Use these #homegrown cores to build kit https://t.co/HUbXBJHILM pic.twitter.com/yTs6D904JK
— Wladek Grabinski (@wladek60) September 4, 2020
from Twitter https://twitter.com/wladek60
September 04, 2020 at 09:09AM
via IFTTT
Sep 3, 2020
[eBook] download figures: POWER/HVMOS Devices Compact Modeling
Broadband Measurements to 220 GHz
VectorStar ME7838G 70 kHz to 220 GHz Single Sweep VNA Measurements and On-Wafer Calibrations
- Miniature mmWave MA25400A NLTL module connects directly to probes without cables for best dynamic range and stability
- MPI TITAN Probes available in 50, 75, and 100 um pitch
- Probes are field replaceable
- SOLT up 40 or 70 GHz if standards provide required performance
- LRM, ALRM, LRRM, and multiline TRL up to 220 GHz
- SOLR when thru is not 0 length, is not well matched, insertion loss is less known, and there is no .s2p file describing the thru
Calibration substrates:
- Available from MPI
- When possible, use a ceramic chuck to minimize the potential for multimode parasitic propagation.
- Alternatively, use an isolation wafer on metal chuck if available
[paper] Wearable Energy Harvester
A Piezoelectric-Transducer-Biased 3-D Photosensitive Thin-Film Transistor
as a Dual-Mode Wearable Energy Harvester
Emad Iranmanesh1, Weiwei Li2,3, Ahmed Rasheed2,3, and Kai Wang2,3 (Member IEEE)
IEEE EDL, Vol. 41, No. 9, Sept. 2020
DOI: 10.1109/LED.2020.3009685
1School of Electronics and Information Technology, Sun Yat-sen University, Guangzhou 510006, China.
2Guangdong Provincial Key Laboratory of Display Material and Technology, Sun Yat-sen University, Guangzhou 510006, China
3State Key Laboratory of Optoelectronic Materials and Technologies, School of Electronics and Information Technology, Sun Yat-Sen University, Guangzhou 510006, China
Abstract: This letter reports on a dual-mode wearable energy harvester that utilizes both piezoelectric and photoelectric effects. It integrates a piezoelectric transducer with a 3-D photosensitive dual-gate thin-film transistor (DGTFT) as a rectifier and a buffer. The energy conversion efficiency is enhanced by reducing the internal resistance of the 3-D photosensitive DGTFT upon light illumination. Such a dual-mode energy harvester is promising for wearable electronics.
Fig.: a) Schematic diagram of the proposed wearable dual-mode energy harvester formed by a polyvinylidene difluoride (PVDF) transducer integrated with a self-driven diode-connected 3-D photosensitive DGTFT as a buffer and a rectifier; b) Equivalent circuit of the proposed dual-mode harvester.
Acknowlwgement: This work was supported by the Guangdong Innovative Research and Entrepreneurial Team Program under Grant 2014ZT05D340
Subscribe to:
Posts (Atom)