[paper] Cryogenic CMOS Device Modeling

Zhidong Tang, Zewei Wang, Yumeng Yuan, Chang He, Xin Luo, Ao Guo, Renhe Chen, Yongqi Hu, Longfei Yang, Chengwei Cao, Linlin Liu, Liujiang Yu, Ganbing Shang, Yongfeng Cao, Shoumian Chen, Yuhang Zhao, Shaojian Hu, and Xufeng Kou

Generic Cryogenic CMOS Device Modeling and EDA-Compatible Platform 

for Reliable Cryogenic IC Design

IEEE JEDS, vol. 13, pp. 117-127 (2025)

DOI: 10.1109/JEDS.2025.3542589

1. ShanghaiTech University, Shanghai (CN)
2. University of Chinese Academy of Sciences, Beijing (CN)
3. Shanghai IC Research and Development Center, Shanghai (CN)
4. Huali Microelectronics Corporation (HLMC), Shanghai (CN)
5. School of Integrated Circuits, Tsinghua University, Beijing (CN)

Abstract: This paper outlines the establishment of a generic cryogenic CMOS database in which key electrical parameters and transfer characteristics of the MOSFETs are quantified as functions of device size, temperature, and frequency responses. Meanwhile, a comprehensive device statistical study is conducted to evaluate the influence of variation and mismatch effects at low temperatures. Furthermore, by incorporating the Cryo-CMOS compact model into the HLMC process design kit (PDK), the cryogenic 4Kb SRAM, 5-bit flash ADC and 8-bit current steering DAC are designed, and their performance is readily investigated and optimized on the EDA-compatible platform, hence laying a solid foundation for large-scale cryogenic IC design.

FIG: Schematic of the solid-state based quantum computer architecture 

with integrated quantum control system in a cryogenic environment.

Acknowledgments: This work was supported by the National Key R&D Program of China (2021YFA0715503, 2023YFB4404000), National Natural Science Foundation of China (92164104), the Strategic Priority Research Program of CAS (XDA18010000), Shanghai Rising-Star Program (21QA1406000) and the Open Fund of State Key Laboratory of Infrared Physics.

[CNM25] Academic Process Design Kit

The aim of this academic process design kit (APDK) is to introduce circuit designers to the top-down design methodology of mixed-signal full-custom integrated circuits (ICs) in CMOS technologies. For this purpose, the following freely available electronic design automation (EDA) tools are proposed for both the schematic and the physical IC design. The APDK incorporates all the required technological information for the simple 2.5um 1P2M PiP CMOS technology (CNM25) from IMB-CNM(CSIC). Anyway, this APDK can be easily customized to extend its coverage to more complex CMOS technologies.

News 2024.04.09:

APDK release version 2024_04_09
+ Update to Glade 6.x series (Qt6)
+ Screenshots

REF: Poster at IEEE ISCAS 2017 in Baltimore, MD, USA.

CONTACT: 

Francesc Serra-Graells

www.cnm.es/users/pserra

tel: +34 93 594 77 00

fax: +34 93 580 02 67

IMB-CNM (CSIC)

Campus UAB Bellaterra

08193 Cerdanyola del Vallès, SPAIN

 

FreePDK15: Process Design kit for 15-nm FinFETs

Development of a Predictive Process Design kit for 15-nm FinFETs: FreePDK15 

Kirti Bhanushali, Chinmay Tembe, and W. Rhett Davis 

arXiv:2009.04600v1 [cs.AR] 9 Sep 2020

Abstract: FinFETs are predicted to advance semiconductor scaling for sub-20nm devices. In order to support their introduction into research and universities it is crucial to develop an open source predictive process design kit. This paper discusses in detail the design process for such a kit for 15nm FinFET devices, called the FreePDK15. The kit consists of a layer stack with thirteen-metal layers based on hierarchical-scaling used in ASIC architecture, Middle-of-Line local interconnect layers and a set of Front-End-of-Line layers. The physical and geometrical properties of these layers are defined and these properties determine the density and parasitics of the design. The design rules are laid down considering additional guidelines for process variability, challenges involved in FinFET fabrication and a unique set of design rules are developed for critical dimensions. Layout extraction including modified rules for determining the geometrical characteristics of FinFET layouts are implemented and discussed to obtain successful Layout Versus Schematic checks for a set of layouts. Moreover, additional parasitic components of a standard FinFET device are analyzed and the parasitic extraction of sample layouts is performed. These extraction results are then compared and assessed against the validation models.

FIG: Middle-of-Line layers used as interconnects

Acknowledgment: The authors would like to thank Paul Franzon at NC State University. The authors would like to thank Mentor Graphics, since this project would not have been possible without their generous gift of supporting funds and Calibre licenses. The authors would also like to thank Tarek Ramadan, Ahmed Hammed Fathy, Omar El-Sewefy, Ahmed El-Kordy, Hend Wagieh and the team at Mentor Graphics for development of the first set of design rules and their constant support.In addition, the authors would like to thank and acknowledge Alexandre Toniolo at Nangate for clarifying the vision of MOL layers. We would also like to thank Cadence designsystems for use of the virtuoso software and Synopsys Inc.for use of Pycell studio. The authors would also like to thanks Vikas Sharma for P-Cells, Vidyanandgouda Patil for design rule fixes and Namrata Sampat for help cleaning up the distribution.