[OpenSUSI] First Tyepout

J. I. Okamura

New Semiconductor Design Programs with Japan’s Open Source Ecosystem

[Society News] in IEEE Solid-State Circuits Magazine, vol. 18, no. 3, pp. 87-88, Summer 2026, 

doi: 10.1109/MSSC.2026.3708432

Abstract: Open Source Utilized Silicon Initiatives (OpenSUSI), founded in April 2024 as a nonprofit organization, has been working closely with two Japanese legacy foundries to foster an open source silicon ecosystem in Japan. On 19 September 2025, TOKAI RIKA Co., Ltd., a 6-inch legacy foundry in Japan, announced the release of a non-disclosure-free process design kit (PDK) as an open source platform [1]. This new open source PDK, called TR-1um [2], was released via the OpenSUSI GitHub repository, and, since last October, we have been cleaning up and maintaining it alongside our collaborators.

Fig. First Tapeout application form on the OpenSUSI homepage.

[OpenPDK] GT2N

This the initial release for the GT2N PDK with 72 standard cells: <https://github.com/azadnaeemi/GT2N>.

It is based on 2nm GAAFET with BSPDN. All the device models are based on 3-stack nanosheets

Standard cell layouts can also be imported using the .gds file: GT2N/gds/gt2_6t_std_cells.gdsLVS and DRC rulesets for icvalidator are present in "GT2N/icv_runset".
Libraries are composed of 3 process corners (under development), 2 nanosheet width (W) flavors, and 5 threshold voltage (VT) flavors. (In the order of decreasing VT, HVT > SVT > LVT > ULVT > ELVT)

The collaterals required for synthesis and PnR are (depending on the process corner and W/VT flavor):

LIB: GT2N/lib/tt/gt2_6t_w31_lvt_tt_0p7v25c.lib
LEF: GT2N/lef/tt/gt2_6t_w31_lvt.lef
Techlef: GT2N/techlib/gt2_tech.lef
ICT: GT2N/qrc/GT2.ict
QRCTech: GT2N/qrc/GT2_qrc.tch
ITF: GT2N/nxtgrd/GT2.itf
NXTGRD: GT2N/nxtgrd/GT2.nxtgrd

The thermal-calibrated GAAFET (3-stack nanosheet) model card is (depending on the process corner and W/VT flavor):

GT2N/device/tt/gt2_w31_lvt_tt.sp

[ref] D. Jang, P. Kumar, M. N. H. Shazon, S. J. Ram, A. Svizhenko, V. Moroz, A. Ceyhan, N. A. Radhakrishn, and A. Naeemi, "GT2N: An Open-Source 2nm Nanosheet PDK Enabling Multi-Width/VT Benchmarking" in IEEE International Symposium on Circuits and Systems (ISCAS) 2026  

[ICTA2026 ] Special OpenPDK Session

IEEE International Conference on Integrated Circuits, Technologies & Applications

ICTA 2026 Special Session “OpenPDK - Global FOSS Scholar Platform"

21st - 24th (Wed - Sat) October 2026

Grand Copthorne Waterfront Hotel, Singapore

The OpenPDK initiative delivers a global FOSS Scholar Platform supporting analog/RF, mixed‑signal, and digital IC design. Central to this effort are accurate SPICE models for low‑power sensing MOSFETs, RF HBTs, and emerging RRAM devices, validated across cryogenic temperatures for space and quantum‑computing applications. The initiative also advances Verilog‑A compact‑model standardization, ensuring result reproducibility and seamless integration into open‑source design flows. Supported by the EU Chips JU, OpenPDK fosters collaboration among academia, startups, and industry, while providing FOSS IC‑design tools covering schematic capture, simulation, layout, and verification up to tape‑out. Similar to the EU Chips JU program, Zhejiang CoreXin in China offers an open‑source PDK together with tape‑out services for its 55nm CMOS process. To accelerate the semiconductor‑industry development across the Asia‑Pacific and Southeast‑Asia regions, semiconductor model development and parameter extraction techniques should be pursued in a more focused manner. This special session brings together experts to present and discuss advances in device characterization, compact modeling, simulation methodologies, and validation techniques for a broad range of solid‑state devices, including Si, III/V semiconductors, power devices, nanoscale structures, and emerging 2.5D/3D advanced packaging technologies [ read more...]

ICTA 2026 Special OpenPDK Session Presenters

• SPICE/Verilog-A standard models and OpenPDK practice
  Wladek Grabinski, GMC Consulting, Switzerland
• Open-Source Ecosystem Updates and Semiconductor Design Development Programs in Japan
  Jun-ichi Okamura, AIST Solutions, OpenSUSI, Japan
• Open-Source EDA Meets Industrial IC Design
  Ehrenfried Seebacher, ams-OSRAM AG, Austria
• Building an Open-Source Process Platform, Empowering VLSI Innovation and Development
  Da Zhang, Zhejiang University/CTO, Zhejiang Chuangxin Integrated Process Platform, China
• From Silicon to Design: Intelligent Measurement and Modeling for DTCO
  Yutao Ma, VP of R&D, Primarius Technologies. Ltd. China
• Beyond Moore, Application-Driven IC Innovation International Cooperation Opportunities at NICE
  Alex Gu, National Innovation Center Par Excellence (NICE), China
• 2.5D/3D IC: AI+EDA Reshaping the System-Design-Technology Co0ptimization (STCO) Paradigm for Advanced Packaging
  Alex Zhao, Founder/CEO Zhuhai SiChip Technology Co., Ltd., China
• Modelling of semiconductor devices: the heart of innovation bridging academia and industrial applications
  Fujiang Lin, University of Science and Technology of China (USTC), China

Special OpenPDK Session progeam include the panel discussion: 

How to have a close loop for PDK, EDA, PDA and ICS simulation?

[ read more...]

[conference] ELECTRONICS 2026 at KTU Kaunas

International Conference ELECTRONICS 2026

From SMT to Advanced Packaging – Manufacturing Meets Microinterconnects

KTU Kaunas, Lithuania

12–13 November 2026

Conference Vision : A joint platform connecting SMT engineers, advanced packaging researchers, reliability specialists, and industry to build a shared technical language, bridge research and manufacturing, and grow German-Baltic collaboration around heterogeneous integration and microinterconnects. Organized by Kaunas University of Technology, the conference serves as a platform for collaboration and discussion among representatives from academy, industry, and business.

Partners:
TUD IAFT (Dresden University of Technology, Institute of Electronic Packaging Technology)
IHP (IHP GmbH, Leibniz Institute for High Performance Microelectronics)
Industry Partners: FINETECH, TELTONIKA, etc.

Conference Program Online <https://eef.ktu.edu/events/electronics2026/>

Conference Organzation Committee:

General Chair

Prof., Dr. Mindaugas ŽILYS, KTU Kaunas

Executive Chair

Dr. Agata ROMANOVA, KTU Kaunas

Co-Chairs

Prof., Dr. Algimantas VALINEVIČIUS, KTU Kaunas

Prof., Dr. Darius ANDRIUKAITIS, KTU Kaunas

Prof., Dr. Dangirutis NAVIKAS, KTU Kaunas

Schematic to Silicon with Mini MOSbius

Zero To ASIC Course and Tiny Tapeout by Matt Venn

Schematic to Silicon with Mini MOSbius 

https://www.youtube.com/watch?v=NM5cLWYWqG0

Take Matt Venn TT course: 

https://www.zerotoasiccourse.com/

Buy a copy of Mini MOSbius, part of the TT IP library, here: 

https://store.tinytapeout.com/products/TTSKY25b-Development-Kit-p849160072

Check the configurator: 

https://github.com/mattvenn/mini-mosbius-configurator

Mini MOSbius is available on these chips

• [OK] TTSKY25a - delivered July 2026 - available in the store
• [OK] TTSKY25b - delivered August 2026 - available in the store
• TTSKY26b - tapeout May 2026
• TTSKY26c - tapeout September 2026
• GF180 - will be taped out December 2026

and finally check out the original MOSBius: https://mosbius.org/ If you are interested to acquire MOSbius kits, review the express license and email Peter Kinget for kit availability before placing an order.