Jan 11, 2025

[paper] Optoelectronic device library containing multiple Verilog-A models

Guanliang Chen, Zhigang Song and Xinhe Zheng
Optoelectronic device library containing multiple Verilog-A models
Sci Rep 15, 1115 (2025) doi: 10.1038/s41598-024-80150-6

1 Key Laboratory of Solid-State Optoelectronics Information Technology, Institute of Semiconductors, Chinese Academy of Sciences, Beijing, 100083, China
2 Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing, 100049, China
3 School of Mathematics and Physics, Beijing Key Laboratory for Magneto-Photoelectrical Composite and Interface Science, University of Science and Technology Beijing, Beijing, 100083, China

Abstract: The advancement of the optoelectronic fusion industry has escalated the demands for optoelectronic simulation, yet a comprehensive model library remains unavailable for chip designers. We have utilized the hardware description language Verilog-A to develop an extensive optoelectronic device model library, featuring a full range of device types, unified interfaces, and the capability to simulate the physical effects of devices. Establishing this model library is intended to alleviate the workload of chip designers and reduce development costs.

TAB: Comparison with Verilog-A model library and others

FIG: Schematic diagram of a compact Verilog-A model of VCSEL and its DC test results



Jan 9, 2025

[mos-ak] [Online Publications] 17th International MOS-AK Workshop Silicon Valley, December 11, 2024

image.png
17th International MOS-AK Workshop 
Silicon Valley, December 11, 2024
   
Online MOS-AK Workshop Publications

The 17th International MOS-AK Workshop on Compact/SPICE Modeling was held online on Dec.11, 2024, in the timeframe of IEDM and Q4 CMC Meetings with Keysight Technologies organization support. The MOS-AK workshop publications [1-9], with individually assigned DOI numbers, are available online:

-- W.Grabinski on the behalf of International MOS-AK Committee
REF:
[1] L. Ma, "What's New in Keysight Device Modeling 2025", presented at the 17th International MOS-AK Workshop (MOS-AK), Remote/Online Silicon Valley, Dec. 11, 2024. doi: 10.5281/zenodo.14621746
[2] P. M. Lee, "Si2 Compact Model Coalition", presented at the 17th International MOS-AK Workshop (MOS-AK), Remote/Online Silicon Valley, Dec. 11, 2024. doi: 10.5281/zenodo.14621935.
[3] Á. Bűrmen, "OpenVAF - status update, ecosystem, and a roadmap", presented at the 17th International MOS-AK Workshop (MOS-AK), Remote/Online Silicon Valley, Dec. 11, 2024. doi: 10.5281/zenodo.14622027.
[4] H. Agarwal and G. Pahwa, "A Wrapper Model for ESD-FET Simulation and Analysis", presented at the 17th International MOS-AK Workshop (MOS-AK), Remote/Online Silicon Valley, Dec. 11, 2024. doi: 10.5281/zenodo.14622109.
[5] T. R. Ratier, J.-C. Delvenne, D. Flandre, L. Van Brandt, "Compact Modelling of Memristors Toward Analog Neuromorphic Circuit Simulations", presented at the 17th International MOS-AK Workshop (MOS-AK), Remote/Online Silicon Valley, Dec. 11, 2024. doi: 10.5281/zenodo.14623688.
[6] H. Dias Gilo, I. Alves Salesand, F. de Assis Brito Filho, "Inductor Modeling and Generation Flow for Verified RFIC Layouts Using Open-Source PDKs", presented at the 17th International MOS-AK Workshop (MOS-AK), Remote/Line Silicon Valley, Dec. 11, 2024. doi: 10.5281/zenodo.14624239.
[7] Q. Chen, V. Kilchytska, E. Bestelink, R. A. Sporea, D. Flandre, L. Van Brandt, "Characterization and modelling of low-frequency noise in polysilicon thin-film source-gated transistors from subthreshold to saturation", presented at the 17th International MOS-AK Workshop (MOS-AK), Remote/Online Silicon Valley, Dec. 11, 2024. doi: 10.5281/zenodo.14624309.
[8] B. Murmann, "Gm/ID-Based Analog Circuit Sizing Using Ngspice and Python", presented at the 17th International MOS-AK Workshop (MOS-AK), Remote/Online Silicon Valley, Dec. 11, 2024. doi: 10.5281/zenodo.14624372.
[9] Roberto Murphy, "Semiconductor R&D in Mexico" presented at the 17th International MOS-AK Workshop (MOS-AK), Remote/Online Silicon Valley, Dec. 11, 2024. doi:10.5281/zenodo.14529798
WG090125

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Jan 7, 2025

[paper] MOSFET-Based Voltage Reference Circuits

Moisello, Elisabetta, Edoardo Bonizzoni, and Piero Malcovati
MOSFET-Based Voltage Reference Circuits in the Last Decade: A Review
Micromachines 15, no. 12 (2024): 1504

Abstract: Voltage reference circuits are a basic building block in most integrated microsystems, covering a wide spectrum of applications. Hence, they constitute a subject of great interest for the entire microelectronics community. MOSFET-based solutions, in particular, have emerged as the implementation of choice for realizing voltage reference circuits, given the supply voltage scaling and the ever-lower power consumption specifications in various applications. For these reasons, this paper aims to review MOSFET-based voltage reference circuits, illustrating their principles of operation, as well as presenting a detailed overview of the state-of-the-art, in order to paint an accurate picture of the encountered challenges and proposed solutions found in the field in the last decade, thus providing a starting point for future research in the field.

FIG: Schematic of a generic threshold voltage-based MOSFET reference circuit
and graphical representation of a transistor ZTC point.

Jan 6, 2025

SSCS PICO Chronicle

Mirjana Videnovic-Misic, Harald Pretl, Ali Sabir, Zonghao (Chris) Li, 
and Sadayuki Yoshitomi
SSCS PICO Chronicles: news from the open source community
Date of current version: 14 November 2023
DOI: 10.1109/MSSC.2023.3315888

The Growing Activity of Open Source Chip Design in Japan

The Chipathon 2023 Team Japan consists of 12 volunteers from industry and academia. Since the team members are located in different parts of Japan, the team will be working remotely to design the project. On 4 August, they held a kickoff meeting where the members, who had been working together on Slack, gathered for the first time in person. Although many of the team members have no tape-out experience, they are all truly interested in IC design. The leader of Team Japan is Prof. Akira Tsuchiya at the University of Shiga in Japan (FIG).

Prof. Tsuchiya has been working on open source IC design and has been a volunteer member of the SSCS Chipathon since October 2022. He has promoted open source IC design and SSCS PICO activities in Japan. He held several hands-on events, for example, at the summer camp of the IE- ICE ICD in 2022. Also, he gave several talks about open source IC design and his research on analog synthesis in domestic conferences. And now, he has recruited members and applied to the latest Chipathon. Let’s look forward to the activities of the new members of “Team Japan.”

FIG: Prof. Akira Tsuchiya, an associate professor of the University of Shiga prefecture, 
Japan, and a snapshot of the kickoff meeting (hybrid) of the Chipathon 2023 Japan team





Dec 29, 2024

[C4P] MIEL 2025

34th IEEE International Conference on Microelectronics 
Niš, Serbia, Oct. 13-16, 2025
Organized by

Serbian Ministry of Science, Technological Development 

and Innovation Society for ETRAN

Abstracts Submission
The authors of contributed papers are expected to submit two-page extended abstracts (including figures, tables, and references) that will serve for the paper selection. A cover page of the abstract should include the paper title, authors, and complete address (including fax and e-mail) of the author to be contacted. The abstracts can be submitted in electronic form (either MS Word, PDF, or PostScript files) via E-mail sent to Conference Secretariat (miel@elfak.ni.ac.rs) by April 25th, 2025. Also, the abstracts can be submitted via System for manuscript submission.

Review Process
Only abstracts that have not been previously published at the time of the conference will be considered. Peer review refers to the evaluation and assessment of submitted two-page extended abstracts by experts in the field of microelectronic devices, circuits, and systems. Note that the most frequent cause of rejection of submitted two-page extended abstracts is lack of new results.

Important Dates
Note for Authors
Extended versions of selected papers from MIEL 2025 Conference will be published (after the regular review process) in:
Programme Committee Chairman
Danijel Danković; Faculty of Electronic Engineering, University of Niš
Vojkan Davidović; Faculty of Electronic Engineering, University of Niš

Contact details:
Faculty of Electronic Engineering, Uni. Nis
Aleksandra Medvedeva 14, 18000 Nis, Serbia
phone: +381 18 529 325, +381 18 529 326
fax: +381 18 588 399