[paper] FDSOI Threshold Voltage Model

Hung-Chi Han1, (Student, IEEE), Zhixing Zhao2, Steffen Lehmann2,

Edoardo Charbon1, (Fellow, IEEE), and Christian Enz1 (Life Fellow, IEEE)

Novel Approach to FDSOI Threshold Voltage Model Validated at Cryogenic Temperatures

in IEEE Access, DOI: 10.1109/ACCESS.2023.3283298

1 Ecole Polytechnique Fédérale de Lausanne (EPFL), 2000 Neuchâtel, Switzerland
2 GlobalFoundries, 01109 Dresden, Germany

Abstract: The paper presents a novel approach to to the modeling of the back-gate dependence of the threshold voltage of Fully Depleted Silicon-On-Insulator (FDSOI) MOSFETs down to cryogenic temperatures by using slope factors with a gate coupling effect. The FDSOI technology is well-known for its capability to modulate the threshold voltage efficiently by the back-gate voltage. The proposed model analytically demonstrates the threshold voltage as a function of the back-gate voltage without the pre-defined threshold condition, and it requires only a calibration point, i.e., a threshold voltage with the corresponding back-gate voltage, front- and back-gate slope factors, and work functions of front and back gates. The model has been validated over a wide range of the back-gate voltages at room temperature and down to 3 K. It is suitable for optimizing low-power circuits at cryogenic temperatures for quantum computing applications

FIG: Room temperature back-gate coefficient η versus VT−VB for an n-type conventional well (RVT) FDSOI FET with 1 µm of gate length and width. The θ=0 happens at VT−VB = −0.63V due to −0.63V of the front-back gate work function difference 

Acknowledgment: The authors would like to thank Claudia Kretzschmar from GlobalFoundries Germany and GlobalFoundries University Partnership Program for providing 22 FDX® test structures and support. Hung-Chi Han would like to thank Davide Braga from Fermi National Accelerator Laboratory for his valuable support. This project has received funding from the European Union’s Horizon 2020 Research & Innovation Program under grant agreement No. 871764. SEQUENCE.

[paper] Vacuum Electron Devices

R. Lawrence Ives, Life Senior Member, IEEE

Advanced Fabrication of Vacuum Electron Devices

(Invited Paper)

IEEE TED, Vol. 70, No. 6, June 2023

DOI: 10.1109/TED.2023.3268629

Abstract: RF source scientist and engineers continuously push the envelope with new designs, striving for improved performance with higher efficiency, higher frequency, greater bandwidth, increased gain, smaller size, lower voltage, and myriad other parameters required for ever more demanding applications. Invariably, it becomes more challenging to achieve the required fabrication and assembly performance with increasing complexity and precision. This publication reviews recent development on advanced fabrication technologies and describes the current state of the art in machining, assembly, and alignment capabilities.

FIG: Assembled 11.4-GHz accelerating structure assembled with elastic averaging

Acknowledgment: Several people assisted with this article, and the author would like to acknowledge their contributions. These include Jeff Herman at Ron Witherspoon, Inc., Colin Joye at the Naval Research Laboratory, Daniel Busbaher at 3M Technical Ceramics, Diana Gamzina at Elvespeed, Emma Snively at SLAC National Accelerator Laboratory, and Philipp Borchard at Dymenso. The author would like to thank RWI for access to their facilities to see their micro-CNC and software capabilities in operation.

[paper] Microchips for Memristive Applications

Kaichen Zhu, Sebastian Pazos, Fernando Aguirre, Yaqing Shen, Yue Yuan, Wenwen Zheng, Osamah Alharbi, Marco A. Villena, Bin Fang, Xinyi Li, Alessandro Milozzi, Matteo Farronato, Miguel Muñoz-Rojo, Tao Wang, Ren Li, Hossein Fariborzi, Juan B. Roldan, Guenther Benstetter, Xixiang Zhang, Husam N. Alshareef, Tibor Grasser, Huaqiang Wu, Daniele Ielmini & Mario Lanza 

Hybrid 2D–CMOS microchips for memristive applications

Nature 618, 57–62 (2023)

DOI: 10.1038/s41586-023-05973-1

Abstract: Exploiting the excellent electronic properties of two-dimensional (2D) materials to fabricate advanced electronic circuits is a major goal for the semiconductor industry1,2. However, most studies in this field have been limited to the fabrication and characterization of isolated large (more than 1 µm2) devices on unfunctional SiO2–Si substrates. Some studies have integrated monolayer graphene on silicon microchips as a large-area (more than 500 µm2) interconnection3 and as a channel of large transistors (roughly 16.5 µm2) (refs. 4,5), but in all cases the integration density was low, no computation was demonstrated and manipulating monolayer 2D materials was challenging because native pinholes and cracks during transfer increase variability and reduce yield. Here, we present the fabrication of high-integration-density 2D–CMOS hybrid microchips for memristive applications—CMOS stands for complementary metal–oxide–semiconductor. We transfer a sheet of multilayer hexagonal boron nitride onto the back-end-of-line interconnections of silicon microchips containing CMOS transistors of the 180 nm node, and finalize the circuits by patterning the top electrodes and interconnections. The CMOS transistors provide outstanding control over the currents across the hexagonal boron nitride memristors, which allows us to achieve endurances of roughly 5 million cycles in memristors as small as 0.053 µm2. We demonstrate in-memory computation by constructing logic gates, and measure spike-timing dependent plasticity signals that are suitable for the implementation of spiking neural networks. The high performance and the relatively-high technology readiness level achieved represent a notable advance towards the integration of 2D materials in microelectronic products and memristive applications.

FIG: Structure of the considered SNN. Each MNIST image is reshaped as a 784x1 column vector, and the intensity of the pixels is encoded in terms of the firing frequency of the input neurons. The only trainable synapses are those connecting the input layer with the excitatory layer, and they are modelled with the STDP characteristic of the CMOS-h-BN based 1T1M cells. The learning is unsupervised, and the neurons are labelled only after the training. These label-neuron assignments are then feed to the decision block altogether with the firing patterns of the neurons, to infer the class of the image presented in the input. 

Acknowledgements: This work has been supported by the Ministry of Science and Technology of China (grant nos. 2019YFE0124200 and 2018YFE0100800), the National Natural Science Foundation of China (grant no. 61874075) and the Baseline funding scheme of the King Abdullah University of Science and Technology.

[Workshop] Open Source PDKs and EDA

 Workshop 1: Open Source PDKs and EDAs, 

Community Experiences toward Democratization of Chip Design

RIHGA Royal Hotel Kyoto, Horikawa Shiokoji, Shimogyo ku, Kyoto 600 8237, Japan.

Date & Time: 5:30pm.-7:15pm on June 11 (Sun), 2023

Since its launch in 2020, the Open MPW shuttle program has received over 500 project submissions spanning 9 shuttles. This workshop will explore various topics related to designers' experiences, including measured results, foundry perspectives, and governmental expectations.

Organizers: 

• Makoto Ikeda (The University of Tokyo)
• Mehdi Saligane (University of Michigan)

Program:

1. Design experience: “The Journey of Two Novice LSI Enthusiasts: Tape-Out of CPU+RAM in Just One Month”, Kazuhide Uchiyama, University of Electro-Communications and Yuki Azuma, University of Tsukuba
2. From Zero to 1000 Open Source Custom Designs in Two Years, Mohamed Kassem, Co-founder and CTO, Efabless
3. The SKY130 Open Source PDK: Building an Open Source Innovation Ecosystem, Steve Kosier, Skywater technology
4. Open Source Chip Design on GF180MCU – A foundry perspective, Karthik Chandrasekaran, Global Foundries
5. Japan Foundries' Perspectives on Silicon design democratization, Shiro Hara, Minimal Fab & AIST
6. Google's perspective on Open source PDKs, Open source EDA tools, and OpenMPW shuttle program, Johan Euphrosine and Tim Ansell, Google
7. The Nanofabrication Accelerator Project, Matthew Daniels, NIST
8. Japanese government perspective on Silicon design democratization, Yohei Ogino, The Ministry of Economy, Trade and Industry METI

VLSI Symposium Workshop1 "Open Source PDKs and EDA" Audience

[book] Tunneling Field Effect Transistors

Tunneling Field Effect Transistors
Design, Modeling and Applications

Edited By T. S. Arun Samuel, Young Suh Song, Shubham Tayal, P. Vimala, Shiromani Balmukund Rahi

ISBN 9781032348766
1st Edition; 316 Pages; 15 Color & 232 B/W Illustrations
June 8, 2023 by CRC Press

Description: This book will give insight into emerging semiconductor devices from their applications in electronic circuits, which form the backbone of electronic equipment. It provides desired exposure to the ever-growing field of low-power electronic devices and their applications in nanoscale devices, memory design, and biosensing applications.

Tunneling Field Effect Transistors: Design, Modeling and Applications brings researchers and engineers from various disciplines of the VLSI domain to together tackle the emerging challenges in the field of nanoelectronics and applications of advanced low-power devices. The book begins by discussing the challenges of conventional CMOS technology from the perspective of low-power applications, and it also reviews the basic science and developments of subthreshold swing technology and recent advancements in the field. The authors discuss the impact of semiconductor materials and architecture designs on TFET devices and the performance and usage of FET devices in various domains such as nanoelectronics, Memory Devices, and biosensing applications. They also cover a variety of FET devices, such as MOSFETs and TFETs, with various structures based on the tunneling transport phenomenon.

The contents of the book have been designed and arranged in such a way that Electrical Engineering students, researchers in the field of nanodevices and device-circuit codesign, as well as industry professionals working in the domain of semiconductor devices, will find the material useful and easy to follow.

Table of Contents:

Chapter 1. Challenges of Conventional Cmos Technology in Perspective of Low Power Applications

Chapter 2. Basic Science and Development of Subthreshold Swing Technology

Chapter 3. Historical Development of MOS technology to Tunnel FETs

Chapter 4. Modeling of Gate Engineered TFETs: Challenges and Opportunities

Chapter 5. Modeling of Gate Engineered TFET: challenges and Opportunities.

Chapter 6. Evolution of Heterojunction Tunnel Field Effect Transistor and its Advantages

Chapter 7. Analog / RF performance analysis of TFET device

Chapter 8. DC Analysis and Analog/HF Performances of GAA-TFET with Dielectric Pocket

Chapter 9. Investigation on Ambipolar Current Suppression in Tunnel FETs

Chapter 10. Analysis of Channel Doping Variation on Transfer Characteristics to High Frequency performance of F-TFET

Chapter 11. Design of Nanotube TFET Biosensor

Chapter 12. TFET-based Memory Cell Design with Top-down Approach

Chapter 13. Designing of nonvolatile memories utilizing Tunnel Field Effect Transistor

Chapter 14. TFET-based Universal

Chapter 15. TFET-based Level Shifter Circuits for Low Power Applications