Apr 19, 2021

[Photos] MOS-AK LADEC Mexico April 18, 2021

Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
MOS-AK LAEDC Workshop
(virtual/online) April 18, 2021

Together with local Host and LAEDC Organizers as well as all the Extended MOS-AK TPC Committee, we have organized the 3rd subsequent MOS-AK/LAEDC workshop which was the Virtual/Online event. There are a couple of the event photos:

MOS-AK Session 1 (APR.18) begun: 8:00am Mexico time zone (GMT-5)

T_1 FOSSEE eSIM: An open source CAD software for circuit simulation
Kannan Moudgalya
IIT Bombay (IN)

T_2 Memristor modeling
Arturo Sarmiento
INAOE (MX)

T_3 Modeling Issues for CMOS RF ICs
Roberto Murphy, Jose Valdes and Reydezel Torres
INAOE (MX)

T_4 Improving Time-Dependent Gate Breakdown of GaN HEMTs with p-type Gate
E. Sangiorgi, A. Tallarico, N. Posthuma, S. Decoutere, C. Fiegna
Universita di Bologna

MOS-AK Session 2 (APR.18) begun: 1:00pm Mexico time zone (GMT-5)

T_5 Compact Models of SiC and GaN Power Devices
Alan Mantooth, Arman Ur Rashid, Md Maksudul Hossain
University of Arkansas (US)

T_6 New analytical model for AOSTFTs
Antonio Cerdeira
CINVESTAV-IPN, Mexico City (MX)

T_7 On the Parameter Extraction of Thin-Film Transistors in Weak-Conduction
Adelmo Ortiz-Conde
Solid State Electronics Laboratory, Simon Bolivar University, Caracas (VE)

End of MOS-AK Workshop
Group Photo






[ECE Seminar] #GLOBALFOUNDRIES #22nm# FDSOI: Enabling Long Battery Life and Unmatched RF Integration in IOT Systems-on-Chip https://t.co/50X0K1cML2 #semi https://t.co/aCgqVU4SF4



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April 19, 2021 at 10:17AM
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Apr 16, 2021

More #wafer #fabs in the #US – When, how? #Intel’s Ocotillo facility in Arizona will be the site where the company will build two new fabs to increase #semi manufacturing capacity in the U.S. [Intel / Electronics360 https://t.co/sBVxQfKqjR] https://t.co/RMYWXx4ZAD



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April 16, 2021 at 08:33PM
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Think tank - Stiftung Neue Verantwortung (SNV) : rejuvenate #European #IC design before building a #fab [Bits&Chips https://t.co/9jc6XZ9kJV] #semi https://t.co/3Lj94gk8zn



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April 16, 2021 at 11:23AM
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SEL-Silvaco unite to develop #SPICE #CAAC-#IGZO model of oxide semiconductor #FET https://t.co/PjLR4Wm5jX #semi https://t.co/SQJBlzllOi



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April 16, 2021 at 10:19AM
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Apr 15, 2021

[paper] GaN-HEMT Compact Model

Ke Li1, Paul Leonard Evans2, Christopher Mark Johnson2, Arnaud Videt3, and Nadir Idir3
A GaN-HEMT Compact Model Including Dynamic RDSon Effect
for Power Electronics Converters
MDPI Energies 2021, 14, 2092.
DOI: 10.3390/en14082092

1 Centre for Advanced Low-Carbon Propulsion Systems, Coventry University, Coventry CV1 2TL, UK
2 Power Electronics, Machines and Control Group, University of Nottingham, Nottingham NG7 2RD, UK;
3 Laboratoire d’Electrotechnique et d’Electronique de Puissance, Université de Lille, France;


Abstract: In order to model GaN-HEMT switching transients and determine power losses, a compact model including dynamic RDSon effect is proposed herein. The model includes mathematical equations to represent device static and capacitance-voltage characteristics, and a behavioural voltage source, which includes multiple RC units to represent different time constants for trapping and detrapping effect from 100 ns to 100 s range. All the required parameters in the model can be obtained by fitting method using a datasheet or experimental characterisation results. The model is then implemented into our developed virtual prototyping software, where the device compact model is co-simulated with a parasitic inductance physical model to obtain the switching waveform. As model order reduction is applied in our software to resolve physical model, the device switching current and voltage waveform can be obtained in the range of minutes. By comparison with experimental measurements, the model is validated to accurately represent device switching transients as well as their spectrum in frequency domain until 100 MHz. In terms of dynamic RDSon value, the mismatch between the model and experimental results is within 10% under different power converter operation conditions in terms of switching frequencies and duty cycles, so designers can use this model to accurately obtain GaN-HEMT power losses due to trapping and detrapping effects for power electronics converters.
Fig: GaN-HEMT device structure and its compact model

Acknowledgments: The authors would like to acknowledge Loris Pace for technical discussions and experimental support. This research was funded by the UK Engineering and Physical Sciences Research Council (EPSRC) through research grant [EP/K035304/1 and EP/R004390/1] and French State Region Plan Contract Intelligent Integrated Energy Converter (CPER-CE2I) project.

#RaspberryPi4 owners can now train their own custom models using Edge Impulse's cloud-based development platform for #machine #learning on edge devices https://t.co/Ge30t4tdmN #semi https://t.co/baPQdajRrk



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April 15, 2021 at 10:39AM
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Apr 13, 2021

[mos-ak] [Final Program] 3rd MOS-AK LAEDC Workshop (virtual/online) April 18, 2021

Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
MOS-AK LAEDC Workshop
(virtual/online) April 18, 2021

Together with local Host and LAEDC Organizers as well as all the Extended MOS-AK TPC Committee, we have the pleasure to invite to the 3rd subsequent MOS-AK/LAEDC workshop which will be Virtual/Online event. Scheduled, MOS-AK/LAEDC workshop, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors.

The MOS-AK workshop program is available online: 
https://www.mos-ak.org/mexico_2021/

Venue: Virtual/Online MOS-AK Workshop - APRIL 18, 2021
  • Session 1 (APR.18) begins: 8:00am Mexico time zone (GMT-5)
  • Session 2 (APR.18) begins: 1:00pm Mexico time zone (GMT-5)
Online Free Registration is open, now:
https://forms.gle/PQgZk9td3Jeb4MWZ9
Registered participants will receive online meeting invitation 24h before the event. Any related enquiries can be sent to <wladek@mos-ak.org>

Postworkshop Publications: Selected best MOS-AK technical presentation will be recommended for further publication in a special Solid State Electronics (SSE) issue on compact modeling.

W.Grabinski on the behalf of International MOS-AK Committee
WG13042021

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[paper] Performance limits of hBN as an insulator for scaled CMOS

Theresia Knobloch1, Yury Yu. Illarionov1,2, Fabian Ducry3, Christian Schleich4, Stefan Wachter5, Kenji Watanabe6, Takashi Taniguchi7, Thomas Mueller5, Michael Waltl4, Mario Lanza8, Mikhail I. Vexler2, Mathieu Luisier3 and Tibor Grasser1
The performance limits of hexagonal boron nitride as an insulator for scaled CMOS devices based on two-dimensional materials
Nature Electronics; Vol 4; Feb.2021; pp.98–108;
DOI: 10.1038/s41928-020-00529-x

1. Institute for Microelectronics, TU Wien, Vienna, Austria.
2. Ioffe Institute, St Petersburg, Russia.
3. Integrated Systems Laboratory, ETH Zürich, Zurich, Switzerland.
4. Christian Doppler Laboratory for Single-Defect Spectroscopy in Semiconductor Devices at the Institute for Microelectronics, TU Wien, Vienna, Austria.
5. Institute for Photonics, TU Wien, Vienna, Austria.
6. Research Center for Functional Materials, National Institute for Matierals Science, Tsukuba, Japan.
7. International Center for Materials Nanoarchitectonics, National Institute for Materials Science, Tsukuba, Japan.
8. Physical Sciences and Engineering Division, King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi Arabia.


Abstract: Complementary metal–oxide–semiconductor (CMOS) logic circuits at their ultimate scaling limits place extreme demands on the properties of all materials involved. The requirements for semiconductors are well explored and could possibly be satisfied by a number of layered two-dimensional (2D) materials, such as transition metal dichalcogenides or black phosphorus. The requirements for gate insulators are arguably even more challenging. At present, hexagonal boron nitride (hBN) is the most common 2D insulator and is widely considered to be the most promising gate insulator in 2D material-based transistors. Here we assess the material parameters and performance limits of hBN. We compare experimental and theoretical tunnel currents through ultrathin layers (equivalent oxide thickness of less than 1 nm) of hBN and other 2D gate insulators, including the ideal case of defect-free hBN. Though its properties make hBN a candidate for many applications in 2D nanoelectronics, excessive leakage currents lead us to conclude that hBN is unlikely to be suitable for use as a gate insulator in ultrascaled CMOS devices.
Fig: Comparison of gate insulators for ultrascaled CMOS devices based on 2D materials. a.) Currents at constant EOT for 3D oxides and layered insulators. The leakage currents as calculated with the Tsu–Esaki model are given for 3D amorphous oxide and 2D layered insulators at a constant thickness of EOT=0.76nm. If no tunnel masses were known, the free-electron mass was used. The filled circles indicate the results of ab initio calculations and the dotted line connecting the circles is a guide to the eye. b.) Currents at constant EOT for native oxides and fluorides. The leakage currents are given for native oxides and ionic fluorides at a constant thickness of EOT=0.76nm.

Acknowledgements: T.K., Y.Y.I. and T.G. acknowledge the financial support through FWF grant numbers I2606-N30, I4123-N30 and P29119-N35. Y.Y.I. and M.I.V. acknowledge financial support by the Ministry of Science and Higher Education of the Russian Federation under project number 075-15-2020-790. F.D. and M. Luisier thank CSCS for giving them access to the Piz Daint supercomputer under project number s876. C.S. and M.W. gratefully acknowledge financial support by the Austrian Federal Ministry for Digital and Economic Affairs and the National Foundation for Research, Technology and Development and the Christian Doppler Research Association. The computational results presented have been achieved in part using the Vienna Scientific Cluster (VSC). S.W. and T.M. acknowledge financial support through the Graphene Flagship number 785219 and number 881603. K.W. and T.T. acknowledge support from the Elemental Strategy Initiative conducted by the MEXT, Japan, number JPMXP0112101001, JSPS KAKENHI grant number JP20H00354 and the CREST(JPMJCR15F3), JST. M. Lanza acknowledges support from the Ministry of Science and Technology of China (grant numbers 2018YFE0100800, 2019YFE0124200) and the National Natural Science Foundation of China (grant number 61874075).

[papers] Compact Modeling

[1] Zhang, Yuanke, Tengteng Lu, Wenjie Wang, Yujing Zhang, Jun Xu, Chao Luo, and Guoping Guo. "Characterization and Modeling of Native MOSFETs Down to 4.2 K." arXiv:2104.03094 (2021).

Abstract: The extremely low threshold voltage (VTH) of native MOSFETs (VTH≈0 V @ 300 K) is conducive to the design of cryogenic circuits. Previous research on cryogenic MOSFETs mainly focused on the standard threshold voltage (SVT) and low threshold voltage (LVT) MOSFETs. In this paper, we characterize native MOSFETs within the temperature range from 300 K to 4.2 K. The cryogenic VTH increases up to ∼0.25 V (W/L = 10 µm/10 µm) and the improved subthreshold swing (SS) ≈ 14.30 mV/dec @ 4.2 K. The off-state current (IOFF) and the gate-induced drain leakage (GIDL) effect are ameliorated greatly. The step-up effect caused by the substrate charge and the transconductance peak effect caused by the energy quantization in different subbands are also discussed. Based on the EKV model, we modified the mobility calculation equations and proposed a compact model of large size native MOSFETs suitable for the range of 300 K to 4.2 K. The mobility-related parameters are extracted via a machine learning approach and the temperature dependences of the scattering mechanisms are analyzed. This work is beneficial to both the research on cryogenic MOSFETs modeling and the design of cryogenic CMOS circuits for quantum chips.
Fig: I-V curves of native MOSFETs with W/L= 10/10µm measured (symbol) and calculated (solid line) at various temperatures. (a) Acomparison of the calculation results between this model and the  EKV2.6 model at 77K and 4.2K. (b) Measurement and calculation results of  the output characteristic at 4.2 K.

[2] Qixu Xie  Guoyong Shi; An analytical gm/ID‐based harmonic distortion prediction method for multistage operational amplifiers; Int J Circ Theor Appl. 2021; 1– 27. DOI: 10.1002/cta.3012

Abstract: An analytical stage‐based harmonic distortion (HD) analysis method for multistage operational amplifiers (Op Amps) is developed in this work. This work contributes two fundamental methods that make the analytical HD prediction possible at the circuit level. Firstly, we propose that the traditionally used first order small‐signal transistor quantities gm (transconductance) and go (output conductance) in the gm/ID design methodology for bulk complementary metal‐oxide‐semiconductor (CMOS) technology can be extended to the higher order quantities gm(k) and go(k) (k=1,2,3). With proper normalization, these quantities become neutral to the device dimensions and operation currents, hence can be precharacterized by sweeping simulations and used as lookup tables. Secondly, we further develop analytical nonlinearity expressions for a set of commonly used amplifier stages, represented as the functions of the nonlinearity parameters gm(k) and go(k) of the transistors that form a stage circuit. A combination of these two fundamental methods on hierarchical nonlinearity modeling enables us to apply the existing analytical HD estimation methods for the stage‐form macromodels to predict the circuit‐level HD behavior, overcoming the need of running repeated simulations under device resizing and rebiasing. The proposed harmonic distortion analysis method has been validated by application to real multistage amplifiers, achieving HD prediction results in excellent agreement to fully transistor‐level circuit simulation results but with substantial speedup.

Apr 12, 2021

White House to zero in on #chip shortage in meeting with company officials



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April 12, 2021 at 05:22PM
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[Neal Freyman] Chips Wanted



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April 12, 2021 at 01:58PM
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The lack of #semi manufacturing in #Europe



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April 12, 2021 at 12:05PM
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[euresearch.ch] Are you ready for the ERC?

 
 
In Focus: Are you ready for the ERC?
 

Horizon Europe will fully take off in a few weeks but the first ERC calls are already out. Typical ERC, you could say, always at the forefront of the Framework Programmes. The next ERC call, the Advanced Grant, is expected to open on 20 May with a deadline on 31 August. What are your ERC plans?

 

2021 is a special year for the ERC: It was not possible for the first calls to open in 2020 and there are no Synergy Grant or Proof of Concept Grant calls in the 2021 Work Programme. These two calls are expected back in the 2022 Work Programme. The Proof of Concept will even have 2 calls with a total of 4 cut-off dates, giving PIs for whom 2021 would have been the last chance to apply the possibility to submit a proposal. These plans as well as tentative opening and closing dates for the other calls were recently communicated by the ERC. In terms of call timelines, 2022 will be the last transition year. With Work Programme 2023, calls are expected to be back to the usual schedule (i.e. Starting Grant closing around October, Consolidator Grant in February, Advanced Grant in summer, and Synergy Grant in November).

Make sure you consider the best time in your career for a proposal submission and schedule in sufficient time for proposal writing. For Starting and Consolidator Grant applicants, it is not necessarily towards the end of the eligibility window. Statistics show that the success rate does not increase substantially with additional years post PhD. To get started, talk with ERC grantees and your peers, and check out the "ERC classes" videos.

Dear readers, these are my last recommendations as a National Contact Point for ERC. After 14 years, I am leaving Euresearch and taking off for new horizons. It was a great pleasure for me to support so many ERC applicants in Switzerland. To work with talented researchers and to see world class research projects develop was truly inspiring. Thank you for your trust and good luck with your ERC plans!

Katja Wirth, National Contact Point for ERC / Member of the Euresearch Management Board

Alexandra Rosakis, Illustration

Impressum
 
Euresearch Communication, com@euresearch.ch
Euresearch, Belpstrasse 11, CH-3007 Bern, Tel +41 31 380 60 00

Disclaimer: We assume no responsibility for the content, accuracy, timeliness, reliability or completeness of the information, nor for references and links to third-party websites.© 2021 Euresearch


                                                           

[C4P] IEEE NMDC 2021 - abstracts due 15-April


16th IEEE Nanotechnology Materials and Devices Conference

October 17th to 20th, 2021 | Vancouver, BC, Canada


Website: https://ieeenmdc.org/nmdc-2021
CALL for PAPERS (download PDF)

Short Abstract (text only) Submission Deadline: April 15, 2021


The IEEE Nanotechnology Council is pleased announce the First Call for Papers for the 16th IEEE Nanotechnology Materials and Devices Conference (IEEE NMDC 2021) which will be co-located with the IEEE Conference on Electrical Insulation and Dielectric Phenomena (IEEE CEIDP) sponsored by the IEEE Dielectrics and Electrical Insulation Society (DEIS). 

Recognizing that plans for this in-person conference could be affected by circumstances related to COVID-19, updates will be provided at IEEE NMDC 2021.

Important Dates:

Special Session and Workshop/Tutorial Proposals Deadline: March 31, 2021
Short Abstract (text only) Submission Deadline: April 15, 2021
Regular, Special Session and Invited Papers Submission Deadline: May 31, 2021 
Late Breaking News Extended Abstract Submission Deadline: August 10, 2021

See the Call for Papers page here.
 

Information for Authors including Submission Instructions and requirements can be found on these pages.


Message sent to IEEE Nanotechnology Council interest list.

Copyright © 2021 IEEE Nanotechnology Council 

Apr 9, 2021

RT: 16bit CPU for the HP 9825 computer

Apr 7, 2021

#Cycling is ten times more important than electric cars for reaching #net-zero cities https://t.co/0Rxbm2Ygt1 #semi https://t.co/lrtHaI1u4N



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April 07, 2021 at 09:28PM
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[papers] compact modeling

Rabnawaz Sarmad Uqaili, Faraz Bashir Soomro, Junaid Ahmed Uqaili, Ahsin Murtaza Bughio 
and Khalid Ali Khan
Study on Compact Equivalent Circuit Model for RF CMOS Transistor 
International Journal of Scientific & Technology Research 
Vol.10, Issue 02, February 2021 ISSN 2277-8616

Abstract: In this study, a physical-based radio-frequency (RF) compact equivalent circuit model (CECM) for complementary metal-oxidesemiconductor (CMOS) transistor and its parameter extraction is presented. The whole structure of CECM that includes a small-signal equivalent circuit model of the transistor, a MOSFET small-signal substrate model, an input and output ground-signal-ground (GSG) pad model, a pad coupling model and a metal interconnection model are briefly studied and discussed. Based on this study, a complete test structure model for RF CMOS is designed and the initial values of parameters are extracted by using the analytical method. The multi-bias scattering parameters (S-Parameters) of model correspondence to the experimentation are validated up to 66 GHz and 220 GHz respectively. A good agreement has been achieved between the simulation and experimental under multi-bias conditions.
Fig: Complete CECM for RF CMOS transistor with an entire test structure.


El Mashade, Mohamed B., and Ahmed Abdel Monem
Transient model for modern microelectronic devices applicable to EKV PMOS model 
Radioelectronics and Communications Systems 
Vol.64, no. 2 (2021): 64-79

Abstract: Massive advances in microelectronic manufacturing technology with an exponential growth of their complexity and speed are needed to ensure a continuous development of novel techniques, structures, devices, circuits and systems. This paper is intended for the introduction of a new PMOS transient model for modern microelectronic devices that provides a fast transient response. Such suggested model expresses the transient terminal currents as polynomial functions of the normalized channel charge densities at the channel bounds with the assistance of a modified version of the cubic spline collocation methodology in symmetrical telescopic fashion. Additionally, the optimum number of segments, which is suitable for the new version of the cubic spline collocation algorithm, is investigated. Moreover, the normalized channel charge density at collocation points is modeled in terms of its values at the channel bounds through the quasi-static approach. Furthermore, by means of introducing an inverse function for the normalized overdrive channel voltage, the transient terminal currents are formulated as a function of the terminal voltages. In comparison with usual cubic spline collocation structure, the novel model has much better accuracy in its application to EKV structure. The developed model has been applied to the standard 0.15 mm technology and validated by MATLAB R2014a. The obtained results demonstrate that it gives a very high degree of relative accuracy, on average of 99%, for the total time and exhibits absolute error of less than 5% of the maximum value, in its worst case.


Rakeshkumar Mahto and Reshma John 
Modeling of Photovoltaic Module 
(April 1st 2021)
DOI: 10.5772/intechopen.97082. 

Abstract: A Photovoltaic (PV) cell is a device that converts sunlight or incident light into direct current (DC) based electricity. Among other forms of renewable energy, PV-based power sources are considered a cleaner form of energy generation. Due to lower prices and increased efficiency, they have become much more popular than any other renewable energy source. In a PV module, PV cells are connected in a series and parallel configuration, depending on the voltage and current rating, respectively. Hence, PV modules tend to have a fixed topology. However, in the case of partial shading, mismatching or failure of a single PV cell can lead to many anomalies in a PV module’s functioning. If proper attention is not given, it can lead to the forward biasing of healthy PV cells in the module, causing them to consume the electricity instead of producing it, hence reducing the PV module’s overall efficiency. Hence, to further the PV module research, it is essential to have an approximate way to model them. Doing so allows for understanding the design’s pros and cons before deploying the PV module-based power system in the field. In the last decade, many mathematical models for PV cell simulation and modeling techniques have been proposed. The most popular among all the techniques are diode based PV modeling. In this book chapter, the author will present a double diode based PV cell modeling. Later, the PV module modeling will be presented using these techniques that incorporate mismatch, partial shading, and open/short fault. The partial shading and mismatch are reduced by incorporating a bypass diode along with a group of four PV cells. The mathematical model for showing the effectiveness of bypass diode with PV cells in reducing partial shading effect will also be presented. Additionally, in recent times besides fixed topology of series–parallel, Total Cross-Tied (TCT), Bridge Link (BL), and Honey-Comb (H-C) have shown a better capability in dealing with partial shading and mismatch. The book chapter will also cover PV module modeling using TCT, BL, and H-C in detail.

Available: https://www.intechopen.com/online-first/modeling-of-photovoltaic-module


#Intel to try to become a #foundry, AGAIN?

 



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April 07, 2021 at 02:02PM
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[paper] Compact Modeling as a Bridge between Technologies and ICs


Compact Modeling as a Bridge 
between Scaled Semiconductor Technologies and Advanced Designs of the Integrated Circuits
AB Bhattacharyya and Wladek Grabinski
IETE Journal of Research 58(3):179-180 (May 2012)
DOI: 10.4103/0377-2063.97322

Abstract: The quality of the integrated circuits analysis, required in present contemporary design flows, is directly linked to the accuracy of its basic components—the Compact Model/Simulation Program with Integrated Circuit Emphasis (SPICE) Model. The compact/SPICE modeling is an essential research activity bridging scaled semiconductor technologies and advanced designs of the integrated circuits. To enable complete access to the new advanced semiconductor technologies, the designers have to frequently update their Computer-Aided Design (CAD) tools with accurate definition of the semiconductor device models that can be implemented into the CAD circuit simulators. The models must preferably be physics-based to account for complex dependencies of the device properties and defined in standard, high-level language, i.e., Verilog-A, to simplify access and implementation into the CAD tools. For the state of the art advanced CMOS technologies (analog, HV, SOI), both modeling and characterization are challenging tasks that will be emphasized in this special issue of Compact Modeling. (REF) Compact Modeling as a Bridge between Scaled Semiconductor Technologies and Advanced Designs of the Integrated Circuits. 

Available from: <http://www.mos-ak.org/india/>
and https://www.researchgate.net/publication/278384752_Compact_Modeling_as_a_Bridge_between_Scaled_Semiconductor_Technologies_and_Advanced_Designs_of_the_Integrated_Circuits

Apr 6, 2021

What China is to #India, #USA is to #China



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April 06, 2021 at 03:28PM
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[C4P] DevIC 2021

DevIC 2021: Call for Papers

DevIC 2021 Logo

IEEE KGEC Student Branch Chapter in association with Department of ECE, KGEC, technically co-sponsored by IEEE EDS Kolkata Chapter  organizes International conference 4th Int. Conference DevIC 2021 “Devices for Integrated Circuit (DevIC)”.  There will be keynote lectures/talks, tutorials, and oral presentations  by eminent researchers. The conference organizers invite original papers in the research areas of various aspects of semiconductor technology and circuits that creates an opportunity to symbiosis on topic ranging from process technology to system-on-chip. Articles announcing significant and original results are highly requested. Papers are solicited across the general field of electronic devices. Topics of interest include, but are not limited to;
  • CMOS Processes, Devices and Integration;
  • VLSI Technology and Circuits;
  • Innovative Systems;
  • Emerging Non-CMOS Devices & Technologies;
  • Device Modelling & Simulation; 
  • Device Characterization, Reliability & Yield; 
  • Devices with New material systems;
  • Devices for Low power applications;
  • Low dimensional devices;
  • Low dimensional Semiconductors; 
  • Design and Simulation of Circuits with nanoscale devices;
  • MEMS, Sensors & Display Technologies;
  • Advanced & Emerging Memories; 
  • High frequency wireless communication;


Apr 2, 2021

US President Joe Biden’s $2 trillion infrastructure plan announced this week increases the amount of funding that would be allocated to revive the American #semi industry to $50 billion https://t.co/nacXyKIZla https://t.co/wiXsrxFY4d



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April 02, 2021 at 09:42PM
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Apr 1, 2021

#Google’s #AI Can Design Computer #Chips In Under 6 Hours https://t.co/LNrFo0a1WO #semi https://t.co/UTjBOOT2F1



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April 01, 2021 at 08:22PM
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Virtual Si Museum /2113/ Smart Knife

Smart phone, smart car, but what is inside a smart knife? Mine, Victorinox Swiss Army Traveler has it all: large blade; small blade; can opener; screwdriver 3 mm; bottle opener; screwdriver 6 mm; wire stripper; reamer, punch and sewing awl; corkscrew; mini screwdriver; scissors; multipurpose hook; nail file; toothpick; pressurized ballpoint pen; pin, stainless steel; key ring; tweezers; digital watch (12h/24); countdown; timer; altimeter (m/feet); barometer; thermometer (°C/°F); alarm:




#SiliconValley Can’t Be Copied https://t.co/SMDp2JeHc1 #semi https://t.co/9cAqYuZlFF



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April 01, 2021 at 12:22AM
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Mar 31, 2021

[EDS DL] Prof. M. Lanza, KAUST; Hexagonal boron nitride based electronic devices and circuits: status and prospects

PROF. Mario Lanza, KAUST- Hexagonal boron nitride based

electronic devices and circuits: status and prospects


The EDS Germany Chapter and NanoP proudly presents Mario Lanza from KAUST, Saudi Arabia for a Distinguished Lecture on
"Hexagonal boron nitride based electronic devices and circuits: status and prospects". The lecture will be held on 20th May 2021 at 3pm Berlin time.

Date and Time

Location

The Distiguished Lecture will be held via Zoom. Login information provided before the event and requires registration.

  • Wiesenstraße 14
  • Gießen
  • Germany 35390
Staticmap?size=250x200&sensor=false&zoom=14&markers=50.5870652%2c8

Hosts

Registration

  • Starts 29 March 2021 06:00 PM
  • Ends 16 May 2021 12:00 AM
  • All times are Europe/Berlin
  • No Admission Charge


[webinar] "More Moore Roadmap" by IRDS and SINANO


IEEE EDS France, IRDS and the SINANO Institute will organize a Webinar 

"More Moore Roadmap"
by Mustafa Badaroglu 
IRDS-IFT More Moore Leader

The webinar will be held on 8th April 2021 at 16:00 Paris time. Interest participants please register via IEEE vTools by the following link: https://events.vtools.ieee.org/event/register/267103

Other Webinars of the IRDS Chapters will be announced in the EDS Newsletters

Intel 2.0 = #Intel #Foundry Services https://t.co/GpOUxvmj8q #semi https://t.co/55IAiX3lK6



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March 30, 2021 at 11:09PM
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Mar 26, 2021