[paper] SiC MOSFET Corner and Statistical SPICE Model Generation

SiC MOSFET Corner and Statistical SPICE Model Generation

Canzhong He, James Victory^* , Yunpeng Xiao^**, Herbert De Vleeschouwer⁺, 

Elvis Zheng⁺⁺, ZhiPing Hu⁺⁺ 

 ISPSD, September 13-18, 2020, Vienna, Austria

DOI: 10.1109/ISPSD46842.2020.9170091

   Power Design Enablement, ON Semiconductor, Mountain Top, Pennsylvania/USA

 ^*Power Design Enablement, ON Semiconductor, Aschheim, Germany

^**Power Design Enablement, ON Semiconductor, Shanghai, China 

 ⁺Wide Bandgap Technology Development, ON Semiconductor, Oudenaarde, Belgium 

⁺⁺Product & Test Development Center, ON Semiconductor, Suzhou, China

Abstract: This paper presents a novel approach to generate corner and statistical SPICE models for SiC MOSFETs. The technique is derived from the mature IC industry standard approach known as Backward Propagation of Variance. Physically based, scalable SiC MOSFET SPICE models are required to simulate the correlations between electrical specifications and process variations. The methodologies presented are applicable to other power discrete devices such as super-junction MOSFETs, IGBTs, and GaN HEMTs.

Fig.: SiC MOSFET (a) Cross Section, (b) Subcircuit SPICE Model

[paper] Native High-k Oxides for 2D Transistors

Yury Yu. Illarionov^1,2, Theresia Knobloch¹ and Tibor Grasser¹

Native high-k oxides for 2D transistors

Nature Electronics vol. 3, pp 442–443 (2020)

Published online: 05 August 2020

DOI: 10.1038/s41928-020-0464-2

¹Institute for Microelectronics, TU Wien, Vienna, Austria
²Ioffe Physical-Technical Institute, St Petersburg, Russia

Abstract: The two-dimensional semiconductor Bi₂O₂Se can be oxidized to create an atomically thin layer of Bi₂SeO₅ that can be used as the insulator in scaled field-effect transistors.

Fig.: Development of FETs with Bi₂O₂Se channels and native Bi₂SeO₅ insulators. a.) Step-by-step oxidation of multilayer Bi₂O₂Se towards Bi₂SeO₅ and the crystal structure of the two materials. b.) Cross-sectional scanning transmission electron microscopy image confirming the atomically sharp interface. c.) Schematic of the top-gated devices fabricated with a native gate oxide. d.) Gate transfer characteristics of the devices with a 4.6-nm-thick Bi₂SeO₅ layer (EOT below 1 nm)

Analog IC Designer's Handbook

Top-Down method at work in analog IC design

by Jean-Francois Debroux

 

Abstract: Analog IC design is one of the particular design activities where designers get feedback on their choices only months after they finish their design and where the cost of even the smallest design change is huge.

This has historically brought the need for new tools such as SPICE, the ancestor of almost all the electric simulators, so as to give feedback on the design choices before actually getting the prototypes. This should also have deeply impacted the design methods, and it has, but the availability of simulators has finally allowed the old “try and fix” method not only to survive but also to stay very popular.

If tools such as electric simulators have gained popularity in most electronic design fields, even out of the IC design world, methods such as the TOP-DOWN approach are not as popular as they should be, especially in the analog design community, even in the analog IC design microcosm. This is probably because this method is felt as difficult to use practically even though most designers agree that it is the right approach.

The goal of this book is to show that the TOP-DOWN approach for analog design is not only valid but that it is one of the most powerful available methods to create good analog design without sacrificing the time to market. This method creates faster and better designs but requires a good understanding of the method itself, of course, but also of the underlying techniques and of the basic design elements.

After a general introduction of the TOP-DOWN method goals and principles in the first part, the second part presents and details analog IC design elements from components to basic building blocks with a strong emphasis on practical aspects. Various additional design techniques are then detailed in the third part. The reader is then ready for the main course, a series of design examples based on the TOP-DOWN method that are grouped in the fourth part. These examples are processed the way they are in real life, from specification to implementation, from general considerations down to implementation details. Analysis of existing circuits is useful for learning but real life design is synthesis, not analysis.

Finally, the fifth part introduces or reminds useful basic concepts and presents the notation in use through the book.

The methods and techniques described in this book have been used by the author through 25 years of analog and mixed signal ICs design experience in various application fields including RF and sensor signal conditioning for various markets such as industrial, automotive and aerospace. The author feels that the method he presents in this book can help many analog electronic designers in their day to day work and hopes it will bring both a deeper understanding of design and a broader view over design activities. [read more...]

Contact / Feedback: jean-francois.debroux@orange.fr

Experience: See  Jean-Francois Debroux profile on LinkedIn

Fwd: Announcement of Online Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates (Sept 14-19, 2020) jointly organized by Science Foundation and MHRD-IIC-DDUC Chapter, Deen Dayal Upadhyaya College, University of Delhi, New Delhi (Under the aegis of DBT Star College Program)

On behalf of Science Foundation and MHRD-IIC-DDUC Chapter, Deen Dayal Upadhyaya College, University of Delhi, New Delhi (Under the aegis of DBT Star College Program), I would like to invite you to kindly register for the Online Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates scheduled for September 14-19, 2020.

The workshop is likely to be supported by the Science Academies and will be organized using CISCO WEBEX/Microsoft Teams.

All Interested Science and Engineering Students and Faculty Members are requested to kindly register on 

or before August 25, 2020 via link appended below

https://docs.google.com/forms/d/e/1FAIpQLSfFA3Yp7quiJN8fZTJrCR8jkyE4XA8Ddr0hdMi5r5IEiTctVg/viewform  

There is NO REGISTRATION FEES. I request you to kindly motivate your students and colleagues to register for the same.

Organizing Committee

• Professor Anurag Sharma, FNA, FNASc, FASc, FNAE, JC Bose National Fellow (SERB), Department of Physics, IIT Delhi (Convener-Workshop)
• Professor Ajoy Ghatak, NASI Meghnad Saha Distinguished Professor, Chairperson-NASI Delhi Chapter.
• Dr. Manoj Saxena, Coordinator-Workshop, Deen Dayal Upadhyaya College, University of Delhi, New Delhi (msaxena@ddu.du.ac.in)
• Committee Members of Science Foundation, MHRD-IIC-DDUC Chapter and DBT Star College Program of  Deen Dayal Upadhyaya College, University of Delhi.

with regards

Dr. Manoj Saxena | डॉ मनोज  सक्सेना 

Associate Professor | सह - आचार्य

Department of Electronics | इलेक्ट्रॉनिक्स विभाग

Deen Dayal Upadhyaya College | दीन दयाल उपाध्याय कॉलेज

University of Delhi | दिल्ली विश्वविद्यालय

Dwarka Sector-3, New Delhi-110078 | द्वारका क्षेत्र -३, नई दिल्ली -११००७८

India | भारत

Official Homepage: https://dducollegedu.ac.in/ViewProfile.aspx?fId=saxenamanoj77@gmail.com

ORCID Webpage : http://orcid.org/0000-0002-9368-4194

Scopus Webpage : http://www.scopus.com/authid/detail.url?authorId=35480023200

ResearcherID-Thomson Reuters : http://www.researcherid.com/rid/K-3863-2015 

Publons Profile: https://publons.com/researcher/1341187/manoj-saxena

Please do not print this email unless it is absolutely necessary. Spread environmental awareness. 

Fwd: IEEE-EDS Santa Clara Valley/San Francisco Chapter August Seminar (Webex only)

Please note that this seminar is now WEBEX participation only! 

Memory Errors in Production Systems – Insights from the Field

Speaker: Dr. Sudhanva Gurumurthi, Principal Member of Technical Staff, AMD

Friday, August 28, 2020 at 12PM – 1PM PDT

Register Here

Abstract: Memory reliability is important for the correct operation of computing systems. While technology scaling has paved the way for improvements in the capacity and energy-efficiency of memory, the reliability aspects of such scaling must be well characterized and addressed in the design of computer hardware. AMD has collected and analyzed memory reliability data from several production systems running in data centers. This data spans several generations of DRAM technologies, as well as SRAM. This talk will first explain how bit-cell reliability can impact on the design and use of computing hardware and highlight the importance of studying memory faults from commercial hardware in the field. The talk will then present memory reliability data and insights from AMD's field studies and discuss their implications from the viewpoint architecting resilient systems.

Speaker Bio: Sudhanva Gurumurthi is a Principal Member of the Technical Staff at AMD, where he leads advanced development in Reliability, Availability, and Serviceability (RAS). He used to be an Associate Professor with tenure in the Computer Science Department at the University of Virginia. Sudhanva is a recipient of the NSF CAREER Award, a Google Focused Research Award, two Google Faculty Research Awards, and other NSF and industry awards. He is a Senior Member of the IEEE and the ACM. 

 

More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

Subscribe or Invite your friends to sign up for our mailing list and get to hear about exciting electron-device relevant talks. We promise no spam and try to minimize email. You can unsubscribe easily.

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[paper] SPICE model of p‐Si TFET

Sola Woo Juhee Jeon Sangsig Kim 

A SPICE model of p‐channel silicon tunneling field‐effect transistors for logic applications

IJNM: 06 August 2020; DOI: 10.1002/jnm.2793

¹Department of Electrical Engineering,Korea University, Seoul, South Korea

Abstract: In this study, we propose a SPICE model of p-channel silicon tunneling field-effect transistors (TFETs) for logic applications. To verify our model, electrical characteristics of fabricated p-TFETs are calibrated by utilizing TCAD and SPICE simulations. We simulate various logic gates, such as complementary TFET (c-TFET) inverters, c-TFET NAND gates, and c-TFET NOR gates using our TFET model. Our simulation shows that a c-TFET inverter can be operated at VDD as low as 0.3?V and that c-TFET logic gates based on our model can operate ~1000 times higher frequency than conventional TFET logic gates.

FIG: 2D structure of p-TFET for our simulation 

and its simulated/measured transfer characteristics at VDS=-1.0V

Acknowledgements: This research was partly supported by the MOTIE (Ministry of Trade, Industry & Energy) (10067791) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device, the Brain Korea 21 Plus Project in 2020, and Samsung electronics.

You don't need a computer science degree to work with #opensource software https://t.co/cpAlOk7V7U https://t.co/u3bNQ295sK

You don't need a computer science degree to work with #opensource software https://t.co/cpAlOk7V7U pic.twitter.com/u3bNQ295sK

— Wladek Grabinski (@wladek60) August 6, 2020

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August 06, 2020 at 05:14PM
via IFTTT

Call for Chapters

Title: Sub-Micron Semiconductor Devices: Design and Applications

Introduction: To follow Moore’s law, semiconductor devices are scaled-down without compromising the performance. Semiconductor devices are supposed to be reduced in dimensions and work at lower operating biases but the problem arises during the manufacturing of the devices. Thus, it is a dire necessity to opt for a solution that can help in continuing the path of performance improvement. Steady performance enhancement using optimization techniques can support the time required for advancements in fabrication technologies. This publication confines the novel semiconductor devices, issues with conventional devices, optimization techniques and solutions for the performance enhancement. Even with the presence of a vast amount of data regarding semiconductor devices, it is hard for a researcher to go through most of the recent advancements altogether and understand them in a clear way. The motive behind the book is to comprehensibly present the material related to the recent advancements in the field of semiconductor devices that can allow the reader to interpret the possible concepts behind the content. The study of novel semiconductor devices may help in unraveling the mystery behind the problems that are required to tackle during the fabrication of molecular devices.

Topics: [Not limited to the given topics but relevant topics will be considered as well]

• Basic of Scaled-Down Devices
• (Nano-FET, TFET, LED, Solar Cell, TFT, HEMT, Diodes, RTDs, Photodiode, Quantum-Dots, Spin-FET, etc.)
• Comparative Study of Novel Semiconductor Devices
• Inclusion of Quantum Effects in Nano-Devices
• (Short Channel Effects, Fermi-Level-Pinning, Quantum Confinement, Discrete DOS, etc.)
• Device Modelling and Physics
• (Analytical, Compact, NEGF, Quantum, Verilog, Spice, etc.)
• Novel Materials for Devices
• (Graphene, Silicene, TMDCs, Organic, Perovskite, 2D Materials, TCO, Photo-dielectric, etc.)
• Characterization and Fabrication
• (Spectroscopic, Microscopic, MBE, CVD, Spin-Coating, Defects, etc.)
• Optimization Techniques
• (Negative Capacitance, Feedback, Gate-on-Source, Dopingless, 2DEG, Schottky Contact, etc.)
• Testing of Semiconductor Devices
• Applications
• (Biosensor, Radiation Sensor, Light Sensor, Analog/Digital Circuit Applications, MEMS, etc.)
• Issues and Solutions of Novel devices
• Future Device Technology

Important Dates (Updated):

Chapter Proposal Submission: 10 September 2020 Notification of Acceptance: 15 September 2020 Full Chapter Submission: 25 October 2020

Review Result Returned: 30 October 2020 Final Acceptance: 10 November 2020 Publication of Book: January-February 2021

Submission:

Kindly submit the chapter proposal [Tittle, Abstract (500-1000 words), Possible Content, Author details] before the due date via E-mail at call.chapters.crc@gmail.com. Any kind of query regarding the chapter or abstract submission, formatting and corrections can be submitted to query.chapters.crc@gmail.com

Editors:

Ashish Raman¹, Deep Shekhar² and Naveen Kumar³

Electronics and Communication Engineering Department, Dr. B. R. Ambedkar National Institute of Technology Jalandhar, [Grand Trunk Road, Barnala - Amritsar Bypass Rd, Jalandhar, India 144011] 

Official E-mail IDs: ¹ ramana@nitj.ac.in, ² deeps.ec.18@nitj.ac.in, ³ naveenk.ec.16@nitj.ac.in

[chapter] Design of FET Biosensors

Khuraijam Nelson Singh¹ and Pranab Kishore Dutta¹

Chapter 8: Analytical Design of FET-Based Biosensors

in Advanced VLSI Design and Testability Issues; Eds: Suman Lata et all.

CRC Press, 19 Aug 2020; 360 pages

¹NERIST, Arunachal Pradesh, India

Abstract: Research on biosensors has seized the interested researchers over the past few decades due to their various advantages and applications. They are used in the discovery of drugs, monitoring of diseases, agriculture, food quality control, industrial wastage monitoring, military, etc. The sensing analyte is the main element that differentiates a biosensor from the other physical/chemical sensors. In general, the biosensor is a device that is used to detect an analyte using a biosensitive receptor. Its main components are as follows:

• Analytes: The substance that is intended to be detected, such as glucose in a glucose sensor, ammonia in ammonia sensor, and so on.
• Bioreceptors: The bioreceptors are biosensitive elements used to detect target analytelbiomolecule. They are sensitive to the analytes of interest. Some examples of bioreceptors are antigen, DNA, enzyme, and so on.
• Transducers: The elements that are used to convert energy from one form to another are called transducers. In a biosensor, the interaction of analytes and bioreceptors produces changes in the form of heat, gas, light, ions, or electrons. These changes are then converted into a quantif‌iable form by the transducer. Usually, the output of the transducer is in the form of electrical or optical signals, and the generated signal is proportional to the interaction between the analyte and the biosensor.

FIG: Schematic diagram of ion-sensitive f‌ield-effect transistor (ISFET)

[paper] GCC Method for Determining MOSFET VTH

Matthias Bucher¹, Nikolaos Makris¹, Loukas Chevas¹

Generalized Constant Current Method for Determining MOSFET Threshold Voltage

arXiv:2008.00576v1 (2 Aug 202) 

has been submitted to the IEEE for possible publication

¹ School of Electrical and Computer Engineering, Technical University of Crete

Abstract: A novel method for extracting threshold voltage (VTH) and substrate effect parameters of MOSFETs with constant current bias at all levels of inversion is presented. This generalized constant-current (GCC) method exploits the charge-based model of MOSFETs to extract threshold voltage and other substrate-effect related parameters. The method is applicable over a wide range of current throughout weak and moderate inversion and to some extent in strong inversion. This method is particularly useful when applied for MOSFETs presenting edge conduction effect (subthreshold hump) in CMOS processes using Shallow Trench Isolation (STI).

Fig:  Application of the GCC method in presence of edge conduction phenomenon in STI MOSFETs. A constant current is applied to determine pinchoff voltage for the center transistor in moderate inversion at IC=2. To characterize the edge transistor, imposing a current criterion IC=1E−4 corresponds to ICe≈0.02. Pinchoff voltage (VP) and slope factor n characteristics illustrate the determination of parameters for center and edge transistors.

Acknowledgment: This work was partly supported under Project INNOVATION-EL-Crete

(MIS 5002772).

#Top10 #Analogue Companies https://t.co/AOW7Q1A4Ou #semi https://t.co/Zzt1sVsobD

#Top10 #Analogue Companies https://t.co/AOW7Q1A4Ou #semi pic.twitter.com/Zzt1sVsobD

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[paper] Macromodels for MEMS Switches

Aurel-Sorin Lup¹, Gabriela Ciuprina¹, Daniel Ioan¹ and Anton Duca¹

and Alexandra Nicoloiu² and Dan Vasilache²

Physics-aware macromodels for MEMS switches

COMPEL International Journal (2020)

¹DEE Politehnica, Uni. Bucharest, (R)

²IMT-Bucharest, Bucharest (R)

Abstract: The purpose of this paper is to propose a physics-aware algorithm to obtain radio frequency (RF)- reduced models of micro-electromechanical systems (MEMS) switches and show how, together with multiphysics macromodels, they can be realized as circuits that include both lumped and distributed parameters. The macromodels are extracted with a robust procedure from the solution of Maxwell’s equations with electromagnetic circuit element (ECE) boundary conditions. The reduced model is extracted from the simulations of three electromagnetic field problems, in full-wave regime, that correspond to three configurations: signal lines alone, switch in the up and down positions. The technique is exemplified for shunt switches, but it can be extended for lateral switches. Moreover, the algorithm is able take frequency dependence into account both for the signal lines and for the switch model. For the later, the order of the model is increased until a specified accuracy is achieved. The use of ECE as boundary conditions for the RF simulation of MEMS switches has the advantage that the definition of ports is unambiguous and robust as the ports are clearly defined. The extraction approach has the advantage that the simplified model keeps the basic phenomena, i.e. the propagation of the signal along the lines. As the macromodel is realized with a netlist that uses transmission lines models, the lines’ extension is natural. The frequency dependence can be included in the model, if needed.

Fig: Modeling chain: from continuous models to reduced macromodels

Acknowledgement: The work has been funded by the Operational Programme Human Capital of the Ministry of European Funds through The Financial Agreement 51675/09.07.2019, SMIS code 125125.

William English, Computer Mouse Co-Creator, Has Passed died July 26 in San Rafael, California. He was 91 years old. https://t.co/q7PNnR694g #semi https://t.co/KOCm8at33a

William English, Computer Mouse Co-Creator, Has Passed died July 26 in San Rafael, California. He was 91 years old.https://t.co/q7PNnR694g#semi pic.twitter.com/KOCm8at33a

— Wladek Grabinski (@wladek60) August 4, 2020

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[paper] SiC MOSFET SPICE Model

Lefdal Hove, Haavard, Ole Christian Spro, Giuseppe Guidi

and Dimosthenis Peftitsis

Improved SiC MOSFET SPICE Model to Avoid Convergence Errors

Materials Science Forum 1004 (July 2020): 856–64

DOI: 10.4028/www.scientific.net/msf.1004.856

Abstract: This paper presents improvements to a SPICE model for a commercially available SiC MOSFET to avoid convergence errors while still providing reliable simulation results. Functionality in the internal part of the model that shapes the transconductance of the device according to its junction temperature and gate-source voltage dependency has been improved to provide a continuous characteristic rather than the initial discontinuous performance. Furthermore, the output characteristics from the initial and the proposed model have been compared to lab measurements of an actual device. The results show that the proposed and initial model provide equally reliable simulation results. However, the proposed model does not run into convergence problems.

References 

[1] X. She, A. Huang, O. Lucia, and B. Ozpineci, Review of Silicon Carbide Power Devices and Their Applications, IEEE Transactions on Industrial Electronics, vol. 64, no. 10, p.8193–8205, (2017).

[2] J. Rabkowski, D. Peftitsis, and H. P. Nee, Silicon carbide power transistors: A new era in power electronics is initiated, IEEE Industrial Electronics Magazine, vol. 6, no. 2, p.17–26, (2012).

[3] A. Stefanskyi, L. Starzak, A. Napieralski, and M. Lobur, Analysis of SPICE models for SiC MOSFET power devices,, 2017 14th CADSM 2017 - Proceedings, p.79–81, (2017).

[4] H. L. Hove, O. C. Spro, D. Peftitsis, G. Guidi, and K. Ljøkelsøy, Minimization of dead time effect on bridge converter output voltage quality by use of advanced gate drivers, 2019 10th ICPE 2019 ECCE Asia, (2019).

[5] N. Mohan, T. Undeland, and W. Robbins, Power Electronics; Converters, Applications, and Design, third ed., Wiley, (2003).

[6] C. Enz, F. Krummenacher, and E. Vittoz, An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Application, Analog Integrated Circuits and Signal Processing, vol. 8, p.83–114, (1995).

[7] M. Bucher, C. Lallement, C. Enz, F. Théodoloz, and F. Krummenacher, The EPFL-EKV MOSFET Model Equations for Simulation Technical Report V2.6,, EPFL, Lausanne, Switzerland, (1999).

[8] B. N. Pushpakaran, S. B. Bayne, G. Wang, and J. Mookken, Fast and accurate electro-thermal behavioral model of a commercial SiC 1200V, 80 mΩ power MOSFET,, Digest of Technical Papers IEEE IPPC, vol. 2015-Octob, p.1–5, (2015).

IEEE International Electron Devices Meeting to be Held Virtually https://t.co/LGJVdu1TyN https://t.co/vVgVsLrX4I #paper https://t.co/XN5oesBAQE

IEEE International Electron Devices Meeting to be Held Virtually https://t.co/LGJVdu1TyNhttps://t.co/vVgVsLrX4I#paper pic.twitter.com/XN5oesBAQE

— Wladek Grabinski (@wladek60) August 3, 2020

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#Samsung wants consortium, not #Nvidia, to buy #ARM https://t.co/oHWncoirCL #semi https://t.co/ugfrenqdAX

#Samsung wants consortium, not #Nvidia, to buy #ARM https://t.co/oHWncoirCL#semi pic.twitter.com/ugfrenqdAX

— Wladek Grabinski (@wladek60) August 3, 2020

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#SMIC, #Beijing to build $7.6 billion #wafer fab https://t.co/ZqczycwQXx #semi https://t.co/VNhsMxR6zX

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[Report] 2nd Latin America MOS-AK Workshop at LAEDC

Recently the 2nd Latin America MOS-AK Workshop at LAEDC was reported in IEEE EDS Newsletter, July 2020 Vol. 27, No. 3 ISSN: 1074 1879 by Lluis Marsal and Benjamin Iñiguez:

The 2nd Latin American edition of the MOS-AK Workshop on Compact Modeling was held at LAEDC in San Jose, Costa Rica, was held in conjunction with the Latin American Symposium on Circuits and Systems (LASCAS 2020).. It was chaired by Prof. Benjamin Iñiguez (Universitat Rovira I Virgili, Tarragona, Spain). It included five talks. Prof. Antonio Cerdeira (CINVESTAV, Mexico) presented an "Analytical Current Voltage Model for Double Gate a-IGZO TFTs with Symmetric Structure." Prof. Alexander Kloes (THM, Giessen, Germany) addressed "Approaches for Analytical (Compact) Modeling of Tunneling Currents in MOS Transistors." Prof. Jean-Michel Sallese (EPFL, Switzerland) gave a talk about "Modeling the Junctionless Ion Sensitive Field Effect Transistor" Prof. Gilson Wirth (UFRGS, Porto Alegre, Brazil) targeted "The area scaling of charge trap induced time-dependent variability." Finally, Prof. Benjamin Iñiguez (URV, Tarragona, Spain) talked about "Characterization and modeling of 1/f noise in organic and IGZO TFTs". Over 70 academics, professionals and students attended these events and enjoyed the discussions with the speakers. 

Visit also <http://www.mos-ak.org/costa_rica_2020/>

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[mos-ak] Fwd: ESSCIRC ESSDERC 2020 | before going on holiday

Are you all set for your well deserved summer holiday? Before you go, have a look at ESSCIRC ESSDERC 2020 Educationals and do not forget to register! 1. TUTORIAL | Quantum Computing: Myth or Reality? 2. WORKSHOP | Emerging Solutions for Imaging Devices, Circuits and Systems 3. WORKSHOP | Non-Volatile Memories: Opportunities and Challenges from Devices to Systems 4. WORKSHOP | New 5G integration solutions, and related technologies (from materials to system) 5. WORKSHOP | Advances in device technologies for automotive industry (power devices, SiC, GaN) 6. WORKSHOP | Embedded monitoring and compensation design for energy or safety constrained applications 7. WORKSHOP | Edge AI and In-Memory-Computing for energy efficient AIoT solutions 8. WORKSHOP | Ab-initio simulations supporting new materials & process developments 9. WORKSHOP | RISC-V cooking session 10. DISSEMINATION WORKSHOP |  Toward sustainable IOT from rare materials to big data 11. DISSEMINATION WORKSHOP | High Density 3D CMOS Mixed-Signal Opportunities 12. MOS-AK WORKSHOP | Compact/SPICE Modeling and its Verilog-A Standardization 13. IPCEI on Microelectronics: Innovative Technologies for Shaping the Future REGISTER NOW! JOIN NOW OUR  ESSCIRC – ESSDERC LinkedIn group! ORGANIZING COMMITTEE Thomas Ernst (CEA-LETI, FR), General co-chair Dominique Thomas (STMicroelectronics, FR), General co-chair François Andrieu (CEA-LETI, FR), ESSDERC TPC Chair Maud Vinet (CEA-LETI, FR), ESSDERC TPC co-Chair Andreia Cathelin (STMicrolectronics, FR), ESSCIRC TPC Chair Sylvain Clerc (STMicrolectronics, FR),  ESSCIRC TPC co-Chair LOCAL EXECUTIVE SECRETARIAT Sandra Barbier (CEA-LETI, FR) | sandra.barbier@cea.fr ORGANIZING SECRETARIAT Sistema Congressi s.r.l. | essxxrc@sistemacongressi.com  ORGANIZERS TECHNICAL SPONSORSHIP FINANCIAL SPONSORSHIP WELCOME OUR DIAMOND SPONSOR! View this email in your browser Copyright © 2020 Sistema Congressi s.r.l., All rights reserved. You are receiving this email because you attended or expressed interest in ESSCIRC-ESSDERC events, or because you are involved in similar fields of research Our mailing address is: Sistema Congressi s.r.l. via Trieste, 26 Padova, PD 35121 Italy Add us to your address book Want to change how you receive these emails? You can update your preferences or unsubscribe from this list.

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Chipmaker #SMIC Eyes China’s Biggest Share Sale in a Decade https://t.co/x7fWlihi15 #semi https://t.co/W5DgoT4Kul

Chipmaker #SMIC Eyes China’s Biggest Share Sale in a Decade https://t.co/x7fWlihi15#semi pic.twitter.com/W5DgoT4Kul

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[paper] Compact Modeling of IGBT

Y. Miyaoku, A. Tone, K. Matsuura, M. Miura-Mattausch, H. J. Mattausch, and *D. Ikoma

Compact Modeling of IGBT Charging/Discharging

for Accurate Switching Prediction

IEEE J-EDS,  DOI:10.1109/jeds.2020.3008919 

Graduate School of Advanced Sciences of Matter, Hiroshima University, Japan

*Denso Corp., Aichi, Japan

Abstract: The trench-type IGBT is one of the major devices developed for very high-voltage applications, and has been widely used for the motor control of EVs as well as for power-supply systems. In the reported investigation, the accurate prediction of the power dissipation of IGBT circuits has been analyzed. The main focus is given on the carrier dynamics within the IGBTs during the switching-off phase. It is demonstrated that discharging and charging at the IGBT’s gate-bottom-overlap region, where electron discharging is followed by hole charging, has an important influence on the switching performance. In particular, the comparison of long-base and short-base IGBTs reveals, that a quicker formation of the neutral region within the resistive base region, as occurring in the long-base IGBT, leads to lower gatebottom-overlap capacitance, thus realizing faster electron discharging and hole charging of this overlap region.

Fig: Studied IGBT structure with indicated current flows

[paper] Vertical III-V Nanowire MOSFETs on Si

Olli-Pekka Kilpi, Markus Hellenbrand, Johannes Svensson, Axel R. Persson, Reine Wallenberg, Erik Lind, Member, IEEE, and Lars-Erik Wernersson

High-Performance Vertical III-V Nanowire MOSFETs on Si With gm > 3 mS/μm

in IEEE EDL vol. 41, no. 8, pp. 1161-1164, Aug. 2020

DOI: 10.1109/LED.2020.3004716

Abstract: Vertical III-V nanowire MOSFETs have demonstrated excellent performance including high transconductance and high Ion. One main bottleneck for the vertical MOSFETs is the large access resistance arising from the contacts and ungated regions. We demonstrate a process to reduce the access resistance by combining a gate-last process with ALD gate-metal deposition. The devices demonstrate fully scalable gm down to Lg = 25 nm. These vertical core/shell InAs/InGaAs MOSFETs demonstrate gm = 3.1 mS/μm and Ron = 190 μm. This is the highest gm demonstrated on Si. Transmission line measurement verifies a low contact resistance with RC = 115 μm, demonstrating that most of the MOSFET access resistance is located in the contact regions.

FIG: (a) of the MOSFET structure demonstrating benefit of the TiN gate metal;

(b )output characteristics of the vertical nanowire MOSFET 

with 90 nanowires, LG = 25 nm and diameter 17 nm.

Acknowledgment: This work was supported in part by the Swedish Research Council, in part by the Knut and Alice Wallenberg Foundation, in part by the Swedish Foundation for Strategic Research, and in part by the European Union H2020 Program INSIGHT under Grant 688784.

“Entrope” High-Frequency #HF #Noise Probe – Device Lab Inc. https://t.co/GSalqQAnX1 #semi https://t.co/rTU6actXHx

“Entrope” High-Frequency #HF #Noise Probe – Device Lab Inc. https://t.co/GSalqQAnX1 #semi pic.twitter.com/rTU6actXHx

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#European Research and Innovation #R&I #Days https://t.co/BR7YIsy2xO #semi https://t.co/qxbrrmOV1j

#European Research and Innovation #R&I #Days https://t.co/BR7YIsy2xO #semi pic.twitter.com/qxbrrmOV1j

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#SOI #Photonics for communication, sensing, and computing markets https://t.co/JFZNFHJkNb #semi https://t.co/fpfZqpGtfW

#SOI #Photonics for communication, sensing, and computing markets https://t.co/JFZNFHJkNb#semi pic.twitter.com/fpfZqpGtfW

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Jerzy Ruzyllo - Guide to Semiconductor Engineering

Guide to Semiconductor Engineering

Jerzy Ruzyllo¹ (Pennsylvania State University, USA)

World Scientific Book Series. March 2020

This Guide to Semiconductor Engineering is concerned with semiconductor materials, devices and process technologies which in combination are the driving force behind the unprecedented growth of our technical civilization over the last half a century. This book was conceived and written keeping in mind those who need to learn about semiconductor engineering, who are professionally associated with select aspects of this technical domain and want to see it in a broader context, or are simply interested in semiconductors. In its coverage of semiconductor engineering this Guide departs from textbook-style, monothematic in-depth coverage of topics such as the physics of semiconductors and semiconductor devices, the manufacturing of semiconductor devices and circuits, and the characterization of semiconductor materials. Instead, it covers the entire field of semiconductor engineering in one concise volume with synergistic interactions between various areas clearly identified. It is a holistic approach to the coverage of semiconductor engineering which makes this guide unique among books covering semiconductor related issues available on the market today. 

[Table of Contents]

¹Jerzy Ruzyllo is a Distinguished Professor Emeritus in the School of Electrical Engineering and Computer Science at the Pennsylvania State University. He joined Penn State in 1984 after completing his education, obtaining a PhD degree in 1977, and serving on the faculty of the Warsaw University of Technology in Poland. Throughout his career, Dr Ruzyllo was actively involved in research and teaching in the area of semiconductor science and engineering. Dr Ruzyllo is a Life Fellow of IEEE and Fellow of the Electrochemical Society.

Jan #Czochralski And The #Silicon #Revolution https://t.co/LMX4tiAuIQ #semi https://t.co/zKPirLDPji

Jan #Czochralski And The #Silicon #Revolution https://t.co/LMX4tiAuIQ #semi pic.twitter.com/zKPirLDPji

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[paper] Compact Source-Gated Sensor

Eva Bestelink, Student Member, IEEE, Kham M. Niang, Georgios Bairaktaris, Luca Maiolo, Francesco Maita, Kalil Ali, Andrew J. Flewitt, S. Ravi P. Silva

and Radu A. Sporea, Senior Member, IEEE

Compact Source-Gated Transistor Analog Circuits for Ubiquitous Sensors

In IEEE Sensors. Jul 18, 2020

Abstract: Silicon-based digital electronics have evolved over decades through an aggressive scaling process following Moore’s law with increasingly complex device structures. Simultaneously, large-area electronics have continued to rely on the same field-effect transistor structure with minimal evolution. This limitation has resulted in less than ideal circuit designs, with increased complexity to account for shortcomings in material properties and process control. At present, this situation is holding back the development of novel systems required for printed and flexible electronic applications beyond the Internet of Things. In this work we demonstrate the opportunity offered by the source-gated transistor’s unique properties for low-cost, highly functional large-area applications in two extremely compact circuit blocks. Polysilicon common-source amplifiers show 49 dB gain, the highest reported for a twotransistor unipolar circuit. Current mirrors fabricated in polysilicon and InGaZnO have, in addition to excellent current copying performance, the ability to control the temperature dependence (degrees of positive, neutral or negative) of output current solely by choice of relative transistor geometry, giving further flexibility to the design engineer. Application examples are proposed, including local amplification of sensor output for improved signal integrity, as well as temperature-regulated delay stages and timing circuits for homeostatic operation in future wearables. Numerous applications will benefit from these highly competitive compact circuit designs with robust performance, improved energy efficiency and tolerance to geometrical variations: sensor front-ends, temperature sensors, pixel drivers, bias analog blocks and high-gain amplifiers.

FIG: a) Photomicrograph of a typical polysilicon SGT fabricated; b) Driver M1 output characteristics (black curves, VGmax = -15 V, step 0.5 V) and superimposed M2 load line (orange, VG = 0 V). VSAT1 occurs as a result from pinch-off at the source and VSAT2 represents channel pinch-off of the parasitic FET. 

Acknowledgment: R.A.S. acknowledges the Royal Academy of Engineering of Great Britain for the support through the Research Fellowship (Grant No. 10216/110), the Royal Society of Great Britain through project ARES IES\R3\170059 and EPSRC for grants EP/R028559/1 and EP/R025304/1. K.M.N. and A.J.F. acknowledge the support of the Engineering and Physical Sciences Research Council (EPSRC) through project EP/M013650/1. R.A.S. thanks Prof John Shannon for technical discussions, Dr Nigel Young and Dr Michael Trainor for assistance with polysilicon device design and fabrication.

#Intel Plunges as It Weighs #Exit From Manufacturing Chips https://t.co/Yxg9KUq5iT #semi https://t.co/fJDOLaFTKD

#Intel Plunges as It Weighs #Exit From Manufacturing Chips https://t.co/Yxg9KUq5iT #semi pic.twitter.com/fJDOLaFTKD

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