Showing posts with label tunnel FET logic gate. Show all posts
Showing posts with label tunnel FET logic gate. Show all posts

Aug 17, 2020

[paper] SPICE model of p‐Si TFET

Sola Woo Juhee Jeon Sangsig Kim 
A SPICE model of p‐channel silicon tunneling field‐effect transistors for logic applications
IJNM: 06 August 2020; DOI: 10.1002/jnm.2793

1Department of Electrical Engineering,Korea University, Seoul, South Korea

Abstract: In this study, we propose a SPICE model of p-channel silicon tunneling field-effect transistors (TFETs) for logic applications. To verify our model, electrical characteristics of fabricated p-TFETs are calibrated by utilizing TCAD and SPICE simulations. We simulate various logic gates, such as complementary TFET (c-TFET) inverters, c-TFET NAND gates, and c-TFET NOR gates using our TFET model. Our simulation shows that a c-TFET inverter can be operated at VDD as low as 0.3?V and that c-TFET logic gates based on our model can operate ~1000 times higher frequency than conventional TFET logic gates.
FIG: 2D structure of p-TFET for our simulation 
and its simulated/measured transfer characteristics at VDS=-1.0V

Acknowledgements: This research was partly supported by the MOTIE (Ministry of Trade, Industry & Energy) (10067791) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device, the Brain Korea 21 Plus Project in 2020, and Samsung electronics.