TCAD Mobility #Model of III-V Short-Channel Double-Gate FETs Including Ballistic Corrections https://t.co/xAcLMzh4S9
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November 25, 2017 at 06:04PM
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Nov 25, 2017
TCAD Mobility #Model of III-V Short-Channel Double-Gate FETs Including Ballistic Corrections https://t.co/xAcLMzh4S9
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November 25, 2017 at 06:04PM
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Nov 24, 2017
A Compact Quasi-Static Terminal Charge and Drain Current #Model for Double-Gate Junctionless Transistors and Its... https://t.co/zg9x86qUaH
A Compact Quasi-Static Terminal Charge and Drain Current #Model for Double-Gate Junctionless Transistors and Its... https://t.co/zg9x86qUaH
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November 24, 2017 at 09:39PM
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A Compact Quasi-Static Terminal Charge and Drain Current #Model for Double-Gate Junctionless Transistors and Its Circuit Validation - IEEE Journals & Magazine https://t.co/NgDkKN8gxr
A Compact Quasi-Static Terminal Charge and Drain Current #Model for Double-Gate Junctionless Transistors and Its Circuit Validation - IEEE Journals & Magazine https://t.co/NgDkKN8gxr
— Wladek Grabinski (@wladek60) November 24, 2017
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November 24, 2017 at 09:39PM
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Nov 22, 2017
Determination of well flat band condition in thin film FDSOI transistors using C-V measurement for accurate parameter extraction https://t.co/6djtGE7OZV #paper https://t.co/RYLH3fSGhg
Determination of well flat band condition in thin film FDSOI transistors using C-V measurement for accurate parameter extraction https://t.co/6djtGE7OZV #paper http://pic.twitter.com/RYLH3fSGhg
— Wladek Grabinski (@wladek60) November 21, 2017
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November 21, 2017 at 11:54PM
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A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation https://t.co/R0t2mdhbMF #paper
A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation https://t.co/R0t2mdhbMF #paper
— Wladek Grabinski (@wladek60) November 21, 2017
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November 21, 2017 at 11:18PM
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Nov 21, 2017
[mos-ak] [Final Program] 10th International MOS-AK Workshop in the Silicon Valley
10th International MOS-AK Workshop
(co-located with the CMC Meeting and IEDM Conference)
Silicon Valley, December 6, 2017
Together with local organization teams Cadence Design Systems and Keysight Technologies as well as International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and all the Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Compact Modeling Workshop which will be organized for consecutive 10th time in the timeframe of coming IEDM and CMC Meetings.
Scheduled,10th subsequent MOS-AK modeling workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online:
Scheduled,10th subsequent MOS-AK modeling workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online:
<http://www.mos-ak.org/silicon_valley_2017/>
Venue:
Postworkshop Publications:
Extended MOS-AK Committee
Venue:
Online Workshop Registration is still openCadence Design Systems2655 Seely AveSan Jose, CA 95134
(any related inquiries can be sent to register@mos-ak.org)
Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems
in a special issue of the International Journal of High Speed Electronics and Systems
Extended MOS-AK Committee
WG211117
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Three-dimensional vertical Si nanowire MOS capacitor #model structure for the study of electrical versus... https://t.co/vekyZr5RmC
Three-dimensional vertical Si nanowire MOS capacitor #model structure for the study of electrical versus... https://t.co/vekyZr5RmC
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November 21, 2017 at 04:49PM
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Three-dimensional vertical Si nanowire MOS capacitor #model structure for the study of electrical versus geometrical Si nanowire characteristics https://t.co/OnvqDTh6l2
Three-dimensional vertical Si nanowire MOS capacitor #model structure for the study of electrical versus geometrical Si nanowire characteristics https://t.co/OnvqDTh6l2
— Wladek Grabinski (@wladek60) November 21, 2017
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November 21, 2017 at 04:48PM
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Nov 16, 2017
#Banks are increasingly turning to #opensource projects. Here’s why. https://t.co/FHoU5O7jdZ
#Banks are increasingly turning to #opensource projects. Here’s why. https://t.co/FHoU5O7jdZ
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Innovations in Electronics and Communication Engineering
Proceedings of the Fifth ICIECE 2016
Volume 7 of Lecture Notes in Networks and Systems
H. S. Saini, R. K. Singh, K. Satish Reddy
Springer, 8 Nov 2017 - Technology & Engineering - 596 pages
ISBN 9811038120, 9789811038129
The book contains high quality papers presented in the Fifth International Conference on Innovations in Electronics and Communication Engineering (ICIECE 2016) held at Guru Nanak Institutions, Hyderabad, India during 8 and 9 July 2016. The objective is to provide the latest developments in the field of electronics and communication engineering specially the areas like Image Processing, Wireless Communications, Radar Signal Processing, Embedded Systems and VLSI Design. The book aims to provide an opportunity for researchers, scientists, technocrats, academicians and engineers to exchange their innovative ideas and research findings in the field of Electronics and Communication Engineering [read more...]
Nov 14, 2017
The Pentagon is set to make a big push toward #opensource software next year https://t.co/EMWCKvEoQM
The Pentagon is set to make a big push toward #opensource software next year https://t.co/EMWCKvEoQM
— Wladek Grabinski (@wladek60) November 14, 2017
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November 14, 2017 at 10:45PM
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3 #opensource alternatives to AutoCAD https://t.co/ysUQCGiq8X https://t.co/V68oi64jF3
3 #opensource alternatives to AutoCAD https://t.co/ysUQCGiq8X http://pic.twitter.com/V68oi64jF3
— Wladek Grabinski (@wladek60) November 14, 2017
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7th All-Russian Workshop on CAD of IC Design
7th All-Russian Workshop on computer aided design (CAD) of integrated circuits (IC) to be held at NRNU MEPhI on December 12-14, 2017. The free workshop is organized by NRNU MEPhI jointly with Cadence Design Systems. The program and further information about the Workshop is available via site cad.mephi.ru.
Program
(with timetable and detailed information in pdf format)
12 December 2017
| 08:45 - 09:15 | Registration (University entrance) |
| 09:30 - 13:00 | Conference hall 3rd floor of the main lecture building |
| - Synthesis in Genus (28nm technology) | |
| - Introduction to Joules | |
| - Innovus 17.1 Topical Introduction | |
| 13:00 - 14:00 | Lunch break |
| 14:00 - 18:15 | Conference hall 3rd floor of the main lecture building |
| - Introduction to Stylus | |
| - Physical verification with the help of PVS | |
| - A new generation of verification software - Xcelium and Indago | |
| - The history and future of megatrends in EDA |
| 9:00 - 18:00 | Laboratory V-315 of the Department of Electronics (Practical classes) |
| - Behavioral modeling | |
| - Logical synthesis | |
| - Simulation of a Verilog modules with element delays | |
| - Physical design of the digital modules | |
| - Verification of the digital modules |
| 10:00 - 12:00 | Laboratory V-315 of the Department of Electronics |
| - Working discussions, summarizing |
Contact Event Secretary: E. Atkin
+7 495 7885699 ext. 9155
+7 499 3242597
Nov 11, 2017
#paper A temperature‐dependent surface potential‐based algorithm for extraction of Vth in homojunction TFETs https://t.co/uhg1laMLY2
#paper A temperature‐dependent surface potential‐based algorithm for extraction of Vth in homojunction TFETs https://t.co/uhg1laMLY2
— Wladek Grabinski (@wladek60) November 11, 2017
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November 11, 2017 at 07:15PM
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#Tesla-inspired Chinese EV startup launches all-electric SUV using #opensource patents https://t.co/LYByI2RCyr
#Tesla-inspired Chinese EV startup launches all-electric SUV using #opensource patents https://t.co/LYByI2RCyr
— Wladek Grabinski (@wladek60) November 11, 2017
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November 11, 2017 at 09:39AM
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Nov 7, 2017
ngspice release 27, September 17th, 2017 https://t.co/0jSKnj19no #Modeling https://t.co/c5INhqX0yD
ngspice release 27, September 17th, 2017 https://t.co/0jSKnj19no #Modeling http://pic.twitter.com/c5INhqX0yD
— Wladek Grabinski (@wladek60) November 7, 2017
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Nov 6, 2017
A Near-Threshold Voltage Oriented Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS https://t.co/OOQYhqgx9U #paper
A Near-Threshold Voltage Oriented Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS https://t.co/OOQYhqgx9U #paper
— Wladek Grabinski (@wladek60) November 6, 2017
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November 06, 2017 at 08:26PM
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Nov 3, 2017
[paper] Validation of MOSFET Model Source–Drain Symmetry
Validation of MOSFET Model Source-Drain Symmetry
Colin C. McAndrew
IEEE TED, Vol. 53, No. 9, Sep. 2006
doi: 10.1109/TED.2006.881005
doi: 10.1109/TED.2006.881005
Abstract: Symmetry around Vds= 0 is a critical requirement for MOSFET models, e.g. as it affects the ability of a model to simulate distortion accurately for some RF CMOS mixers. The Gummel symmetry test (GST) has been the standard test used to evaluate the symmetry of MOSFET models. However, this test is only applicable to DC current, and is only valid when there is negligible gate or substrate current. This paper presents a DC symmetry test that is applicable in the presence of gate and substrate currents, and an AC symmetry test that is simple and effective in verifying symmetry of Cgs and Cgd.
FIG: Biasing scheme for dc symmetry testing.
Nov 2, 2017
Circuit-aging #modeling based on dynamic MOSFET degradation and its verification (#SISPAD) https://t.co/QgJ5UIe7Yx
Circuit-aging #modeling based on dynamic MOSFET degradation and its verification (#SISPAD) https://t.co/QgJ5UIe7Yx
— Wladek Grabinski (@wladek60) November 2, 2017
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November 02, 2017 at 10:43AM
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Analytical #modeling is both science and art https://t.co/DBdMqRJqkU https://t.co/G45cufzKTb
Analytical #modeling is both science and art https://t.co/DBdMqRJqkU http://pic.twitter.com/G45cufzKTb
— Wladek Grabinski (@wladek60) November 2, 2017
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November 02, 2017 at 10:07AM
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#Modeling of flicker noise in quasi-ballistic FETs - IEEE Conference Publication https://t.co/JpropPaK27
#Modeling of flicker noise in quasi-ballistic FETs - IEEE Conference Publication https://t.co/JpropPaK27
— Wladek Grabinski (@wladek60) November 2, 2017
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November 02, 2017 at 10:05AM
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Circuit-aging #modeling based on dynamic MOSFET degradation and its verification - IEEE Conference Publication https://t.co/QnZG525Y7R
Circuit-aging #modeling based on dynamic MOSFET degradation and its verification - IEEE Conference Publication https://t.co/QnZG525Y7R
— Wladek Grabinski (@wladek60) November 2, 2017
from Twitter https://twitter.com/wladek60
November 02, 2017 at 10:04AM
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Oct 31, 2017
[mos-ak] [2nd Announcement and Call for Papers] 10th International MOS-AK Workshop in the Silicon Valley
10th International MOS-AK Workshop
(co-located with the CMC Meeting and IEDM Conference)
http://www.mos-ak.org/silicon_valley_2017/
Silicon Valley, December 6, 2017
2nd Announcement and Call for Papers
Together with local organization teams Cadence Design Systems and Keysight Technologies as well as International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and all the Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Compact Modeling Workshop which will be organized for consecutive 10th time in the timeframe of coming IEDM and CMC Meetings.
Planned,10th MOS-AK workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.
Important Dates:
Topics to be covered include the following among other related to the compact/SPICE modeling :
Online Workshop Registration
Postworkshop Publications:
Extended MOS-AK Committee
Planned,10th MOS-AK workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.
Important Dates:
- Call for Papers - Sept. 2017
- 2nd Announcement - Oct. 2017
- Final Workshop Program - Nov. 2017
- MOS-AK Workshop - Dec.6, 2017
Cadence Design Systems2655 Seely AveSan Jose, CA 95134
Topics to be covered include the following among other related to the compact/SPICE modeling :
- Compact Modeling (CM) of the electron devices
- Advances in semiconductor technologies and processing
- Verilog-A language for CM standardization
- New CM techniques and extraction software
- Open Source TCAD/EDA modeling and simulation
- CM of passive, active, sensors and actuators
- Emerging Devices, TFT, CMOS and SOI-based memory cells
- Microwave, RF device modeling, high voltage device modeling
- Nanoscale CMOS devices and circuits
- Technology R&D, DFY, DFT and reliability/ageing IC Designs
- Foundry/Fabless Interface Strategies
(any related inquiries can be sent to papers@mos-ak.org)
Online Workshop Registration
(any related inquiries can be sent to register@mos-ak.org)
Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems
in a special issue of the International Journal of High Speed Electronics and Systems
Extended MOS-AK Committee
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[paper] Review of physics-based compact models for emerging nonvolatile memories
Nuo Xu1, Pai-Yu Chen2, Jing Wang1, Woosung Choi1, Keun-Ho Lee3, Eun Seung Jung3, Shimeng Yu2
Review of physics-based compact models for emerging nonvolatile memories
1Device Lab, Samsung Semiconductor Inc., San Jose, CA 95134, USA
2School of ECEE, Arizona State University, Tempe, AZ 85281, USA
3Semiconductor R&D Center, Samsung Electronics, Hwasung-si, Gyeonggi-do, Korea
Journal of Computational Electronics, 2017, pp. 1-13
https://doi.org/10.1007/s10825-017-1098-0
Abstract: A generic compact modeling methodology for emerging nonvolatile memories is proposed by coupling comprehensive physical equations from multiple domains (e.g., electrical, thermal, magnetic, phase transitions). This concept has been applied to three most promising emerging memory candidates: PCM, STT-MRAM, and RRAM to study their device physics as well as to evaluate their circuit-level performance. The models’ good predictability to experiments and their effectiveness in large-scale circuit simulation suggest their unique role in emerging memory research and development [read more...]
https://doi.org/10.1007/s10825-017-1098-0
SSCS Members Who Are 2017 IEEE Fellows
SSCS members who are IEEE Fellows pose with SSCS President, Jan Van der Spiegel and IEEE President, Karen Bartelson at ISSCC 2017. From left to right- Jan Van der Spiegel, Zhihua Wang, Andrei Vladimirescu, Carlo Samori, Borivoje Nikolic, Junichi Nakamura, Deog-kyoon Jeong, Hideto Hidaka, Payam Heydari, Edoardo Charbon, and Karen Bartleson
Oct 30, 2017
How to pick a #winning #IoT #business #model https://t.co/YjMfxPAEZB https://t.co/SDOt080Ka6
How to pick a #winning #IoT #business #model https://t.co/YjMfxPAEZB http://pic.twitter.com/SDOt080Ka6
— Wladek Grabinski (@wladek60) October 30, 2017
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October 30, 2017 at 03:39PM
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FOSDEM 2018 CAD and Open Hardware Devroom Call for Participation
(Also visible at https://www.ohwr.org/projects/ohr-meta/wiki/FOSDEM2018)
This is the call for participation in the FOSDEM 2018 devroom on Computer Aided Design (CAD) tools and Open Hardware, to be held on Saturday 3 February 2018 in Brussels, Belgium. We are looking for contributions under the form of talks and tutorials covering the following main topics:
- Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
- Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce,GHDL, Icarus and Verilator)
- Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen) and HDL synthesis tools (e.g. Yosys)
- Field solvers such as openEMS
- Mechanical 2D and 3D CAD tools such as LibreCAD, FreeCAD, OpenSCAD andSolveSpace
- Open Hardware projects such as the Teres laptop and the lowRISC SoC
- Inter-project opportunities for collaboration
We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS CAD and Open Hardware developments, share knowledge and identify opportunities to collaborate on development tasks. This devroom is an evolution of the EDA devroom we organised in 2015, 2016 and 2017.
The submission process: Please submit your proposals at
https://penta.fosdem.org/submission/FOSDEM18 before 1 December 2017.
If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself under Person -> Description -> Abstract. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "CAD and Open Hardware Devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.
Important dates
- 1 December 2017: deadline for submission of proposals
- 8 December 2017: announcement of final schedule
- 3 February 2018: devroom day
Recordings: The FOSDEM organisers hope to be able to live-stream and record all the talks. The recordings will be published under the same licence as all FOSDEM content (CC-BY). Only presentations will be recorded, not informal discussions and whatever happens during the lunch break. By agreeing to present at FOSDEM, you automatically give permission to be recorded. The organisers will agree to make exceptions but only for exceptional and well-reasoned cases.
Mailing list: Feel free to subscribe to the mailing list of the CAD and Open Hardware devroom to submit ideas, ask questions and generally discuss about the event:
Spread the word!
Oct 26, 2017
#Modeling the Performance of Nano Machined CMOS Transistors for Uncooled IR Sensing https://t.co/p4RnuHkJiZ
#Modeling the Performance of Nano Machined CMOS Transistors for Uncooled IR Sensing https://t.co/p4RnuHkJiZ
— Wladek Grabinski (@wladek60) October 26, 2017
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October 26, 2017 at 11:26AM
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Oct 25, 2017
UNIST Researchers Develop Highly Stable #Perovskite #Solar #Cells https://t.co/g1CN5I44r1 #paper... https://t.co/WSUSekJ1ky
UNIST Researchers Develop Highly Stable #Perovskite #Solar #Cells https://t.co/g1CN5I44r1 #paper... https://t.co/WSUSekJ1ky
— Wladek Grabinski (@wladek60) October 25, 2017
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October 25, 2017 at 08:47PM
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UNIST Researchers Develop Highly Stable #Perovskite #Solar #Cells https://t.co/g1CN5I44r1 #paper https://t.co/p6Jr0nPqF1
UNIST Researchers Develop Highly Stable #Perovskite #Solar #Cells https://t.co/g1CN5I44r1 #paper http://pic.twitter.com/p6Jr0nPqF1
— Wladek Grabinski (@wladek60) October 25, 2017
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October 25, 2017 at 08:47PM
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Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper https://t.co/LglxkaZ9PP
Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper https://t.co/LglxkaZ9PP
— Wladek Grabinski (@wladek60) October 25, 2017
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October 25, 2017 at 11:59AM
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Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper
Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper
— Wladek Grabinski (@wladek60) October 25, 2017
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October 25, 2017 at 11:59AM
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