More papers

Another paper: Arbitrary Density of States in an Organic Thin-Film Field-Effect Transistor Model and Application to Pentacene Devices. After reading it, I've been left with the feeling that they have done a lot of very good work, but that the results are somehow quite similar to those that one can obtain with the old good RPI model. Probably it is my fault, but it seems too much work to end up with a gds that is not accurate, and with a fitting comparable to RPI. However, I repeat, the work is quite good and the problems I mention are mainly due to problems with the parameter extraction.

More Organic Circuits

I'm sorry, but this is quite out of topic. One of my personal obsessions are organic circuits, and this month the IEEE Journal of Solid-State Circuits publishes two very promising papers:
A 13.56-MHz RFID System Based on Organic Transponders
and the other one:
An Organic FET SRAM With Back Gate to Increase Static Noise Margin and Its Application to Braille Sheet Display
This means that it is more and more important having good models for plastic electronics. And this does not mean that we should be able to predict (more or less) the static curves, but also the gm and gds and, more and more important, the capacitances. This must be done if we are to implement full systems-on-display, as it seems to be the trend.

Some papers

I've been reading some new papers, and I've found some worth noticing:

The first one (Statistics of Grain Boundaries in Polysilicon),from H. Watanabe, is a quite interesting paper, discussing the application of statistics to a MOSFET model. I believe that the idea is applicable not only to bulk MOS, like he does, but it is somehow the path to follow for all the models devoted to devices where a signifiant parameter dispersion is expected. In fact, I think that this is a better way to face the problem than the one proposed by the EKV model, where they proposed a model for the deviations of the parameters.

And tomorrow, more...

SISPAD 2007

The 2007 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) will be held this year in Vienna (Sept 25-27 2007), organized by TU-Wien (Technische Universität Wien). SISPAD is considered one of the top conference on device and process simulation.

You can find all the information in:

www.sispad.org

The topics of SISPAD include all kinds of modeling techniques.

I want to remark that, according to the CFP, one of the topics is "Compact device modeling for circuit simulation".

For compact model developers, SISPAD can be a very attractive forum to present new developments and results, and to interact with researchers working in numerical and predictive process and device simulation.

Besides, there are two interesting companion workshops:
1) Workshop on Electromigration Reliability (Sept 24)
2) Workshop on Organic Electronics (Sept 28)

Of course, it is also a good opportunity to enjoy the wonderful city of Vienna!

How many angels can dance on top of a pin?

Two weeks ago I was in Rome, in the ITC. As you can guess from the title, I had a quite interesting, but byzantine, discussion. I was presenting a paper (with B. Iniguez, M. Shur and some other people) about a universal procedure to model TFT. The core idea of the procedure is using a compact model to model an intrinsic device, and then model all the rest of the parasitic elements as lumped elements. The other guy was telling me that this is not physical. Obviously, I don't agree. Moreover, I think that using lumped elements is near as physical as it can get.
My point is: it is OK trying to put everything inside your equations. However, this usually leads to a loss of insight on what is happening in the field-effect device. I think it is better to model the device with as much accuracy as possible and without losing the insight, and then add as many elements as necessary as lumped elements. Thus, the resulting model will have a quite straight physical representation, easy to grasp by intuition, and will not lose precision due to any approximation. Moreover, the simulator will handle quite effectively the model, because it has been programed to do so. Probably, it will even behave better, because the equations will be easier to handle.
Anyway, it is only my opinion, and there are some argements in the other side that I'll discuss another day.

RF Simulators

I've seen that Agilent Technologies announces a breakthrough in high-frequency SPICE simulation technology for high-speed digital board design. It seems that they have just realized that simulation in the frequency domain is faster than that in time domain. I don't grasp the novelty of the news, because they have been doing so for a long time. However, the point I'd like to make is that a good model for RF design not only has to be accurate, etc.... but it also has to take into account the possibility of being used in a simulator oriented to frequency.
It seems then that in a good model to be used in an RF environment, we should be careful enough as to explicitly state the equations for the S parameters, and not only for the capacitances. Thus, we should present both versions of the model: one with the capacitances, and another one with the S-parameters. It would be then a question of choosing the most appropriate set of equations to simulate.

Back to work

Here I am, back to real world after two weeks of conferences. I must confess that I'm happy to be at home again. Well, to the point. The last one of the conferences was a bit disappointing, because it was mainly dedicated to solar cells in the oral sessions. This is so because it was organized by the Solar Energy Institute. The poster sessions were more interesting, with many different topics, though the only ones dedicated to compact modeling were some posters from B. Iñiguez and Toni Lazaro, dedicated mainly to double gate and RF modeling. Quite interesting, even if they didn't win the best paper award (by the way, only five of the six awards went to people related to the organizers).
Another poster I was happy to see was one about pi-gate FETs, where they were modeling the transistor using some device simulator. The funny thing was to see the double threshold effect, with some explanantions about it.

IET (former IEE) Award

Today I've learnt that the Institution of Engineering and Technology has awarded the Circuits, Devices and Systems Premium, to B. Iniguez, J. Deen and O. Marinov, for the paper “Charge Transport in Organic and Polymer Thin-Film Transistors: Recent Issues”.

Congratulations!

CDE in Madrid

Today I'm leaving for the CDE in Madrid. It is a Spanish conference, though with many international attendants. This year it is mainly focused on photonics, but there are many papers (and posters) on compact modeling. I'll report on this conference next week, with some comments on the best (under my own criteria) papers.

About the ITC'07 in Rome

Well, it has been a little bit disappointing, because though there were near 100 works, only four of them were on compact modeling. However, the rest of all has been very interesting, and I've learn more than I ever wanted to know about fabrication processes...
Once everything is added up, I'd like to point out some papers: one of Plastic Logic, Ltd where they were presenting statistics about defects in their fabricated circuits (panels), and another from Canon and the Tokyo Institute of Technology.
The latter was about parameter dispersion on TFT, one thing I believe to be quite forgotten about in compact modeling and very (VERY) important for design. The paper is good, but it lets out many things (effects of separation, orientation, mismatch in size, correlations among variations, etc...) However, it is a good start.

The European Network of Excellence "SINANO" addressed Compact Modelling of Multiple-Gate MOSFETs

From January 2004 to December 2006, a number of European teams have been working together in a Network of Excellence called SINANO, devoted to the study of novel structures of Silicon nanodevices.

The work has included technology, characterization, advanced simulation and compact modeling of novel structures of nanoscale MOSFETs.

The compact modeling work has especially addressed Multuple-Gate MOSFETs, in particular Double-Gate (DG) and Gate All Around (GAA) MOSFETs. The joint effort on compact modeling has led to several publications in international journals and conference proceedings.

Among the compact modeling publications carried out under the umbrella of the SINANO Network of Excellence, I want to mention the following paper, which was invited to the Special Issue on Advanced Compact Models and 45-nm Modeling Challenges, of IEEE Transactions on Electron Devices:
B. Iñiguez, T. A., Fjeldly, A. Lazaro, F. Danneville and M. J. Deen, “Compact-modeling solutions for nanoscale double-gate and gate-all-around MOSFETs,” IEEE Trans. on Electron Devices, vol 53, no. 9, pp. 2128-2142 September 2006

(This is an excellent review of the compact modeling work carried so far in Multiple-Gate devices and provides very interesting solutions for a 2-D or 3-D analytical model)

ITC in Rome

Well, today I'm leaving for the International Thin-Film Transistor in Rome, so the blog is going to be un-updated until I come back. However, I promise a (quite) full report when I return.

A historical note

This post is a historical hint. This weekend I've been surfing the internet, and I've been looking for some pages on Spice history. Why Spice? Well, all of you know that if spice (or similar) didn't exist, then probably the semiconductor revolution wouldn't have taken place. The first link is to the wikipedia, where they put a quite extensive article about it, including even a list of commercial and free simulators. Only a little comment: In the list they include Eldo, and I think that I should note that, while Eldo is in fact a simulator, it is one of the few that is not Spice-based. Another link is to the page of ecircuitcenter, where they put quite the same information, but in the format of list, which is maybe clearer.

The basic facts about the name "Spice" are few: created as a class project by Larry Nagel (under supervision of Ron Rohrer) it was first called CANCER (Computer Analysis of Non-Linear Circuits Excluding Radiation), because of the time it was created. In 1972 (yes, that's before I was born...), the final name SPICE (Simulation Program with IC Emphasis) was introduced. And that's all about the name. Another day, I'll talk about other features of this simulator.

Language of choice

I agree with the post from Marek Mierzwinski (below) from Tiburon Design Automation. Moreover, we people working on compact modelling should agree to use all the same language of choice. However, the nice thing about standards is having so many to choose from...

Anyway, there is a question I would like to point out: model development should be done in a language that allows easy integration with commercial simulators. Up to here, both Verilog and HDLs meet the requirements. However, the last step for a model (when it comes of age or it has been accepted by the community as the ideal model for a given device), must be to be implemented in a (many) simulator as a built-in option. In this case, obviously, implementation must be done in some lower-level language like C/C++/Fortran/etc... Otherwise, the simulator will be too sloooooowwwww to simulate large circuits.

More DG

I've been looking at a not very known journal: the International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, from Wiley. I've found an useful paper from the EKV people: "Explicit modelling of the double-gate MOSFET with VHDL-AMS". It is in the vol 19, issue 3 (may/june 2006). It seems that going VHDL is the future for all those implementing models, at least in the first stages. I agree with this trend, because it is much easier to use than trying to tie your C-code inside programs like HSPICE or Intusoft's simulator IsSpice. Moreover, it is also easier to depure and also it is easier to test the models. In some days, I should post something about model testing...

In the same issue, there is also another interesting paper about accurate substrate modelling for RF applications.

Undoped Double-Gate MOSFETs

It seems that this is the star subject in compact modelling in both Solid-State Electronics from Elsevier and the IEEE Transactions on Electron Devices. I have seen at least four different papers on the subject.

I think that the more interesting one among them is "A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs", from Adelmo Ortiz-Conde et al. I believe this for two reasons: the first one is that it is very convenient having a review of the state-of-the-art from time to time, and the second reason is that they are, probably, one of the best people to do this review, because they were one of the first research groups to work on this subject.

An interesting grant offer

The Microelectronics National Center (in Barcelona, dependent on the Spanish Research Council (CSIC)) opened a call for proposals to allow external researchers the use of their installations. The grant offer may also include allocation fees. Interesting to all those interested, mainly, in MEMs.

Tanner

Nearly a year after they released the 11.2 version of Tanner Tools, they are releasing a new version 12.2. Why am I posting this? Because they were one of the first to implement the PSP model (I remind you that PSP was elected on november 2005 by the CMC as the new standard). However, I'd like to point out that no effort has been put into implementing the other finalist (HiSim) or even the BSIM5. Life is hard for loser models...

Plastic electronics

I've got a mail from a friend (Jamal Deen) with some very important news to all those working on plastic electronics: it seems that Plastic Logic has got some small cash (around 100.000.000'00 USD) to start a production facility in Dresden, Germany. They are planning to build the first commercial production plant of plastic electronics, starting in 2008 (yes, that is next year!). Look at their press release here.

The other news is that Polymer Vision (Philips' spin-off) will be starting the production of rollable displays as soon as this same year. See the press release here.

Well, big news for everybody. It seems that we're about to enter a new age in consumer electronics, that of flexible electronics. Changes are very likely to be huge, but this is good, don't you agree?

Simulators

Today, I'll talk about ngSpice. The link is a page dedicated to this free-source simulator (in fact, it is its homepage). there you can find anything you need to download and compile one of the best simulators going around. However, the point is not only that it is a very good simulator, but that you can also implement your models there. And it's for free.... If you need more, you can also go to the gEDA project, that is a full design suite. It is more oriented to simulation of circuits than to simulation of devices, but it can be useful to device people to check the model in a full design flow.

Conferences

A friend of mine (Benjamin Iñiguez) has sent me links to some important conferences regarding compact modeling. The first one is to be held on Yokohama, Japan on January 23, and it is called the 4th International Workshop on Compact Modeling (IWCM). Lots of interesting talks and many good research being presented there.

The second link is for the 2007 Workshop on Compact Modeling, to be held in Santa Clara on May, 20-24. Also lots of important people (Jamal Deen, Chenming Hu, Matthias Bucher, Tor Fjieldy, Benjamin Iñiguez, Adelmo Ortiz-Conde, etc..), so it is very possible that you will find lots of important results there.

Another conference is the CDE, in Spain. It is a national one, but many good people is going there.

Why models are useful

Have a look at this blog from David Rutledge. It explanins very clearly what models (as he says, in the sense used in the Semiconductor industry) are, and what are they used for. He explains many things about different kinds of models, including the whole design process. It is good to keep an eye on the whole process, and not to get too focused on the mathematical modeling of the transistors.

Happy new year!

Well, after the celebrations of New Year, it's now time to get again to the real life. There are lots of things to comment on.
The first thing is the effect of the earthquake on the semiconductor production capabilities of Taiwan and the neighbour countries. People says that these effectes have been "limited" (have a look at this link: it is a very good source of news). We'll see...
I'd like to comment also the work of one of my students: she passed her final project on december 22 (with very good marks...), and she is now a very happy telecom engineer. However, her project had little to do with telecommunications, because I was directing her and it is traditional in our university that the project is related to the research of the supervisor. The project was on comparing the goodness of different methods of fitting models to experimental results using genetic algorithms. She compared queen-bee with classical methods, plus a combination of both. Results were quite good. If you are interested, ask me...