Tuesday, January 23, 2007

The European Network of Excellence "SINANO" addressed Compact Modelling of Multiple-Gate MOSFETs

From January 2004 to December 2006, a number of European teams have been working together in a Network of Excellence called SINANO, devoted to the study of novel structures of Silicon nanodevices.

The work has included technology, characterization, advanced simulation and compact modeling of novel structures of nanoscale MOSFETs.

The compact modeling work has especially addressed Multuple-Gate MOSFETs, in particular Double-Gate (DG) and Gate All Around (GAA) MOSFETs. The joint effort on compact modeling has led to several publications in international journals and conference proceedings.

Among the compact modeling publications carried out under the umbrella of the SINANO Network of Excellence, I want to mention the following paper, which was invited to the Special Issue on Advanced Compact Models and 45-nm Modeling Challenges, of IEEE Transactions on Electron Devices:
B. IƱiguez, T. A., Fjeldly, A. Lazaro, F. Danneville and M. J. Deen, “Compact-modeling solutions for nanoscale double-gate and gate-all-around MOSFETs,” IEEE Trans. on Electron Devices, vol 53, no. 9, pp. 2128-2142 September 2006

(This is an excellent review of the compact modeling work carried so far in Multiple-Gate devices and provides very interesting solutions for a 2-D or 3-D analytical model)

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