Monday, 15 January 2007

More DG

I've been looking at a not very known journal: the International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, from Wiley. I've found an useful paper from the EKV people: "Explicit modelling of the double-gate MOSFET with VHDL-AMS". It is in the vol 19, issue 3 (may/june 2006). It seems that going VHDL is the future for all those implementing models, at least in the first stages. I agree with this trend, because it is much easier to use than trying to tie your C-code inside programs like HSPICE or Intusoft's simulator IsSpice. Moreover, it is also easier to depure and also it is easier to test the models. In some days, I should post something about model testing...

In the same issue, there is also another interesting paper about accurate substrate modelling for RF applications.

1 comment:

Anonymous said...

I think you're correct in saying that most compact model development will be done with HDLs; however, it's clear that Verilog-A (a subset of Verilog-AMS) will be the language of choice. Compiled versions of the language are supported in all major simulators (HSPICE, Spectre, ADS, Eldo). Also the language has specific features for compact models (for parameter management). Verilog-A has been recognized as an acceptable format for model description by the Compact Model Council. See http://www.eigroup.org/cmc/veriloga/default.htm.

Using Verilog-A for compact models should make it much easier to develop and distribute new or enhanced models.

Marek Mierzwinski
Tiburon Design Automation