Revolution EDA Mistral AI Experiments

Revolution EDA MistralAI Experiments

by Murat Eskiyerli  

There was a recent article by Prof Razavi, where the problems of Large Language Models in identifying various analogue integrated circuit blocks were recounted.

Revolution EDA uses structured JSON data format to store design files. JSON also happens to be very easy for LLMs to parse and understand. In fact, Mistral AI has a JSON mode. Mistral AI is the latest addition to the growing number of LLMs that Revolution EDA is able to use.

We did ask a few questions to Mistral AI to test its understanding of designs in Revolution EDA and its potential to help designers. The results have been very encouraging. The future analogue integrated circuit designers will be able to use large language models like Mistral AI to quickly gain understanding of a circuit and improve on it.

The transcription below is taken exactly from the interaction with Mistral AI except for small formatting changes [read more...]

2nd Semiconductor Device Frontier Summit

Date: May 18, 2026; Time: 10:00AM ~ 05:00PM

Ewha Womans University Student Culture Center (Small Theater B101)

The Semiconductor Device Research Group of the Society of Semiconductor Engineers has been holding this event since 2025 to strengthen human networks among domestic researchers and share the latest research trends.

This year's summit, now in its second year, invited top-notch speakers from various fields to provide a broad view of the latest technologies in industry and academia. It will be a place for meaningful academic exchanges to grasp the latest semiconductor technology trends as well as to share in-depth opinions on international market trends. This event is co-organized by the Society of Semiconductor Engineers and the IEEE EDS Seoul Section Chapter and aims to become an international event representing the semiconductor device field in Korea in the future. We ask for your interest and participation so that the 'Semiconductor Device Frontier Summit', which will be the core pillar of the Korean researcher network, can become the cornerstone of the development of our semiconductor industry.

Pre-registration deadline: Until May 16, 2026 (Saturday)

Time	Program
Opening Session
10:00 – 10:20	Welcome & Registration
10:20 – 10:30	Opening Remarks (Prof. Sung‑Jae Cho, Ewha Womans University)
Session 1 | Chair: Prof. Sung‑Jae Cho
10:30 – 11:15	Semiconductor Devices for the New Computing Era Prof. Woo‑Young Choi, Seoul National University
11:15 – 12:00	Development Strategy for AI‑Oriented NAND Solutions Prof. Ki‑Hwan Song, Yonsei University
12:00 – 13:30	Lunch
Session 2 | Chair: Prof. Myung‑Gon Kang
13:30 – 14:15	Trends and Outlook of eNVM Technology Visiting Prof. Yong‑Gyu Lee, Seoul National University
14:15 – 15:00	Memcapacitor Technology for Charge‑Domain PIM Implementation Prof. Tae‑Hyun Kim, Seoul National University of Science and Technology
15:00 – 15:10	Coffee Break
Session 3 | Chair: Prof. Il‑Hwan Cho
15:10 – 15:55	Atomically Thin 2D Semiconductor Electronics toward Beyond‑CMOS Technology Prof. Chul‑Ho Lee, Seoul National University
15:55 – 16:40	Orders‑of‑Magnitude Faster TCAD Device Simulation of GAA MOSFETs without Additional Computational Training Cost Prof. Sung‑Min Hong, GIST
16:40 – 17:00	Closing Ceremony | Prof. Il‑Hwan Cho, Myongji University

[chapter] Modeling of the MOSFETs

Jean-Marc Dienot, “A Review on Analytical and Electrical Modeling of the MOSFET Transistor”

Chapter 2 in "Field-Effect Transistors – Fundamentals, Technologies, and Future Applications"

Editor: Kenan Cicek

DOI: 10.5772/intechopen.1009040

ABSTRACT: Power semiconductor MOSFET and other MOS-controlled devices benefit from material and technology improvements to respond to high-level power features, high voltage, high current density, short switching times, and thermal constants, which optimize energy efficiency. These enhanced characteristics induce more electromagnetic noises and temperature-management constraints for the deployment of this technology. We describe synthetically modeling theory and technic, from basic-to-advanced, to derive predictive simulations for the power MOSFET challenging issues. Analytical and electrical circuit model of the MOSFET elementary cell at semiconductor level, time-domain simulation. Distributed and propagative model, including device packaging and power-printed circuit board (PPCB) PEEC and 3D model levels, signal integrity simulation, common mode emission simulation, and radiated field simulation. Electro-thermal model with thermal propagative network model coupled with electrical model at circuit level, time multi-domain simulation. Case studies on Power PCB with MOSFET Si et SiC illustrate modeling procedures.

FIG: Overeview of analytical equations of the MOSFETs

 

[Newsletter] Revolution EDA April 2026

Revolution EDA has two updates to share this month: 

• a browser-based cloud trial environment is now live, and 
• hierarchical Layout vs Schematic (LVS) verification has been added to the platform

Cloud Trial Environment

[paper] Open-Source SkyWater 130 nm MOSFETs at 77K

F. Beall1, A. Rimal1, O. Seidel1, Y. Mei1, A. D. McDonald3, I. Parmaksiz5,1 V. A. Chirayath1, J. Asaadi1, D. Braga2, J. B. R. Battat4

DC Cryogenic Modeling of Open-Source SkyWater 130 nm MOSFETs at 77K Using BSIM4

arXiv:2604.21625v1 [cond-mat.mes-hall] 23 Apr 2026

1 The University of Texas at Arlington, Physics Department, Arlington, TX 76019, USA
2 Fermi National Accelerator Laboratory, Microelectronics Department, Batavia, IL 60510, USA
3 Instrumentation Frontier Scientific, Arlington, TX 76019, USA
4 Wellesley College, Physics and Astronomy Department, Wellesley, MA 02481, USA
5 Rice University, Physics Department, Houston, TX 77005, USA

Abstract: Cryogenic applications in high-energy physics (HEP) demand reliable, low-power CMOS electronics capable of operating at liquid nitrogen temperatures (77K). The open-source SkyWater 130nm (SKY130) CMOS process has previously been shown to operate at temperatures as low as 4K making it a promising candidate for HEP applications. In this work, we characterize and model SKY130 low-threshold voltage transistors at 77K, which is a temperature commonly used in modeling applications for liquid argon detectors. DC characteristic measurements were performed at both room temperature and liquid nitrogen temperature. We created a cryogenic modeling approach to produce a SPICE-compatible, isothermal BSIM4-based model for select transistor sizes at 77K. The resulting model agrees with data at 77K with an average error on the order of 20% (relative RMS) and shows no dependence on drain voltage. Due to the open-source nature of SKY130, we have made our models publicly available on Github. We hope this work will continue the trend for democratizing circuit design at cryogenic temperatures in high-energy physics by enabling open access to accurate cryogenic CMOS device models at 77K.

Fig: Hardware setup used for I-V measurements: (a) Schematic of the I-V measurement

system (b) Wirebonded SKY130 chip mounted on PCB

Acknowledgments: The authors would like to thank various engineers in the microelectronics department at FNAL for their guidance and assistance on this project: Albert Dyer for help operating the cryo-cooler, and Louis Dal Monte and Pamela Klabbers for PCB design. The authors would also like to extend gratitude to Andy Pender from Synopsys for assistance with the modeling software, Mystic™. This material is also based upon work supported by U.S. Department of Energy, Office of Science, Office of High Energy Physics under Award Number DE-SC0022296 and DE-SC00253485 as well as support from the University of Texas at Arlington’s Center for Advanced Detector Technologies.