[poster] Active Cantilever with Dual Actuator

Bartosz Pruchnik1, Fabian Dietrich2, Richard Subianto2, Katerina Ivanova2, Athulya K. Muraleedharan Bindu2, Hans-Georg Pietscher2, Javad Basseri2, Muralikrishnan Brajesh Kaimal2, Władysław Kopczyński1, Wojciech Godlewski1, Dominik Badura1, Piotr Putek1, Krzysztof Kwoka1, Piotr Smagowski1, Andrew Yacoot3, Tomasz Piasecki1, Fangzhou Xia4, Ivo W. Rangelow2 

Active Cantilever with Dual Actuator

52nd International Micro and Nano Engineering Conference

Sep. 21-24, 2026 Interlaken (CH)

MEN2026 Poster S05A-T2-P-5

1. Wrocław University of Science and Technology,

2. nano analytik GmbH, 

3. National Physical Laboratory

4. University of Texas at Austin

Abstract: Atomic Force Microscopy (AFM) is often limited by the speed and bandwidth of three main components: the cantilever, the scanner, and the controller. Recent microelectromechanical systems (MEMS) have improved the performance of the cantilever and scanner by combining high-speed active cantilevers with low-latency scanners. In this work, we present a standardized active cantilever design. The system combines a large cantilever that acts as a Z-axis actuator with a smaller active cantilever sensor that provides a bandwidth greater than 400kHz. The smaller cantilever is integrated into the larger structure, creating a compact and highly responsive device. We introduce a new active cantilever architecture that uses two integrated electrothermal actuators. One actuator is used for cantilever operation, while the second provides vertical (Z-axis) movement for surface tracking. This design allows AFM measurements to be performed without the need for an external piezoelectric z-actuator.

Acknowledgements: This work was supported by the European Union's Horizon Europe research and innovation program under the Marie Sklodowska-Curie grant agreement No 101072775, and by the National Science Centre, Poland (grant No. 2021/41/B/ST7/03144).

[paper] Open Source EZ130 8T standard cell library

Oscar Castaneda, Lavinia Recchioni, Tobias Senti, Flurin Cahenzli, Marco Ferroni, Thorben Heekenjann, Robert Kenter, Stefan Odermatt, Daniel Richner, Gabriel Altendorfer, Davide Cannone, Miguel Correa, Ivan Herger, Lars Kroger, Nicolas Nanzer, Darja Nonaca, Christopher Reinwardt, Lukas Winklhofer, Enrico Zelioli, Yiheng Zhang, Yingxue Zhang, Domenic Keller, Seyed Hadi Mirfarshbafan, Zerun Jiang, Beat Muheim, Arianna Rubino, Jeremy Guichemerre, Frank K. Gurkaynak, and Christoph Studer

An Open-Source Standard-Cell Library for IHP 130 nm Developed by Students

arXiv:2609.29965v1 [cs.AR] 24 Sep 2026

1. Department of Information Technology and Electrical Engineering, ETH Zurich, Switzerland

* The open-source EZ130 8T standard-cell library is available at https://ez.ethz.ch

Abstract: Standard-cell libraries form the critical interface between transistor-level circuit design and automated digital design flows, yet their design and characterization are rarely covered in depth in digital VLSI courses. This paper presents VLSI 5, a graduate-level course at ETH Zurich in which students design, lay out, characterize, and integrate their own standard cells using IHP’s open-source 130 nm SG13G2 process design kit. In the first course offering, 19 students developed EZ130 8T, an open-source eight-track standard-cell library comprising 220 cells. We evaluate successive library versions using eight synthesis benchmarks, across which EZ130 8T achieves significant area reduction compared to the SG13G2 library at competitive timing. For a postlayout 8×8 matrix-vector multiplier, EZ130 8T reduces cell area by 35% and energy by 39% while maintaining virtually the same clock period. The library has already been adopted in other ETH Zurich VLSI courses, enabling the creation of chips entirely designed by students down to the transistor level.

FIG: a.) ETH Zurich course series on digital VLSI design. By teaching students to create a standard-cell library, the new VLSI 5 course closes the gap between transistor-level and HDL-level IC design;
b.) and c.) Layout of two example standard cells from the EZ130 8T library.

Aknowlegements: This work has received funding from the Swiss State Secretariat for Education, Research, and Innovation (SERI) under the SwissChips initiative. The authors thank Cadence for their support by providing licenses to design and characterize the EZ library. The authors also thank H. Pretl, T. Benz, and P. Sauter for their feedback on preliminary versions of the EZ library.

[paper] n-MOS pseudo-resistor nA current reference

Bruni, Italo, Mariane Petraglia, and Fabián Olivera

Area-efficient nanoampere current reference employing

a temperature-controlled n-MOS pseudo-resistor

AEU IJ EC (2026): 156642.

DOI: 10.1016/j.aeue.2026.156642

Abstract: This paper presents a CMOS current reference topology that avoids the use of large-area resistors by using a temperature-controlled pseudo-resistor. The proposed technique for achieving a reference current consists of applying proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) voltages to the drain and gate of an n-MOS EKV-based pseudo-resistor, respectively, thereby stabilizing its current against temperature variations. Two current reference design versions, namely D01 and D02, were implemented using a 180 nm technology. Extensive post-layout simulation results for design D01 show a typical reference current of 6.30 nA, an average temperature coefficient (TC) of 414 ppm/C (nominal 219 ppm/C) across a range from −40C to 120C, and a line regulation (LR) of 11.76 %/V. To improve LR, design D02 was developed, achieving a significantly optimized LR of 0.33 %/V while maintaining a typical current of 6.22 nA and an average TC of 401 ppm/C (nominal 191 ppm/C) over the same temperature range. The area-efficient technique enables compact silicon areas of 0.0018 mm2 and 0.0020 mm2 for D01 and D02, respectively.

FIG: Schematics of the CTAT voltage generator topologies: .a) 3T; b.) 6T

and its layout implementation of the current reference designs: c.) D01; d.) D02.

Acknowledgment: This work was supported in part by the Brazilian research funding agencies CNPq, FAPERJ, and Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - Brasil (CAPES) Finance Code 001; by grant 307092/2025-9, funded by CNPq/MCTI/FNDCT N∘18/2024; and by grant E-26/204.222/2025 (SEI-260003/020616/2025), founded by FAPERJ JCNE .

[webinar] Colombia in OpenSilicon Age

IEEE SSCS: Colombia in OpenSilicon Age

• Date: Thursday, October 8, 2026
• Time: 1:00 PM – 2:30 PM (Colombia, GMT-5)
• Platform: Cisco Webex
• Access: Free/Open access

This open online event is the first IEEE SSCS Colombia session. It shares a vision for creating a strong microelectronics ecosystem in Colombia by bringing universities and industry together and helping develop highly skilled engineers. The event will review the current state of microelectronics in Colombia, discuss the future of integrated circuit (IC) design, present recent semiconductor policy initiatives, and explain the goals of the IEEE SSCS Colombia chapter. Speakers from Colombia and abroad will share their experience in IC design, open-source silicon, semiconductor education, and industry development. The session aims to encourage collaboration between academia, industry, and government to support the growth of the semiconductor sector in Colombia.

Featured Panelists and Keynote Speakers

• Made in Colombia: Review of Colombian Microelectronics
  Javier Ardila, Onsilicon, UIS and President, IEEE SSCS
• ColombiaThe Global Map of CI Design: Tools, Foundry and Methodology
  Hugo Hernández, Teradar, Boston, MA
• OpenSilicon Opportunities
  Fernando Guarín IEEE Division 1
• Bill for the promotion of the electronics and semiconductor industry
  Lorena García Founder, Colombian Network of Electronics and Semiconductors

IEEE LA & Caribbean Semi Summit

IEEE Latin America & the Caribbean

Semiconductor Summit

LACSS 2026 will bring together leaders from industry, government, academia, research institutions and the investment community to explore Latin America and the Caribbean’s role in the rapidly evolving global semiconductor ecosystem.

The two-day (Oct. 1-2) program will examine regional capabilities and opportunities across semiconductor design, talent development, advanced manufacturing, packaging and testing, supply chains, investment, public policy, research, critical technologies and international cooperation. The IEEE EDS/CASS MQ Semiconductors in Latin America will follow on the third day (Oct.3)

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DAY 1 — Academia and Industry: Building Talent, Research and Innovation
Thursday, October 1st, 2026

Opening
08:30–09:00	Opening Ceremony Ivan Armuelles, Chair IEEE LACSS 2026 Juan Pimiento, SENACYT, Panama
09:00–09:30	Overview of the Semiconductor Industry Today and Opportunities for Latin America through the IEEE Open Silicon Initiative Fernando Guarin, IEEE Division I, Director - GlobalFoundries (Retired) / IBM (Retired), USA
Building Semiconductor Talent: National Experiences from Latin America Moderator: Fernando Guarín, IEEE
09:30–09:50	Building Panama's National Semiconductor Talent Pipeline Zoila De Castillo, C-TASC, Panama
09:50–10:10	Brazil´s Semiconductor Industry and Design House Ecosystem Jacobus Swart, University of Campinas (UNICAMP) / INCT NAMITEC, Brazil
10:10–10:30	The Kutsari initiative and strategy for the future (virtual) Edmundo Gutierrez, Kutsari (National Center for Semiconductor Design in Mexico), Mexico
10:30–11:00	Networking Coffee Break
Electronic Design Automation Moderator: Ricardo Reis, UFRGS, Brazil
11:00–12:30	Panel: EDA Innovation and Latin America’s Role in the Global Semiconductor Ecosystem Antonio de la Serna, Siemens EDA Victor Grimblatt, Synopsys Marcelo Da Silva, Cadence
12:30–14:00	Lunch
Talent Development and Industrial Capabilities Moderator: Carlos Silva, PUCP, Peru
14:00–14:30	Talent: the keyword for the development of semiconductors Ricardo Reis, Institute of Informatics, Federal University of Rio Grande do Sul (UFRGS), Brazil
14:30–15:45	Panel: Preparing Semiconductor Talent–Industry and University Experiences Rodrigo Jaramillo, Circuify Semiconductors, Mexico Alfredo Arnaud, Universidad Católica del Uruguay, Uruguay Victor Grimblatt, Synopsys, Chile Amílcar Josué Véliz Solares, Universidad Galileo, Guatemala Javier Marte Michelen, Pontificia Universidad Católica Madre y Maestra, Dominican Republic
15:45–16:15	Networking Coffee Break
16:15–16:45	Assembly, Testing and Packaging: Opportunities for Latin America Joel Molina, INAOE, Mexico
Day 1 Wrap-up
16:45–17:00	Day 1 Wrap-Up Ivan Armuelles, Chair IEEE LACSS 2026
18:00–20:00	Welcome Reception (off-site) La Casa - Ciudad del Saber

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DAY 2 — Government and Industry: Policy, Investment and Regional Strategy
Friday, October 2nd, 2026

08:30–08:45	Day 2 Kick-off Start of Day 2: summary of the previous day and agenda of the day
Global Policy, Cooperation and Investment Moderator: Erik Heilman, IEEE-USA
08:45–09:30	Global Policy Perspectives for Semiconductor Development Filipe Silva, Semiconductors Team Lead, OECD (virtual)
09:30–10:00	Pax Silica and the Global Semiconductor Ecosystem: Implications for Latin America and the Caribbean (virtual) Akhil Ramesh, PAC Forum
10:00–10:30	Panama’s Semiconductor Strategy (TBC) Victor Sanchez, C-TASC AIP, Panama
10:30–11:00	Networking Coffee Break
The Semiconductor Policy Playbook: Regulation, IP and Regional Development Moderator: TBC
11:00–12:20	Panel: Policies and Partnerships for Latin American Semiconductor Ecosystems Adão Villaverde, Brazil Mayté Milián, Guatemala Nestor García Romero, Mexico Lorena Garcia, Colombia
12:20–12:30	IEEE Division I–Synopsys MoU Signing Ceremony: Semiconductor Workforce Development Fernando Guarín, IEEE Division I Victor Grimblatt, Synopsys
12:30–14:00	Lunch
Semiconductor Design, Manufacturing and Entrepreneurship Moderator: Lorena Garcia, Alianza E, Colombia
14:00–15:30	Panel: Building Semiconductor and Hardware Businesses in Latin America Rodrigo Jaramillo, Circuify Semiconductors, Mexico Israel Mejia, QSM, Mexico (virtual) Gabriel Ortiz, Pixart, Argentina Alfonso Chacon, Rydev, Costa Rica Javier Ardila, OnSilicon, Colombia (virtual)
15:30–16:00	Networking Coffee Break
Expanding Access to Semiconductor Design, Prototyping and Manufacturing Moderator: Joel Molina, INAOE, Mexico
16:00–17:00	Panel: Expanding Access to Semiconductor Design, Prototyping and Manufacturing Pat Deegan, Tiny Tapeout Mitchell Hsing, InchFab Alfonso Torres, INAOE (virtual)
FET 100 Moderator: Arokia Nathan, IEEE EDS, USA
17:00–17:45	FET100 Speakers: Fernando Guarin, Jacobus Swart.
17:45–18:00	Closing - LACSS 2027 announcement Ivan Armuelles Ricardo Reis
18:00	End of LACSS

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DAY 3 — 2026 IEEE EDS/CASS MQ Semiconductors in Latin America
Saturday, October 3rd, 2026

Universidad De Panama Auditorio (Piso 3), Facultad De Informática, Electrónica Y Comunicación

	IEEE EDS/CASS MQ Session:  Exploring Innovation, Research, and Opportunities for a Semiconductor Future in the Caribbean
8:00–8:15	Opening Ceremony — Registration and Welcome Remarks
8:15–8:45	Low Power Design for Sustainable Manufacturing in Agribusiness Victor Grimblatt
8:45–9:15	Embedded Timing: A New Scaling Layer for Compute at System Scale Rodrigo Calderon
9:15–9:45	Reliability Topics for Advanced Semiconductors Fernando Guarin
9:45–10:15	Physical Design Automation: From Past to Future Ricardo Reis
10:15–10:45	Networking Coffee Break
10:45–11:15	Brazil’s Semiconductor Industry and Design House Ecosystem Jacobus Swart
11:15–11:45	Oxide Electronics Arokia Nathan
11:45–12:15	Dielectrics Materials from Field Effect Transistors to In-Memory Computing Durga Misra
12:15–13:30	Lunch