Showing posts with label Summit. Show all posts
Showing posts with label Summit. Show all posts

Oct 1, 2026

IEEE LA & Caribbean Semi Summit

IEEE Latin America & the Caribbean
Semiconductor Summit

LACSS 2026 will bring together leaders from industry, government, academia, research institutions and the investment community to explore Latin America and the Caribbean’s role in the rapidly evolving global semiconductor ecosystem.

The two-day (Oct. 1-2) program will examine regional capabilities and opportunities across semiconductor design, talent development, advanced manufacturing, packaging and testing, supply chains, investment, public policy, research, critical technologies and international cooperation. The IEEE EDS/CASS MQ Semiconductors in Latin America will follow on the third day (Oct.3)

DAY 1 — Academia and Industry: Building Talent, Research and Innovation
Thursday, October 1st, 2026

Opening

08:30–09:00

Opening Ceremony

Ivan Armuelles, Chair IEEE LACSS 2026

Juan Pimiento, SENACYT, Panama

09:00–09:30

Overview of the Semiconductor Industry Today and Opportunities for Latin America through the IEEE Open Silicon Initiative
Fernando Guarin, IEEE Division I, Director - GlobalFoundries (Retired) / IBM (Retired), USA

Building Semiconductor Talent: National Experiences from Latin America

Moderator: Fernando Guarín, IEEE

09:30–09:50

Building Panama's National Semiconductor Talent Pipeline
Zoila De Castillo, C-TASC, Panama

09:50–10:10

Brazil´s Semiconductor Industry and Design House Ecosystem
Jacobus Swart, University of Campinas (UNICAMP) / INCT NAMITEC, Brazil

10:10–10:30

The Kutsari initiative and strategy for the future (virtual)
Edmundo Gutierrez, Kutsari (National Center for Semiconductor Design in Mexico), Mexico

10:30–11:00

Networking Coffee Break

Electronic Design Automation

Moderator: Ricardo Reis, UFRGS, Brazil

11:00–12:30

Panel: EDA Innovation and Latin America’s Role in the Global Semiconductor Ecosystem

Antonio de la Serna, Siemens EDA

Victor Grimblatt, Synopsys

Marcelo Da Silva, Cadence

12:30–14:00

Lunch

Talent Development and Industrial Capabilities

Moderator: Carlos Silva, PUCP, Peru

14:00–14:30

Talent: the keyword for the development of semiconductors

Ricardo Reis, Institute of Informatics, Federal University of Rio Grande do Sul (UFRGS), Brazil

14:30–15:45

Panel: Preparing Semiconductor Talent–Industry and University Experiences

Rodrigo Jaramillo, Circuify Semiconductors, Mexico

Alfredo Arnaud, Universidad Católica del Uruguay, Uruguay

Victor Grimblatt, Synopsys, Chile

Amílcar Josué Véliz Solares, Universidad Galileo, Guatemala

Javier Marte Michelen, Pontificia Universidad Católica Madre y Maestra, Dominican Republic

15:45–16:15

Networking Coffee Break

16:15–16:45

Assembly, Testing and Packaging: Opportunities for Latin America

Joel Molina, INAOE, Mexico

Day 1 Wrap-up

16:45–17:00

Day 1 Wrap-Up

Ivan Armuelles, Chair IEEE LACSS 2026

18:00–20:00

Welcome Reception (off-site)

La Casa - Ciudad del Saber


DAY 2 — Government and Industry: Policy, Investment and Regional Strategy
Friday, October 2nd, 2026

08:30–08:45

Day 2 Kick-off

Start of Day 2: summary of the previous day and agenda of the day

Global Policy, Cooperation and Investment

Moderator: Erik Heilman, IEEE-USA

08:45–09:30

Global Policy Perspectives for Semiconductor Development

Filipe Silva, Semiconductors Team Lead, OECD (virtual)

09:30–10:00

Pax Silica and the Global Semiconductor Ecosystem: Implications for Latin America and the Caribbean (virtual)

Akhil Ramesh, PAC Forum

10:00–10:30

Panama’s Semiconductor Strategy (TBC)

Victor Sanchez, C-TASC AIP, Panama

10:30–11:00

Networking Coffee Break

The Semiconductor Policy Playbook: Regulation, IP and Regional Development

Moderator: TBC

11:00–12:20

Panel: Policies and Partnerships for Latin American Semiconductor Ecosystems

Adão Villaverde, Brazil

Mayté Milián, Guatemala

Nestor García Romero, Mexico

Lorena Garcia, Colombia

12:20–12:30

IEEE Division I–Synopsys MoU Signing Ceremony: Semiconductor Workforce Development
Fernando Guarín, IEEE Division I

Victor Grimblatt, Synopsys

12:30–14:00

Lunch

Semiconductor Design, Manufacturing and Entrepreneurship

Moderator: Lorena Garcia, Alianza E, Colombia

14:00–15:30

Panel: Building Semiconductor and Hardware Businesses in Latin America

Rodrigo Jaramillo, Circuify Semiconductors, Mexico

Israel Mejia, QSM, Mexico (virtual)

Gabriel Ortiz, Pixart, Argentina

Alfonso Chacon, Rydev, Costa Rica

Javier Ardila, OnSilicon, Colombia (virtual)

15:30–16:00

Networking Coffee Break

Expanding Access to Semiconductor Design, Prototyping and Manufacturing

Moderator: Joel Molina, INAOE, Mexico

16:00–17:00

Panel: Expanding Access to Semiconductor Design, Prototyping and Manufacturing

Pat Deegan, Tiny Tapeout

Mitchell Hsing, InchFab

Alfonso Torres, INAOE (virtual)

FET 100

Moderator: Arokia Nathan, IEEE EDS, USA

17:00–17:45

FET100

Speakers: Fernando Guarin, Jacobus Swart.

17:45–18:00

Closing - LACSS 2027 announcement

Ivan Armuelles

Ricardo Reis

18:00

End of LACSS


DAY 3 — 2026 IEEE EDS/CASS MQ Semiconductors in Latin America
Saturday, October 3rd, 2026
Universidad De Panama Auditorio (Piso 3), Facultad De Informática, Electrónica Y Comunicación

IEEE EDS/CASS MQ Session: 
Exploring Innovation, Research, and Opportunities for a Semiconductor Future
in the Caribbean
8:00–8:15 Opening Ceremony — Registration and Welcome Remarks
8:15–8:45 Low Power Design for Sustainable Manufacturing in Agribusiness
Victor Grimblatt
8:45–9:15 Embedded Timing: A New Scaling Layer for Compute at System Scale
Rodrigo Calderon
9:15–9:45 Reliability Topics for Advanced Semiconductors
Fernando Guarin
9:45–10:15 Physical Design Automation: From Past to Future
Ricardo Reis
10:15–10:45 Networking Coffee Break
10:45–11:15 Brazil’s Semiconductor Industry and Design House Ecosystem
Jacobus Swart
11:15–11:45 Oxide Electronics
Arokia Nathan
11:45–12:15  Dielectrics Materials from Field Effect Transistors to In-Memory Computing
Durga Misra
12:15–13:30  Lunch



Jan 24, 2024

[C4P] RISC-V Summit Europe



The RISC-V Summit Europe is the premier event that connects the European movers and shakers - from industry, government, research, academia and ecosystem support - that are building the future of innovation on RISC-V.
RISC-V, the open standard instruction set architecture (ISA), is enabling a range of new applications and research that will define the future of computing in Europe. The region has been central to RISC-V’s success, with one-third of RISC-V’s global community based in Europe. 
RISC-V Summit Europe takes place from Monday 24th to Friday 28th June, 2024. The combination of strong industrial and academic communities is key to the success of RISC-V in Europe, and for this reason the conference is designed to help attendees to explore both commercial and research applications.

Present your work
Presentations on inspirational ideas and technical progress are invited to present 
at RISC-V Summit Europe.

RISC-V Summit Europe brings together developers, architects, technical decision and policy makers from across the European RISC-V ecosystem. Attendees from academia, research, SMEs, industry, and open source communities will come together to exchange knowledge, ideas, technologies, and research, shaping the future of RISC-V computing in Europe.

Taking place from June 24-28, 2024, the event will have a single track of keynotes, invited and selected talks, alongside an exhibition showcasing the latest developments across industry and research, including technology demonstrations and poster sessions. Submissions are invited either for:
🚀  Industry Sessions
Exciting large-scale research efforts, announcement and success-stories.
👩‍🔬  R&D Sessions

Leading edge academic and industry research & development insights.


Important dates
  • Abstract submission deadline: March 15th, 2024, AoE (Anywhere on Earth).
  • Author notification: April 29th, 2024.
  • Final abstract PDF and slides deadline: May 31st, 2024 AoE.
  • Poster PDF deadline: June 14, 2024 AoE.
  • RISC-V Summit Europe: June 24-28, 2024, Munich.
The Steering Committee aims to provide a limited budget for stipends. More information will be available on the conference website before the submission deadline.


Feb 9, 2023

[C4P] RISC-V Summit Europe

RISC-V Summit in Barcelona

On 5-9th June, in Barcelona, RISC-V Summit Europe brings together developers, architects, technical decision and policy makers from across European RISC-V ecosystem. Attendees from academia, research, SMEs, industry and open source communities will gather to exchange knowledge, ideas, technologies, and research shaping the future of RISC-V computing.

The event will include a single track of keynotes, invited and selected talks alongside an exhibition showcasing the latest developments across industry and research including technology demonstrations and poster sessions.

RISC-V Summit Europe is an opportunity not to be missed, come to Barcelona from 5-9th June 2023 to be part of the new wave of European computing innovation!

Call for Submissions

RISC-V Summit Europe brings together developers, architects, technical decision and policy makers from across the European RISC-V ecosystem. Attendees from academia, research, SMEs, industry, and open source communities will come together to exchange knowledge, ideas, technologies, and research shaping the future of RISC-V computing in Europe.

The event will have a single track of keynotes, invited and selected talks alongside an exhibition showcasing the latest developments across industry and research, including technology demonstrations and poster sessions. We invite blind submissions related to RISC-V addressing the following technical topics of interest:

    Automotive
    Cloud computing
    Compilation and code optimization
    Embedded systems, IoT, edge computing
    Hardware/software co-design
    High-performance computing
    Open EDA tools
    Open-source hardware and open silicon
    Operating system and software ecosystem
    RISC-V related educational activities
    RISC-V ISA extensions
    Systems-on-Chip, including processor cores, accelerators, peripherals
    Security and functional safety
    Verification
    Any other topic related to RISC-V and open hardware


We also welcome non-blind submissions related to:

    Commercial applications for real world deployment
    Policies, strategies, business and industry trends
    Publicly funded projects presentations and/or results


Important dates:

    Abstract submissions hard deadline: Monday, March 13th, 2023, AOE.
    Author notifications: Monday, April 24th, 2023, AOE.
    Final abstract version, de-anonymized, deadline: Thursday, Monday May 1st, 2023, AOE.
    Final slides and poster deadline: Thursday, June 1st, 2023, AOE.
    RISC-V Summit Europe: 5-9 June, 2023, Barcelona.