Aug 14, 2023

[11k online viewers] 7th Sino MOS-AK/Nanjing

Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
7th Sino MOS-AK Workshop in Nanjing (CN)
August 11-13, 2023 (online/onsite)
Recent, consecutive, 7th Sino MOS-AK/Nanjing Workshop discussing the Compact/SPICE modeling and its Verilog-A Standardization reached 11k online viewers. The MOS-AK participants and online attendees have followed one day SiC-related device modeling training on August 11 featured presentations by experts currently working at Robert Bosch GmbH and then two days workshop with 24 R&D Compact/SPICE modeling presentations:




Aug 10, 2023

[paper] 5-DC-parameter MOSFET model

Deni Germano Alves Neto1, Cristina Missel Adornes1, Gabriel Maranhao1, Mohamed Khalil Bouchoucha2,3, Manuel J. Barragan3, Andreia Cathelin2, Marcio Cherem Schneider1, Sylvain Bourdel3 and Carlos Galup-Montoro1
A 5-DC-parameter MOSFET model for circuit simulation in QucsStudio and SPECTRE
2023 21st IEEE Interregional NEWCAS Conference (NEWCAS) 
DOI: 10.1109/NEWCAS57931.2023.10198173

1 Federal University of Santa Catarina, Florianopolis (BR)
2 STMicroelectronics, Crolles (F)
3 Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, Grenoble (F)


Abstract: A minimalist MOSFET model for circuit simulation with only five DC parameters written in Verilog-A is presented. The five parameters can be extracted from direct and simple methods in common circuit simulators. The DC characteristics of transistors in both 180-nm bulk CMOS and 28-nm FD-SOI technologies generated by the five-parameter model are compared with those generated by the BSIM and UTSOI2 models, respectively. The simulation of some basic circuits using the proposed 5-DC-parameter MOSFET model shows good matching with the simulation using the BSIM model, at the benefit of a much simpler set of DC parameters.
Fig: DC characteristic gm/ID vs. id used to extract ζ.


REF:
[1] Advanced Compact MOSFET (ACM) in C. M. Adornes, D. G. Alves Neto, M. C. Schneider, and C. Galup-Montoro, “Bridging the gap between design and simulation of low voltage CMOS circuits,” Journal of Low Power Electronics and Applications, vol. 12, no. 2, 2022.

Aug 8, 2023

[mos-ak] [Final Program] 7th Sino MOS-AK Workshop in Nanjing (CN) August 11-13, 2023 (online/onsite)

Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
7th Sino MOS-AK Workshop in Nanjing (CN)
August 11-13, 2023 (online/onsite)

The 7th Sino MOS-AK Workshop in Nanjing (CN), carefully planned by the organizers Nanjing University of Posts and Telecommunications and Nanjing University of Aeronautics and Astronautics, will be held at the "Anheng Youth Theater" of Nanjing University of Posts and Telecommunications on August 11-13 2023. The SiC-related device modeling training on Aug.11 featured presentations by experts currently working at Robert Bosch GmbH. Considering the opportunity to allow more contributors to speak and communicate on stage, we fine-tuned the conference agenda and report time, so this time there are a total of 19 oral presentations, covering Advanced CMOS, GaN, SiC, SOI, Organic transistor, SiGe HBT, MRAM, etc., among which several new reports are from BGI Nine Days, Primarius, Nanjing University of Aeronautics and Astronautics, Southeast University, and others. Please refer to the Program https://www.mos-ak.org/nanjing_2023/

-- Min Zhang <zhang@xmodtech.cn>






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Aug 2, 2023

[video] Semiconductor industry in Switzerland

75th Anniversary of the Transistor
Semiconductor Industry in Switzerland

A commemorative and networking event was organized by the IEEE Solid-State Circuits Chapter of Switzerland at the EPFL Microcity building in Neuchâtel, Switzerland. In the first part of the afternoon, we had the honor to host three Distinguished Lecturers:
  • Prof. Tom Lee presentation “From Rocks to Chips: Stories of the Transistor” covered the early history of the transistor.
  • Dr. Chris Mangelsdorf described circuit design techniques using the bipolar junction transistor (BJT) in his talk “Don’t Try This With CMOS!”.
  • Prof. Christian Enz concluded this session, describing the development of low power CMOS using the EKV MOSFET model.
This video covers the second part of the event, “From transistor manufacturing in the late 1950’s until today”. It hosted five speakers who were key actors or are still active in the semiconductor sector of Switzerland.


[video] Interviews from FSiC, Paris, 2023


Interviews from the Free Silicon Conference, Paris, 2023

The 2023 Free Silicon Conference (FSiC) took place in Paris (Sorbonne Université, 4 Place Jussieu, Paris) on July 10 - 12 2023 (Monday to Wednesday). The conference brought together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference covered the full spectrum of the design process, from system architecture, to layout and verification.

Interviews with selected Free Silicon Conference Participation by Matt Venn are available online:

00:00 FSiC 2023 Intro, Matt Venn
00:23 Luca Alloatti, FSiC Organizing Committee
01:59 Thomas Benz, ETH Zurich
06:05 Jørgen Kragh Jakobsen, IC Works - Open Source Chip Design
08:57 Thomas Parry, SPHERICAL
11:05 Rene Scholz, IHP Microelectronics
14:06 Dan Fritchman, UC Berkeley
18:41 Harald Pretl, Johannes Kepler University Linz

All the conference proceedings (slide presentations and prerecorded talks) are also available at the FSiC website.