Postdoc position in GaN power devices

The POWERlab (https://powerlab.epfl.ch) at EPFL is looking for excellent and motivated candidates to work on new concepts for power electronic devices based on GaN heterostructures. The candidate will pursue novel ideas related to concepts developed in our laboratory, for example [1]. The candidate will have the opportunity to work on several aspects involved in demonstrating high-performance power devices (cleanroom fabrication, device simulation and characterization) relying on the excellent facilities in our laboratory and at EPFL. Most importantly, the candidate is encouraged to try new ideas and approaches.

Profile: The candidate is expected to have a solid theoretical background in semiconductors and experience in cleanroom fabrication of GaN electronic devices, with strong aptitude to perform experiments, explore new concepts, and communicate his/her findings in high-quality scientific publications.

What is offered: The selected candidate will be offered a fellowship with very competitive salary and excellent conditions to excel in his/her research.

How to apply: If you are interested, and have the correct profile for this position, please send your CV to elison.matioli@epfl.ch, including publication list and names of two references.

REF:

[1] L. Nela, J. Ma, C. Erine, P. Xiang, T.-H. Shen, V. Tileli, T. Wang, K. Cheng and E. Matioli, “Multi-channel nanowire devices for efficient power conversion” Nature Electronics, 4, 284–290, (2021)

[chapter] Systematic Design of Analog CMOS Circuits with Lookup Tables

Systematic Design of Analog CMOS Circuits with Lookup Tables

By Paul G. A. Jespers, Université Catholique de Louvain, Belgium

in Foundations and Trends in Integrated Circuits and Systems

Vol. 2: No. 3, pp 193-243. http://dx.doi.org/10.1561/3500000004

Publication Date: 08 May 2023

© 2023 P. G. A. Jespers*

ABSTRACT The idea underlying the methodology described in this monograph consists in the use of a set of Lookup Tables embodying device data extracted prior from systematic runs done once and for all using an advanced circuit simulator, the same as used for final design verifications. In this way, all parameters put to use during the sizing procedure incorporate not only the bearings of bias conditions and geometry, but also every second-order effect present in the simulator’s model, in particular short-channel effects. Consequently, the number of verification simulations one has to perform is not only substantially reduced, but the designer may concentrate on actual design strategies without being bothered by inconsistencies caused by poor models or inappropriate parameters.

Fig: The drain current ID versus the gate-to-source voltage VGS (plain lines) compared to the EKV best fit (+). The other lines represent the exponential and quadratic approximations.

∗The author acknowledges the kind support of Prof. Boris Murmann in writing this monograph.

OpenPDK Networking Workshop

OpenPDK, OpenTooling and Open Source Design

An Initiative to Push Development

Date:
Networking Workshop FMD-QNC on 27-28 June 2023
Location:
IHP; Im Technologiepark 25; 15236 Frankfurt (Oder)
Contact:
Sergei Andreev; Phone: +49 335 5625 523

Free Registration: 

OnLine

The workshop is organised by IHP and FMD (Research Fab Microelectronics Germany) within the framework of the FMD-QNC Project.

Within the project FMD-QNC analog circuit design with open source software shall be enabled. For this purpose, both the open source design tools and a process design kit of the semiconductor technology used must support the entire design flow with sufficient quality. IHP provides its 130 nm BiCMOS technology SG13G2 for open source design. This technology is particularly suited for high frequency and mixed signal design applications. While basic tool support already exists for digital circuit design, it is still very rudimentary for analog designs and especially for high frequency designs. A considerable effort has to be put into the development of the design tools as well as into the creation of the technology specific Process Design Kit (PDK).

The 2-day workshop is intended to promote exchange and networking between tool developers, the PDK developers at IHP and designers. Tool developers are to present the capabilities of the tools as well as planned enhancements. Designers are to present ideas that can be used for training chip designers. Requirements for open source design tools for digital design, mixed signal design, and high frequency design are to be highlighted.

Discussions will identify and prioritize gaps for a complete design flow in the open source tools and PDK. The workshop will thus help to concrete the planning for the Open Design Platform and to create a roadmap for future work.

Presentation	Presenter/Institution	Timeline
Day 1
Welcome by coordinator FMD-QNC	Dr. Andreas Bruning Research Fab Microelectronics Germany	9:00-9:10
Introduction FMD-QNC project status and IHP OpenPDK Roadmap	Dr. Rene Scholz IHP	9:10-9:30
Status OpenPDK and OpenTooling for SG13G2 BiCMOS technology	Sergei Andreev IHP	9:30-10:00
An Ultra-Low-Power High-Density Wireless Biomedical Sensing System	Prof. Harald Pretl Johannes Kepler University Linz	10:00-10:30
Teaching digital design by using open-source EDA tools	Prof. Steffen Reith Rhein Main University of Applied Sciences	10:30-11:00
Coffee break		11:00-11:40
CMOS Rail-to-Rail Operational Amplifier for HPGe Radiation Detector	Prof. Herman Jalli Ng Karlsruhe University of Applied Sciences	11:40-12:10
Design-flow approaches for mmWave and sub-THz integrated transceiver circuits for radar and communication	Sasha Breun FAU Erlangen	12:10-12:40
Lunch break		12:40-13:40
TBD	Dr. Frank K. Gurkaynak ETH Zurich	13:40-14:10
TBD	Joachim Hebeler Karlsruhe Institute of Technology	14:10-14:40
Coffee break		14:40-15:10
TBD	Prof.  Dietmar Kissinger Ulm University	15:10-15:40
LibMan - an easy way to manage your open source design flow	Dr. Anton Datsuk IHP	15:40-16:10
Get together (Barbecue)		17:00-…
Day 2
ngspice - status and future developments	Prof. Holger Vogt	9:00-9:20
DMT - Python Toolkit for Device Modeling	Mario Krattenmacher SemiMod	9:20-9:40
OpenVAF - Next Generation Verilog-A Compiler with ngspice integration	Mario Krattenmacher SemiMod	9:40-10:00
Coffee break		10:00-10:40
Best practices for implementing and optimizing KLayout DRC and LVS decks	Matthias Köfferlein	10:40-11:00
Generating DRC and LVS Runsets for KLayout	Dr. Andreas Krinke TU Dresden	11:00-11:20
OpenEMS in open source EDA	Jan Taro Svejda University of Duisburg-Essen	11:20-11:40
Lunch break		11:40-12:40
Panel discussion on the roadmap – open source tools for IC design Topics: Digital design flow Analog design flow Challenges in RF design	Dr. Norbert Herfurth IHP Panelists: TBD	12:40-14:10

ECME 2023: deadline for abstract submission

 

Dear Colleague, 

as you may know, the 16^th European Conference of Molecular Electronics (ECME) will be held in Bari (Italy) on 2-6 October 2023 in the beautiful venue of the Municipal Theatre Niccolò Piccinni (https://www.ecme2023.eu/). 

This mail is to kindly invite you to submit your contribution to ECME-2023 by May 24, 2023.

Over the years, ECME has become the premier European Conference in the field of Molecular Electronics, and ECME 2023 will continue the prestigious series of biannual conferences previously organized in Italy (Padua, 1992), Germany (Kloster Banz, 1994), Belgium (Leuven, 1996), UK (Cambridge, 1997), Sweden (Linköping, 1999), The Netherlands (Rolduc, 2001), France (Avignon, 2003), Italy (Bologna, 2005), France (Metz, 2007), Denmark (Copenhagen, 2009), UK (London, 2013), France (Strasburg, 2015), Germany (Dresden, 2017), Sweden (Linköping, 2019).

 
The conference will cover all areas related to molecular-organic and plastic electronics including chemistry, physics, biology, materials science, nanoscience, engineering, device fabrication, and commercialization. 

You will also have the chance to enjoy your stay in the beautiful city of Bari, the capital of the Apulia region (https://www.italia.it/en/puglia/bari). The conference venue is right in the city center directly connected to the international airport and very close to the medieval quarter called "Bari vecchia". Bari is not only rich in monuments, medieval churches, and cultural sites, but holds one of the most beautiful and long promenades in Italy overlooking a wonderful clear sea, all at walking distance from the conference venue. Walking through the streets of Bari means appreciating not only the local culture, history, art, and architecture but also the local cuisine served in any restaurants, trattoria, osteria, or else enjoying the typical humble street food, such as focaccia and panzerotti. 

We are looking forward to welcoming you to Bari,

Luisa Torsi and Gianluca Farinola

(ECME 2023 Chairpersons) 

[EDS MQ/DL] The Transistor Turns 75

The Transistor Turns 75

A Forward Look to Challenges and Opportunities

A series of IEEE EDS Distinguished Lecturer talks on topics in current transistor and electron device research, reflecting on the challenges ahead and the rewards inherrent in overcomming them.

DATE AND TIME	LOCATION	HOSTS	REGISTRATION
Date: 02 Jun 2023 Time: 08:30 AM to 05:30 PM All times are (UTC+00:00) Edinburgh	Moller Institute Cambridge, England UK CB3 ODE Click here for Map	UK and Ireland Section Chapter, ED15 Contact Host	Starts 19 April 2023 06:00 AM Ends 30 May 2023 06:30 PM All times are (UTC+00:00) Edinburgh No Admission Charge Register Now

EDS DL SPEAKERS

• Benjamin Iniguez: Modeling 2D Semiconductor Devices
• Lluis Marsal: Organic Photovoltaics: Opportunities and Challenges
• Arokia Nathan: 
• Fernando Guarin: 75th Anniversary of the Transistor Semiconductor Industry Perspective
• Edmundo A. Gutierrez-D.: DC and RF reliability of advanced bulk and SOI CMOS technologies
• Merlyne De Souza: Challenges to Edge computing: an era beyond silicon CMOS
• Samar Saha: 
• MK Radhakrishnan: Birth and Evolution of Transistor and Its Impact on Humanity
• Xiaojun Guo: Transistor Technologies for Hybrid Integration at Micro- and Macro-scales
• Hiroshi Iwai: Present status and future of the nanoelectronics technology