Systematic Design of Analog CMOS Circuits with Lookup Tables
By Paul G. A. Jespers, Université Catholique de Louvain, Belgium
in Foundations and Trends in Integrated Circuits and Systems
Vol. 2: No. 3, pp 193-243. http://dx.doi.org/10.1561/3500000004
Publication Date: 08 May 2023
© 2023 P. G. A. Jespers*
ABSTRACT The idea underlying the methodology described in this monograph consists in the use of a set of Lookup Tables embodying device data extracted prior from systematic runs done once and for all using an advanced circuit simulator, the same as used for final design verifications. In this way, all parameters put to use during the sizing procedure incorporate not only the bearings of bias conditions and geometry, but also every second-order effect present in the simulator’s model, in particular short-channel effects. Consequently, the number of verification simulations one has to perform is not only substantially reduced, but the designer may concentrate on actual design strategies without being bothered by inconsistencies caused by poor models or inappropriate parameters.
Fig: The drain current ID versus the gate-to-source voltage VGS (plain lines) compared to the EKV best fit (+). The other lines represent the exponential and quadratic approximations.
∗The author acknowledges the kind support of Prof. Boris Murmann in writing this monograph.
