May 4, 2020

[paper] Benchmark Tests for MOSFET Thermal Noise Models

Scholten A.J., Smit G.D.J., Pijper R.M.T., Tiemeijer L.F.
Benchmark Tests for MOSFET Thermal Noise Models
In: Grasser T. (eds) Noise in Nanoscale Semiconductor Devices. Springer, Cham

Abstract - In today’s semiconductor industry, many traditional integrated device manufacturers (IDMs) are moving away from chip manufacturing, and transforming into fabless companies that use foundry services for manufacturing their ICs. This is especially true in the field of advanced CMOS technologies. In these companies-under-transformation, the work of the modeling engineer is changing: instead of building models from scratch themselves, most companies choose to use the modeling packages that are delivered by the foundries. There are two reasons to be skeptical about RF noise models. First, measurement of noise, and RF noise in particular, is a difficult and specialist topic. One should not take for granted that every company has the required expertise to carry out this task successfully. A second reason to check RF noise models is that the most popular compact MOSFET models are BSIM4 [1] and BSIMBULK [2], which are not particularly strong and certainly not predictive when it comes to RF noise. As a consequence, the work of the modeling engineer is changing from model creation to model verification.

Tab: Overview of benchmark tests for thermal noise
#No
Bias
Length
Quantity
Test
Remark
#1
VDS = 0V
All
SID
γ = 1

#2
VDS = 0 V
All
SIG
β = 5/12

#3
VDS = 0 V
All
c
c = 0
In the limit f ↓ 0 Hz
#4
Weak Inv
All
SID
F = 1
Disregard SIG contributions from gate to drain
#5
Saturation
Long
SID
γ = 2/3

#6
Saturation
Long
SIG
β = 4/3

#7
Saturation
Long
c
c = 0.4j

#8
Saturation
Short
SID
γ enhancement
Switch off gate resistance
#9
Saturation
All
SID
γ D,NMOS ≥ γ D,PMOS
Switch off gate resistance
#10
Saturation
All
SID
Different Vth flavors should nearly coincide
When plotted against ID


First Online: 27 April 2020
DOI: 10.1007/978-3-030-37500-3_20

Ref: 
[1] N. Paydavosi, T.H. Morshed, D.D. Lu, W. Yang, M.V. Dunga, X. Xi, J. He, W. Liu, K.M. Cao, X. Jin, J.J. Ou, M. Chan, A.M. Niknejad, C. Hu, BSIM4v4.8.0 MOSFET Model - User’s Manual. [Online]. Available: http://bsim.berkeley.edu/models/bsim4/
[2] H. Agarwal, C. Gupta, H.-L. Chang, S. Khandelwal, J.P. Duarte, Y.S. Chauhan, S. Salahuddin, C. Hu, BSIM-BULK106.2.0 MOSFET Compact Model - Technical Manual. [Online]. Available: http://bsim.berkeley.edu/models/bsimbulk/

[paper] DHBT with Record ft of 813 GHz

Y. Shiratori, T. Hoshi and H. Matsuzaki,
InGaP/GaAsSb/InGaAsSb/InP Double Heterojunction Bipolar Transistors
With Record ft of 813 GHz
IEEE EDL vol. 41, no. 5, pp. 697-700, May 2020
doi: 10.1109/LED.2020.2982497

Abstract - We fabricated InGaP/GaAsSb/InGaAsSb/InP double heterojunction bipolar transistors (DHBTs) with an aggressive lateral and vertical scaling technology to improve the current gain cutoff frequency (fT) further. A 13-nm-thick GaAsSb/InGaAsSb base and a 40-nm-thick InP collector are used to reduce electron transit time. In addition, the width of the base electrode on each side of the emitter is reduced to about 0.05µm to suppress increases in parasitic collector capacitance. A fabricated DHBT with the emitter size of 0.24µm×7.8 µm exhibits maximum differential current gain of ∼95 and collector-emitter breakdown voltage of 2.6V. At a collector current density of 18 mA/µm2, the DHBT exhibits fT of 813 GHz, which is the highest among all types of transistors measured at a room temperature.
Fig: (a) Current gain ( |h21| ) and Mason’s unilateral power gain (Ug ) of the DHBT as a function of frequency. JC and VCE are 18 mA/μm2 and 1.0 V, respectively. ft and fmax are extrapolated by single-pole fitting. Inset: frequency dependence of extrapolating ft and fmax . (b) Gummel’s ft extraction (imaginary part of 1/h21 as a function of frequency). The red circles and black line show experimental data and a linear fitting, respectively.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9044299&isnumber=9079222

May 1, 2020

[paper] Physical Mechanisms of Reverse DIBL and NDR in FeFETs With Steep Subthreshold Swing

C. Jin, T. Saraya, T. Hiramoto and M. Kobayashi,
in IEEE J-EDS, vol. 8, pp. 429-434, 2020
doi: 10.1109/JEDS.2020.2986345

Abstract - We have investigated transient IdVg and IdVd characteristics of ferroelectric field-effect transistor (FeFET) by simulation with ferroelectric model considering polarization switching dynamics. We show transient negative capacitance (TNC) with polarization reversal and depolarization effect can result in sub-60mV/dec subthreshold swing (SS), reverse drain-induced barrier lowering (R-DIBL), and negative differential resistance (NDR) without traversing the quasi-static negative capacitance (QSNC) region of the S-shaped polarization-voltage (PV) predicted by single-domain Landau theory. Moreover, the mechanisms of R-DIBL and NDR based on the TNC theory are discussed in detail. The results demonstrated in this work can be a possible explanation for the mechanism of previously reported negative capacitance field-effect transistor (NCFET) with sub-60mV/dec SS, R-DIBL, and NDR.
Equivalent circuits of a ferroelectric capacitor in both static and transient conditions.

Apr 30, 2020

#paper: W. E. Muhea, G. U. Castillo, H. C. Ordoñez, T. Gneiting, G. Ghibaudo and B. Iñiguez, "Parameter Extraction and Compact Modeling of 1/f Noise for Amorphous ESL IGZO TFTs," in IEEE J-EDS, vol. 8, pp. 407-412, 2020. https://t.co/SCTs7BsGJZ https://t.co/gZcCgMrYVd


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April 30, 2020 at 03:13PM
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#paper: J. Leise et al., "Charge-Based Compact Modeling of Capacitances in Staggered Multi-Finger OTFTs," in IEEE J-EDS, vol. 8, pp. 396-406, 2020. https://t.co/zk4BAp2tMj https://t.co/Ay502xHy1w

#paper: J. Leise et al., "Charge-Based Compact Modeling of Capacitances in Staggered Multi-Finger OTFTs," in IEEE J-EDS, vol. 8, pp. 396-406, 2020



https://t.co/zk4BAp2tMj pic.twitter.com/Ay502xHy1w

— Wladek Grabinski (@wladek60) April 30, 2020 from Twitter https://twitter.com/wladek60

#Spanish and #French governments turn to Jitsi Meet #opensource video-conferencing platform https://t.co/68ZzP2iPq2 https://t.co/uXUBtMOAli


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April 30, 2020 at 10:05AM
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Apr 29, 2020

#paper: K. Xia, "New C∞ Functions for Drain–Source Voltage Clamping in Transistor Modeling," in IEEE TED, vol. 67, no. 4, pp. 1764-1768, April 2020. https://t.co/N9yGopiPNg https://t.co/9AKubeYY5x


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April 29, 2020 at 04:16PM
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#paper: E. A. Gutiérrez-D., J. Méndez-V., J. C. Tinoco, E. T. Rios and O. V. Huerta-G., "DC and 28 GHz Reliability of a SOI FET Technology," in IEEE J-EDS, vol. 8, pp. 385-390, 2020. https://t.co/slotpnOx43 https://t.co/sfZjtH0CPq

XXII ESCOLA SUL DE MICROELETRÔNICA: EMicro 2020 XXXV SIMPÓSIO SUL DE MICROELETRÔNICA: SIM 2020 27-30 April 2020 Virtual Event: https://t.co/DzzZLK7lIF Recordings: https://t.co/RuFy6pR6Qa #paper https://t.co/bItZC5bjWv


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April 29, 2020 at 09:21AM
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Apr 28, 2020

#paper: H. Cortes-Ordonez et al., "Parameter extraction and compact drain current model for IGZO transistor from 210K up to 370K," 2020 IEEE Latin America Electron Devices Conference (LAEDC), San Jose, Costa Rica, 2020, pp. 1-5. https://t.co/WDalcLFJsX https://t.co/FJGSnemXhj


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April 28, 2020 at 05:01PM
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Apr 27, 2020

#paper: X. Lu, M. Law, Y. Jiang, X. Zhao, P. Mak and R. P. Martins, "A 4um Diameter SPAD Using Less-Doped N-Well Guard Ring in Baseline 65nm CMOS," in IEEE TED, vol. 67, no. 5, pp. 2223-2225, May 2020. https://t.co/FFxEEIyh8J https://t.co/LGo5VTESKd


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April 27, 2020 at 11:37AM
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Apr 26, 2020

#paper: Y. Hernández-Barrios, A. Cerdeira, M. Estrada and B. Iñíguez, "Analytical Current–Voltage Model for Double-Gate a-IGZO TFTs With Symmetric Structure for Above Threshold," in IEEE TED, vol. 67, no. 5, pp. 1980-1986, May 2020. https://t.co/mJQkQo60Th https://t.co/Z1xMTrw56o


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April 26, 2020 at 03:49PM
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Apr 24, 2020

#paper: L. Liu, W. Chen, X. Liu and G. Du, "Photoelectric Characteristic Evaluation of Different Structured UTBB MOSFETs," in IEEE TED, vol. 67, no. 5, pp. 1919-1923, May 2020 https://t.co/2onkfigdMS https://t.co/XWNv6uZML9


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April 24, 2020 at 05:49PM
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Online Classes on The Principle of Semiconductor Devices

Professor Mansun Chan, UST (HK), has developed a 13 weeks online class on the principle of semiconductor devices.  Unlike tradition lectures, the class use extensive animations to help students to visualize the actions of carriers in a device.  The classes was divided into two part, part I on semiconductor carrier statistics, PN Junction, BJT and part II on MOSFET and advanced FET.


Meet your instructor:

Mansun Chan
Chair Professor, Department of Electronic and Computer Engineering
The Hong Kong University of Science and Technology


conference FOSS paper reached 300 reads


D. Tomaszewski, G. Głuszko, M. Brinson, V. Kuznetsov and W. Grabinski, "FOSS as an efficient tool for extraction of MOSFET compact model parameters," 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems, Lodz, 2016, pp. 68-73.

Abstract - A GNU Octave - based application for device-level compact model evaluation and parameter extraction has been developed. The applications main features are as follows: experimental I–V data importing, generating input data for different circuit simulation programs, running the simulation program to calculate I–V characteristics of the specified models, calculating model misfit and its sensitivity to selected parameter variation, and the comparison of experimental and simulated characteristics. Measured I–V data stored by different measurement systems are accepted. Circuit simulations may be done with Ngspice, Qucs and LTSpiceIV © . Selected aspects of the application are presented and discussed.

Apr 20, 2020

Pokit PRO. Multimeter, Oscilloscope & Logger https://t.co/m65iiW8ckl #paper https://t.co/qAYsVIiW7m


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April 20, 2020 at 02:23PM
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#paper: J. Li, Z. Chen, Y. Qu and R. Zhang, "Traps Around Ge Schottky Junction Interface: Quantitative Characterization and Impact on the Electrical Properties of Ge MOS Devices," in IEEE J-EDS, vol. 8, pp. 350-357, 2020 https://t.co/zD5bzZH2cN https://t.co/g7qcnAGtjM


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April 20, 2020 at 10:49AM
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#paper: D. Arbet, L. Nagy, V. Stopjakova "Ultra-Low-Voltage IC Design Methods" Integrated Circuits/Microchips, 2020 | IntechOpen https://t.co/QuPlCt45YH https://t.co/XsJrid4jC7


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April 20, 2020 at 09:21AM
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Apr 15, 2020

#paper: W. Cheng et al., "Fabrication and Characterization of a Novel Si Line Tunneling TFET With High Drive Current," in IEEE J-EDS Society, vol. 8, pp. 336-340, 2020 https://t.co/BQAZV3tf3C https://t.co/Eqw9tGmBDI


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April 15, 2020 at 05:30PM
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Fwd: "It is forbidden to spit on cats during plague-time"

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Date: Wed, Apr 15, 2020 at 5:10 PM
Subject: users on Empyrean XTop ECOs, and Cadence Tempus vs. PrimeTime

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#paper: Lin, P., Li, C., Wang, Z. et al. Three-dimensional memristor circuits as complex neural networks. Nat Electron (2020) https://t.co/9ikrvgQq3z https://t.co/MH0mVWdyVj


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April 15, 2020 at 02:51PM
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#paper: Darsen D. Lu, Sourav De, Mohammed Aftab Baig, Bo-Han Qiu and Yao-Jen Lee; A computationally efficient compact model for ferroelectric FETs for the simulation of online training of neural networks; arXiv preprint arXiv:2004.03903, 2020 https://t.co/JBZfgb2jZw https://t.co/AH9NvasJuD


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April 15, 2020 at 10:27AM
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Apr 14, 2020

#paper: Meng Zhang and Dragan Damjanovic; Quasi-rayleigh model for modeling hysteresis of piezoelectric actuators; Smart Materials and Structures; DOI: https://t.co/0lOX07NnAU https://t.co/WaSgY5lYML https://t.co/Dux8Lpe4wq


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April 14, 2020 at 02:24PM
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ICMTS2020 #paper: Cutoff Frequency Fluctuation in RF-MOSFETs

2020 ICMTS, April 6-9, Edinburgh (UK)
Novel Statistical Modeling and Parameter Extraction Methodology
of Cutoff Frequency for RF-MOSFETs
Chika Tanaka, Yasuhiko Iguchi, Atsushi Sueoka, and Sadayuki Yoshitomi
Memory Division, Kioxia Corporation
2-5-1, Kasama, Sakae-ku, Yokohama, 247-8585, Japan

Abstract: The cutoff frequency fluctuation in RF-MOSFET has been investigated. Detailed analysis for capacitance fluctuation as well as the extraction of an intrinsic MOSFET parameter were performed. The extracted process parameters were verified by the framework of effective mobility. The global statistical model of cutoff frequency was successfully developed in terms of capacitance fluctuation, considering intrinsic (channel and bulk charge) and extrinsic (overlap and fringe) capacitance components separately and identifying the major variability sources for cutoff frequency by using extracted parameter.
Fig: Calculated σfT is plotted against σfT obtained from measured data.




Apr 11, 2020

Fwd: MIXDES 2020 moves online

------- Forwarded message ---------
From: MIXDES 2020 Organising Committee <mixdes2020@dmcs.p.lodz.pl>
Date: Thu, 9 Apr 2020 at 22:03
Subject: MIXDES 2020 moves online
To: <wladek@grabinski.ch>


Dear Colleagues,

As the Covid-19 disease is spreading worldwide and we have not yet seen
the peak, we have decided to move current edition of MIXDES to the
Internet. Hopefully next year we will be able to meet face to face. In
the meantime please keep your calendars blocked for the original
conference dates (June 25-27), and prepare to join us online. We will
inform you about the details later.

We are planning to reduce the conference fee to the level of ca. 100 Euro.

As in the previous years, the Conference Proceedings containing all the
presented papers will still be published on IEEE Xplore, so you do not
have to worry about visibility of your papers.


Wishing you Happy Easter and hoping that you stay safe,

Mariusz Orlikowski

--
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Fwd: Immediate changes for ESSCIRC-ESSDERC 2020 in Grenoble

------- Forwarded message ---------
From: Andreia CATHELIN <andreia.cathelin@st.com>
Date: Thu, 9 Apr 2020 at 17:11
Subject: Immediate changes for ESSCIRC-ESSDERC 2020 in Grenoble
To: Andreia CATHELIN <andreia.cathelin@st.com>
CC: Andreia CATHELIN <andreia.cathelin@st.com>, Sylvain CLERC <sylvain.clerc@st.com>, Maud VINET <maud.vinet@cea.fr>, ANDRIEU François 200489 <francois.andrieu@cea.fr>, Dominique THOMAS <dominique.thomas@st.com>, ERNST Thomas 175262 <thomas.ernst@cea.fr>, andrea.baschirotto@unimib.it <andrea.baschirotto@unimib.it>, huang@iis.ee.ethz.ch <huang@iis.ee.ethz.ch>


Grenoble, April 9th, 2020

 

Dear TPC members of ESSCIRC-ESSDERC conference,

 

First of all, we truly hope this email finds you in good health, together with family and friends!

 

Together with our sponsoring IEEE Societies, SSCS and EDS, ESSCIRC-ESSDERC is closely monitoring developments related to the rapidly evolving COVID-19 pandemic. The health and safety of our members is the number one priority of our societies. As of today April the 9th, 2020, more than one third of the Global population is under severe confinement, as a result of the protective public health measures imposed by the different governments, states or provinces. The situation is still evolving rapidly and dramatically, unfortunately in an unpredictable way.

 

Given this uncertain situation, we, the organizing committee of ESSxxRC2020 Grenoble and the ESSCIRC-ESSDERC Steering committee, have decided to propose a new format for our conference:

 

From a practical point of view:

For all the authors who have been or were about to prepare papers for this version of ESSCIRC-ESSDERC, we strongly encourage you to submit your publications directly to the following IEEE journals:

  • For ESSCIRC, please see https://sscs.ieee.org/publications:
    • IEEE SSC-L, Solid-State Circuits Letters (same 4-pages format as ESSCIRC)
      • The SSCS has just created a Special Section on ESSCIRC 2020, inside the SSC-Letters: https://mc.manuscriptcentral.com/ssc-l
      • When submitting their manuscript, authors need to select: Special Section on ESSCIRC 2020. It is open for submissions from April 9, 2020 to May 4, 2020.
      • The authors having accepted papers through this path will be kindly invited in September 2021 to present this same work in a Special Oral Session of ESSCIRC2021.
    • IEEE JSSC, Journal of Solid-State Circuits
    • IEEE O-JSSC, Open-Journal of Solid-State Circuits (open access)

  • For ESSDERC, please see https://eds.ieee.org/publications :
    • IEEE EDL, Electron Devices Letters (same 4-pages format as ESSDERC) 
    • IEEE TED, Transactions on Electron Devices
    • IEEE JEDS, Journal of Electron Devices Society (open access)
    • We are actively working with EDS to propose a similar Special Section for ESSDERC together with ED-L.

 

In 2021, we are planning to resume to a usual conference development schedule with tentative dates of: 

  • paper submission deadline on April 19th, 2021,
  • the conference in Grenoble, September 6-9, 2021.

All the topology of the conference with regards to the different tracks and TPC members stays exactly the same for 2021. You might as well be solicited by the different IEEE journals for anonymous reviews, please do provide all your support, as they will get a much larger volume of publications than regular.

 

The 2022 version of ESSCIRC-ESSDERC will take place in September 2022 in Milano. We thank very much to Andrea Baschirotto&team for their immediate proactivity, flexibility and cooperation.

 

This information shall be posted as well on our website within the hour, and we will massively announce it also on social media. Please do not hesitate to spread this information to your personal network.

 

Thank you very much for your continued trust, and stay safe!

 

Kind regards,

 

Andreia Cathelin, TPC chair ESSCIRC

Francois Andrieu, TPC chair ESSDERC

Sylvain Clerc, TPC co-chair ESSCIRC

Maud Vinet, TPC co-chair ESSDERC

Thomas Ernst, Conference Chair

Dominique Thomas, Conference Co-Chair

Qiuting Huang, ESSCIRC-ESSDERC Steering Committee Chair

 

 

Andreia Cathelin | Tel: +33 476926603 | Mobile: +33 607649918

Technology & Design Platform | Strategy & Innovation/Ecosystem | Technology R&D Fellow

 

STMicroelectronics Crolles2

850 rue Jean Monnet | 38926 Crolles Cedex | France

 

Knowledge is proud that he has learned so much,
Wisdom is humble that he knows no more.

The Task, Book 6, 'The Winter Walk at Noon' (published 1785). William Cowper

 

 

 

--
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Apr 6, 2020

#paper: T. Joshi, Y. Singh and B. Singh, "Extended-Source Double-Gate Tunnel FET With Improved DC and Analog/RF Performance," in IEEE TED, vol. 67, no. 4, pp. 1873-1879, April 2020 https://t.co/Pj1MYX1aF1 https://t.co/S2UjuAbMwn


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April 06, 2020 at 11:05AM
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#paper M. Ba, A. K. Diallo, E. H. B. Ly, J. Launay and P. Temple-Boyer, "Numerical Modeling of Glucose Biosensor With pH-Based Electrochemical Field-Effect Transistor Device," in IEEE TED, vol. 67, no. 4, pp. 1787-1792, April 2020. https://t.co/h8fblSoTWn https://t.co/5G6IJilTPO


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April 06, 2020 at 10:21AM
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