#Modeling of flicker noise in quasi-ballistic FETs - IEEE Conference Publication https://t.co/JpropPaK27
— Wladek Grabinski (@wladek60) November 2, 2017
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Nov 2, 2017
#Modeling of flicker noise in quasi-ballistic FETs - IEEE Conference Publication https://t.co/JpropPaK27
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November 02, 2017 at 10:05AM
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Circuit-aging #modeling based on dynamic MOSFET degradation and its verification - IEEE Conference Publication https://t.co/QnZG525Y7R
Circuit-aging #modeling based on dynamic MOSFET degradation and its verification - IEEE Conference Publication https://t.co/QnZG525Y7R
— Wladek Grabinski (@wladek60) November 2, 2017
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Oct 31, 2017
[mos-ak] [2nd Announcement and Call for Papers] 10th International MOS-AK Workshop in the Silicon Valley
10th International MOS-AK Workshop
(co-located with the CMC Meeting and IEDM Conference)
http://www.mos-ak.org/silicon_valley_2017/
Silicon Valley, December 6, 2017
2nd Announcement and Call for Papers
Together with local organization teams Cadence Design Systems and Keysight Technologies as well as International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and all the Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Compact Modeling Workshop which will be organized for consecutive 10th time in the timeframe of coming IEDM and CMC Meetings.
Planned,10th MOS-AK workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.
Important Dates:
Topics to be covered include the following among other related to the compact/SPICE modeling :
Online Workshop Registration
Postworkshop Publications:
Extended MOS-AK Committee
Planned,10th MOS-AK workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.
Important Dates:
- Call for Papers - Sept. 2017
- 2nd Announcement - Oct. 2017
- Final Workshop Program - Nov. 2017
- MOS-AK Workshop - Dec.6, 2017
Cadence Design Systems2655 Seely AveSan Jose, CA 95134
Topics to be covered include the following among other related to the compact/SPICE modeling :
- Compact Modeling (CM) of the electron devices
- Advances in semiconductor technologies and processing
- Verilog-A language for CM standardization
- New CM techniques and extraction software
- Open Source TCAD/EDA modeling and simulation
- CM of passive, active, sensors and actuators
- Emerging Devices, TFT, CMOS and SOI-based memory cells
- Microwave, RF device modeling, high voltage device modeling
- Nanoscale CMOS devices and circuits
- Technology R&D, DFY, DFT and reliability/ageing IC Designs
- Foundry/Fabless Interface Strategies
(any related inquiries can be sent to papers@mos-ak.org)
Online Workshop Registration
(any related inquiries can be sent to register@mos-ak.org)
Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems
in a special issue of the International Journal of High Speed Electronics and Systems
Extended MOS-AK Committee
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[paper] Review of physics-based compact models for emerging nonvolatile memories
Nuo Xu1, Pai-Yu Chen2, Jing Wang1, Woosung Choi1, Keun-Ho Lee3, Eun Seung Jung3, Shimeng Yu2
Review of physics-based compact models for emerging nonvolatile memories
1Device Lab, Samsung Semiconductor Inc., San Jose, CA 95134, USA
2School of ECEE, Arizona State University, Tempe, AZ 85281, USA
3Semiconductor R&D Center, Samsung Electronics, Hwasung-si, Gyeonggi-do, Korea
Journal of Computational Electronics, 2017, pp. 1-13
https://doi.org/10.1007/s10825-017-1098-0
Abstract: A generic compact modeling methodology for emerging nonvolatile memories is proposed by coupling comprehensive physical equations from multiple domains (e.g., electrical, thermal, magnetic, phase transitions). This concept has been applied to three most promising emerging memory candidates: PCM, STT-MRAM, and RRAM to study their device physics as well as to evaluate their circuit-level performance. The models’ good predictability to experiments and their effectiveness in large-scale circuit simulation suggest their unique role in emerging memory research and development [read more...]
https://doi.org/10.1007/s10825-017-1098-0
SSCS Members Who Are 2017 IEEE Fellows
SSCS members who are IEEE Fellows pose with SSCS President, Jan Van der Spiegel and IEEE President, Karen Bartelson at ISSCC 2017. From left to right- Jan Van der Spiegel, Zhihua Wang, Andrei Vladimirescu, Carlo Samori, Borivoje Nikolic, Junichi Nakamura, Deog-kyoon Jeong, Hideto Hidaka, Payam Heydari, Edoardo Charbon, and Karen Bartleson
Oct 30, 2017
How to pick a #winning #IoT #business #model https://t.co/YjMfxPAEZB https://t.co/SDOt080Ka6
How to pick a #winning #IoT #business #model https://t.co/YjMfxPAEZB http://pic.twitter.com/SDOt080Ka6
— Wladek Grabinski (@wladek60) October 30, 2017
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October 30, 2017 at 03:39PM
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FOSDEM 2018 CAD and Open Hardware Devroom Call for Participation
(Also visible at https://www.ohwr.org/projects/ohr-meta/wiki/FOSDEM2018)
This is the call for participation in the FOSDEM 2018 devroom on Computer Aided Design (CAD) tools and Open Hardware, to be held on Saturday 3 February 2018 in Brussels, Belgium. We are looking for contributions under the form of talks and tutorials covering the following main topics:
- Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
- Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce,GHDL, Icarus and Verilator)
- Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen) and HDL synthesis tools (e.g. Yosys)
- Field solvers such as openEMS
- Mechanical 2D and 3D CAD tools such as LibreCAD, FreeCAD, OpenSCAD andSolveSpace
- Open Hardware projects such as the Teres laptop and the lowRISC SoC
- Inter-project opportunities for collaboration
We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS CAD and Open Hardware developments, share knowledge and identify opportunities to collaborate on development tasks. This devroom is an evolution of the EDA devroom we organised in 2015, 2016 and 2017.
The submission process: Please submit your proposals at
https://penta.fosdem.org/submission/FOSDEM18 before 1 December 2017.
If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself under Person -> Description -> Abstract. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "CAD and Open Hardware Devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.
Important dates
- 1 December 2017: deadline for submission of proposals
- 8 December 2017: announcement of final schedule
- 3 February 2018: devroom day
Recordings: The FOSDEM organisers hope to be able to live-stream and record all the talks. The recordings will be published under the same licence as all FOSDEM content (CC-BY). Only presentations will be recorded, not informal discussions and whatever happens during the lunch break. By agreeing to present at FOSDEM, you automatically give permission to be recorded. The organisers will agree to make exceptions but only for exceptional and well-reasoned cases.
Mailing list: Feel free to subscribe to the mailing list of the CAD and Open Hardware devroom to submit ideas, ask questions and generally discuss about the event:
Spread the word!
Oct 26, 2017
#Modeling the Performance of Nano Machined CMOS Transistors for Uncooled IR Sensing https://t.co/p4RnuHkJiZ
#Modeling the Performance of Nano Machined CMOS Transistors for Uncooled IR Sensing https://t.co/p4RnuHkJiZ
— Wladek Grabinski (@wladek60) October 26, 2017
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October 26, 2017 at 11:26AM
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Oct 25, 2017
UNIST Researchers Develop Highly Stable #Perovskite #Solar #Cells https://t.co/g1CN5I44r1 #paper... https://t.co/WSUSekJ1ky
UNIST Researchers Develop Highly Stable #Perovskite #Solar #Cells https://t.co/g1CN5I44r1 #paper... https://t.co/WSUSekJ1ky
— Wladek Grabinski (@wladek60) October 25, 2017
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October 25, 2017 at 08:47PM
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UNIST Researchers Develop Highly Stable #Perovskite #Solar #Cells https://t.co/g1CN5I44r1 #paper https://t.co/p6Jr0nPqF1
UNIST Researchers Develop Highly Stable #Perovskite #Solar #Cells https://t.co/g1CN5I44r1 #paper http://pic.twitter.com/p6Jr0nPqF1
— Wladek Grabinski (@wladek60) October 25, 2017
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October 25, 2017 at 08:47PM
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Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper https://t.co/LglxkaZ9PP
Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper https://t.co/LglxkaZ9PP
— Wladek Grabinski (@wladek60) October 25, 2017
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October 25, 2017 at 11:59AM
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Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper
Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper
— Wladek Grabinski (@wladek60) October 25, 2017
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October 25, 2017 at 11:59AM
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A Planar Junctionless FET Using SiC With Reduced Impact of Interface Traps: Proposal and Analysis https://t.co/g3qPsLKIqB #paper
A Planar Junctionless FET Using SiC With Reduced Impact of Interface Traps: Proposal and Analysis https://t.co/g3qPsLKIqB #paper
— Wladek Grabinski (@wladek60) October 25, 2017
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October 25, 2017 at 11:34AM
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Oct 24, 2017
Cryogenic characterization of CMOS technologies
A. Beckers, F. Jazaeri, A. Ruffino, C. Bruschini, A. Baschirotto and C. Enz
Cryogenic characterization of 28 nm bulk CMOS technology for quantum computing
47th ESSDERC, Leuven, Belgium, 2017, pp. 62-65.
Abstract: This paper presents the first experimental investigation and physical discussion of the cryogenic behavior of a commercial 28 nm bulk CMOS technology. Here we extract the fundamental physical parameters of this technology at 300,77 and 4.2 K based on DC measurement results. The extracted values are then used to demonstrate the impact of cryogenic temperatures on the essential analog design parameters. We find that the simplified charge-based EKV model can accurately predict the cryogenic behavior. This represents a main step towards the design of analog/RF circuits integrated in an advanced bulk CMOS process and operating at cryogenic temperature for quantum computing control systems [read more...] doi: 10.1109/ESSDERC.2017.8066592
R. M. Incandela, L. Song, H. A. R. Homulle, F. Sebastiano, E. Charbon and A. Vladimirescu
Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures
47th ESSDERC, Leuven, Belgium, 2017, pp. 58-61.
Abstract: The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations and measurements for DC and time-domain at 4 K and, for the first time, at 100 mK [read more...] doi: 10.1109/ESSDERC.2017.8066591
Oct 19, 2017
#opensource Summit Europe 2017 https://t.co/c1TgRIgzVE https://t.co/RZqPRisbbS
#opensource Summit Europe 2017 https://t.co/c1TgRIgzVE http://pic.twitter.com/RZqPRisbbS
— Wladek Grabinski (@wladek60) October 18, 2017
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October 18, 2017 at 11:41PM
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Oct 17, 2017
A Compact QS Terminal Charge and Drain Current #Model for DG Junctionless Transistors and Its Circuit Validation https://t.co/hTsw5blL8f
A Compact QS Terminal Charge and Drain Current #Model for DG Junctionless Transistors and Its Circuit Validation https://t.co/hTsw5blL8f
— Wladek Grabinski (@wladek60) October 17, 2017
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October 17, 2017 at 11:26AM
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[paper] Accurate diode behavioral model with reverse recovery
Stanislav Banáša,b, Jan DivÃnab, Josef DobeÅ¡b, Václav Paňkoa
aON Semiconductor, SCG Czech Design Center, Department of Design System Technology, 1. maje 2594, 756 61 Roznov pod Radhostem, Czech Republic
bCzech Technical University in Prague, Faculty of Electrical Engineering, Department of Radioelectronics, Technicka 2, 166 27 Prague 6, Czech Republic
Volume 139, January 2018, Pages 31–38
Highlights:
ABSTRACT: This paper deals with the comprehensive behavioral model of p-n junction diode containing reverse recovery effect, applicable to all standard SPICE simulators supporting Verilog-A language. The model has been successfully used in several production designs, which require its full complexity, robustness and set of tuning parameters comparable with standard compact SPICE diode model. The model is like standard compact model scalable with area and temperature and can be used as a stand-alone diode or as a part of more complex device macro-model, e.g. LDMOS, JFET, bipolar transistor. The paper briefly presents the state of the art followed by the chapter describing the model development and achieved solutions. During precise model verification some of them were found non-robust or poorly converging and replaced by more robust solutions, demonstrated in the paper. The measurement results of different technologies and different devices compared with a simulation using the new behavioral model are presented as the model validation. The comparison of model validation in time and frequency domains demonstrates that the implemented reverse recovery effect with correctly extracted parameters improves the model simulation results not only in switching from ON to OFF state, which is often published, but also its impedance/admittance frequency dependency in GHz range. Finally the model parameter extraction and the comparison with SPICE compact models containing reverse recovery effect is presented [read more...]
- The complex robust time and area scalable Verilog-A model of diode containing reverse recovery effect has been developed.
- Due to implemented reverse recovery effect the model is useful especially for high-speed or high-voltage power devices.
- The model can be used as stand-alone 2-terminal diode or as a parasitic p-n junction of more complex lumped macro-model.
- Two methods of model parameter extraction or model validation have been demonstrated.
ABSTRACT: This paper deals with the comprehensive behavioral model of p-n junction diode containing reverse recovery effect, applicable to all standard SPICE simulators supporting Verilog-A language. The model has been successfully used in several production designs, which require its full complexity, robustness and set of tuning parameters comparable with standard compact SPICE diode model. The model is like standard compact model scalable with area and temperature and can be used as a stand-alone diode or as a part of more complex device macro-model, e.g. LDMOS, JFET, bipolar transistor. The paper briefly presents the state of the art followed by the chapter describing the model development and achieved solutions. During precise model verification some of them were found non-robust or poorly converging and replaced by more robust solutions, demonstrated in the paper. The measurement results of different technologies and different devices compared with a simulation using the new behavioral model are presented as the model validation. The comparison of model validation in time and frequency domains demonstrates that the implemented reverse recovery effect with correctly extracted parameters improves the model simulation results not only in switching from ON to OFF state, which is often published, but also its impedance/admittance frequency dependency in GHz range. Finally the model parameter extraction and the comparison with SPICE compact models containing reverse recovery effect is presented [read more...]
FIG: Solving the recursive calculation of reverse recovery charge
Oct 15, 2017
Software #model multi-level #photonic #IC designs https://t.co/24rtqqVTBH
Software #model multi-level #photonic #IC designs https://t.co/24rtqqVTBH
— Wladek Grabinski (@wladek60) October 14, 2017
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October 15, 2017 at 01:05AM
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