[paper] Low-Frequency Noise in Single-Layer Graphene FETs

An extended low-frequency noise compact model for single-layer graphene FETs 

including correlated mobility fluctuations effect

Nikolaos Mavredakis, Anibal Pacheco-Sanchez, and David Jiménez

https://arxiv.org/pdf/2512.08388

Departament d’Enginyeria Electrònica, Escola d’Enginyeria, Universitat Autònoma de Barcelona, Bellaterra 08193 (SP)
Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, 18011 Granada (SP)

Abstract: Correlated mobility fluctuations are considered in the physics-based carrier number fluctuation (ΔΝ) low-frequency noise (LFN) compact model of single-layer graphene field effect transistors (GFET) in the present study. Trapped charge density and Coulomb scattering coefficient ΔΝ LFN parameters are obtained after applying a parameter extraction methodology, adapted from conventional silicon technologies,to the linear ambipolar regions of GFETs. Appropriate adjustments are considered in the method according to GFETs’physical characteristics. Afterwards, Hooge mobility as well asseries resistance fluctuations LFN parameters can be extracted.The updated LFN model is validated with experimental data from various long and short-channel GFETs at an extendedrange of gate and drain bias conditions.

Fig: SID2/ID2 vs. VGS at 1 Hz for B (a) and A (b) -type RF GFETs with W=12μm and L=100nm

at VDS=60 mV. Markers: measurements, solid lines:model, dashed lines in (b): 

θint=0 V-1. Different colors represent different LFN contributions.

Acknowledgments: This work has received funding from the European Union’s Horizon2020 research and innovation programme under grant agreements NoGrapheneCore3 881603, from Ministerio de Ciencia, Innovación y Universidades under grant agreements RTI2018-097876-B-C21(MCIU/ AEI/ FEDER, UE), PID2021-127840NB-I00(MCIN/AEI/FEDER, UE), and CNS2023-143727 RECAMBIO (MCIN/AEI/ 10.13039 /501100011033). 

This work is also supported by the European Union Next Generation EU/PRTR research project.

[mos-ak] [Final Program] MOS-AK LatAm Webinar, Dec. 12, 2025

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK LatAm Workshop

(online), Dec. 12, 2025

The End‑of‑Year MOS-AK Workshop/Webinar on Compact/SPICE Modeling will be held online on Dec. 12, 2025. We invite you to join this webinar to learn from the experts in Compact SPICE modeling, Verilog‑A standardization, and FOSS CAD/EDA IC design support for OpenPDKs, internationally, with particular focus on Latin America

Venue: MOS-AK LatAm (Webinar)
Online Webinar Access Link: https://meet.jit.si/MOS-AK_LA_2025

• Final Workshop Program: Dec. 12 2025
San Francisco, 09:00 - 11:00
Rio de Janeiro, 14:00 - 16:00
Geneve, 18:00 - 20:00

T_1	OpenPDK LatAm Krzysztof Herman IHP (D)
T_2	AI/ML-Driven Device Modeling for Advanced Nodes, RF and Power Applications Fahad Usmani Keysight Technologies (US)
T_3	Design and Integration of Multiple Open-Source Analog Circuits Fabricated in SKY130 Technology within Silicluster v2 Uriel Jaramillo Toral* Hector Emmanuel Muñoz Zapata and Susana Cisneros Ortega CINVESTAV (MX)
T_4	SemiCoLab, A Multi-Project ASIC Platform for Democratizing Chip Design Emilio Baungarten, Susana Ortega, Miguel Rivera, and Francisco Javier CINVESTAV (MX)
T_5	Building an Ecosystem Through IC Education in Colombia: A Model for Emerging Semiconductor Regions Juan Sebastián Moya Baquero SymbioticEDA
T_6	Silicon-Proven Learning With OpenPDKs and MPW Access for IC Education Eduardo Holguin Weber Universidad San Francisco de Quito (EC)
T_7	OpenPDK Mismatch Testchip Juan Pablo Martinez Brito CEITEC S.A. (BR)
T_8	Physics-Based Modeling and Charge Density Saturation in GaN/AlGaN MOS-HEMTs Ashkhen Yesayan, Farzan Jazaeri, Jean-Michel Sallese EPFL (CH)

W.Grabinski for Extended MOS-AK Committee

WG111225

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[paper] Noise Propagation and Statistic Variability in MOSFETs

Raphael Chatzipantelis, Loukas Chevas, Nikolaos Makris and Matthias Bucher

Noise Propagation and Statistic Variability in MOSFETs Using Probability Density Functions

Fluctuation and Noise Letters (Accepted Paper)

DOI: 10.1142/S0219477525400255

1) School of Electrical and Computer Engineering, Technical University of Crete, Chania 73100, Greece
2) Foundation for Research and Technology Hellas, Heraklion 70013, Greece,

Abstract: Probability density functions using stochastic methods are shown to be an effective tool in the context of MOSFET noise and variability modeling. These methods are employed here in the context of the charge-based EKV MOSFET model. As an example, a Gaussian noise density function applied at the gate or the source of a MOSFET causes a corresponding drain current noise density function, which may be expressed analytically as a function of inversion coefficient only. The same expression may be used to model drain current variability due to MOSFET parameters such as threshold voltage. Furthermore, the method is extended to variations of quantities such as transconductance and transconductance-to-current ratio. The method shows promise in variability modeling of MOSFETs and may complement traditional approaches.

FIG: Comparing the traditional ”small-signal” transconductance method with the stochastic PDF method for 𝑖𝑓, derived from the charge-based model, where in both cases the same noise (or variability) at the gate is applied (𝑉𝐺= 87mV, 𝜎𝑉𝐺=10mV), centered at 𝑖𝑓=2, showing slightly different mean and ±3𝜎 values, while the tail distributions differ significantly.

Acknowledgements: The authors gratefully acknowledge Dr. Predrag Habas from EM Microelectronic S.A. for valuable discussions and wafers for noise and statistical analysis. This work was partly funded by the European Union, and by Greek National funds, under the topic DIGITAL- Chips-2024-SG-CCC-1 - Competence Centers, Project No 101217803 - HCCC.

[semiwiki] Revolution EDA

Revolution EDA: A New EDA Mindset for a New Era

by Semiwiki Admin in Category: EDA on 11-17-2025 at 6:00 am

Key Takeaways

• Revolution EDA introduces an open-source core platform inspired by Visual Studio Code, allowing rapid development and integration with modern machine learning workflows.
• The platform uses JSON for design data storage, making it AI-readable and eliminating data format friction, which contrasts with traditional binary databases.
• Revolution EDA provides a complete front-end design environment with advanced schematic and layout editors, incorporating Python for dynamic functionalities.

Murat Eskiyerli, PhD, is the founder of Revolution EDA  with the tagline “A new EDA mindset for a new era.”  The revolution won’t happen overnight. But it has to start somewhere [ read more... ] 

[mos-ak] [Announcement] MOS-AK LatAm Webinar, Dec. 11-12, 2025

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK Workshop

LatAm (online), Dec. 11-12, 2025

The End‑of‑Year MOS-AK Workshop/Webinar on Compact/SPICE Modeling will be held online on December 11–12, 2025. We invite you to join this webinar and learn from experts in Compact SPICE modeling, Verilog‑A standardization, and FOSS CAD/EDA design support for OpenPDKs. The MOS-AK LatAm Workshop provides a forum to: Strengthen networks and discussions among experts in compact/SPICE modeling; Promote open information exchange on Verilog‑A standardization; Connect academic and industrial specialists in the modeling field; Gather feedback from technology manufacturers, circuit designers, and CAD/EDA tool developers supporting foundry/fabless interface strategies with a focus on OpenPDKs (e.g., Skywater/GF CMOS, IHP RF BiCMOS)

 

Important Dates:

• 1st Announcement: Nov. 2025
• Final Workshop Program: Dec.1 2025
• MOS-AK LatAm online/webinar: Dec. 11-12, 2025

MOS-AK/LatAm Speakers Tentative List (alphabetic order):

• Sergio Bampi, Mateus Grellert and team at UFRGS (BR)
• Juan Pablo Martinez Brito, CEITEC S.A. (BR)
• Carlos Galup, Márcio Cherem Schneider and team at UFSC (BR))
• Krzysztof Herman, IHP (D)
• Eduardo Holguín and team at Universidad San Francisco de Quito (EC)
• Uriel Jaramillo and team from CINVESTAV (MX)
• Peter Lee, Si2 CMC Chair (US)
• Jorge Ivan Marin Hurtado, Universidad del Quindío (CO)
• Mehdi Saligane, Uni. Brown (US) IEEE SSCS TC-OSE Chair
• Fahad Usmani, Keysight (US)

Online Abstract Submission will be open (any related enquiries can be sent to abstracts@mos-ak.org)
Online Free Registration will be open (any related enquiries can be sent to registration@mos-ak.org)

W.Grabinski for Extended MOS-AK Committee

WG221125

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[C4P] ICMC2026 Submission Deadline: February 1, 2026 (4-page paper)

ICMC2026 | July 30-31, 2026| Long Beach, CA

Call for Papers
Submission Deadline: February 1, 2026  (4-page paper)

The Compact Model Coalition (CMC) brings academia and industry partners together in the development and standardization of compact models for semiconductor devices. For more than 30 years, the CMC has been instrumental in creating standardized and verified models for designers to use in their increasingly complex circuits for SPICE simulation. The CMC is organizing the second edition of the International Compact Modeling Conference, cosponsored by IEEE EDS. It will focus uniquely on compact device models, their development, and broad application in the semiconductor industry. You are invited to participate in the evolution of these models, guiding model development to help circuit designers achieve the best circuit performance possible, and enabling foundries to leverage the strength of their device fabrication to the full extent. Join world experts in design, process technology, and model development for a two-day in-person event to discuss state-of-the-art semiconductor device modeling, offering a rare opportunity to present and learn about this core element of circuit design and how to get the most from these global collaborations.

 
HIGHLIGHTED THEMES FOR ICMC 2026 

This year, ICMC especially encourages submissions in the following domains: 

• Electrostatic Discharge (ESD) modeling for protection design
• Modeling of parasitic BJT activation, snapback behavior, ESD stress and breakdown, transient response, failure prediction, etc.
• Reliability and aging-aware compact models and simulation techniques
• for degradation mechanisms such as Bias Temperature Instability (BTI), Hot Carrier Degradation (HCI), Time Dependent Dielectric Breakdown (TDDB)
• self-heating and circuit reliability prediction
• AI or Machine Learning for model development, parameter extraction, circuit simulation efficiency, etc. 

GENERAL TOPICS 

 We are also seeking submissions in the following domains.

Application of Device Models Innovative application of CMC standard device models Designer's perspective: best practices, novel use, and benefits of standard device models to improve circuit design and system performance. Use of compact models to demonstrate foundry device capabilities Device Model Development Modeling of physical phenomena: Statistical variation, noise and fluctuations, RF and high-frequency effects, layout effects, etc. Methodologies to assist in model development, practices for coding, quality assurance, circuit simulator integration, etc. Parameter extraction, measurement techniques, model calibration, validation, and verification methodologies.	Model Enhancements and Implementations Model extensions to capture additional device features (leakage, capacitance, second-order dependencies)or expand the operating range of existing devices (bias, power, temperature, frequency, etc.) Model enhancements to support the design of new or demanding circuits Model workflow, implementation, and integration into the design environment (PDK) Computing/simulation platforms, simulation algorithms, and methodologies to improve simulation performance (parallel processing, etc.) Models for established device types that currently lack standardization. Emerging devices Modeling of emerging and future devices:compact models for novel device technologies and architectures that could further revolutionize circuit performance and design flow. For example, complementary FET, ferroelectric devices, silicon photonics, MRAM, RRAM, cryogenic, quantum computing, 2D-materials, oxide semiconductors, etc.
IMPORTANT DATES February 1, 2026 Submission deadline  (4-page paper) April 6, 2026 Acceptance notification May 10, 2026 Final version for publication July 30-31, 2026 Conference takes place For more details, visit: 2026.si2-icmc.org	ICMC2026 COMMITTEE General Chair: Shahed Reza (Sandia National Laboratories) Vice Chair: Harshit Agarwal (IIT Jodhpur) Technical Program Chair: Gert-Jan Smit (NXP) Technical Program Vice-Chair: Girish Pahwa (NYCU Taiwan) Treasurer: Leigh Anne Clevenger (Si2) Publicity Committee Chair: Wladek Grabinski (MOS-AK)

[C4P] Exploring Beyond-CMOS Paradigms for Energy-Efficient Computing

Exploring Beyond-CMOS Paradigms for Energy-Efficient Computing

Call for Papers

Excited to announce that our Research Topic is now open for submissions! As CMOS technology reaches its limits, emerging devices like NCFETs, TFETs, spintronic systems, 2D materials, wide-bandgap semiconductors, and MEMS are paving the way for next-generation low-power computing. We invite Original Research, Reviews, Mini-Reviews, and Perspectives from researchers working on innovative materials, devices, models, circuits, and system-level demonstrations.

• Summary Deadline: 13 Feb 2026
• Manuscript Deadline: 29 May 2026

Let’s push the boundaries of energy-efficient, beyond-CMOS electronics together! Submit your work and be part of this emerging frontier.

Call for Papers - Frontiers in Electronics with Impact Factor: 2.1

Topic editors

Fabrizio Bonani, Polytechnic University of Turin (IT)

Mariana Amorim Fraga, School of Engineering, UPM, São Paulo, (BR)

Sonal Shreya, Aarhus University (DK)

Abhishek Acharya, Sardar Vallabhbhai National Institute of Technology Surat (IN)

Topic coordinator

Khoirom Johnson Singh, Dhanamanjuri University, Imphal, Manipur (IN)

[IEEE EDS DL] Multifunctional materials for emerging optoelectronic technologies

IEEE EDS Distinguished Lecture

Hawaii Section Jt. Chapter, ED15/SSC37

December 19 @ 6:30 pm - 8:00 pm

Room: 244, Bldg: Holmes Hall, 2540 Dole St, Honolulu

Hawaii, United States, 96822

Dr. Federico Rosei from the University of Trieste will be presenting a Distinguished Lecturer Seminar titled "Multifunctional materials for emerging optoelectronic technologies" on Friday December 19th at 6:30PM. RSVP one week in advance for a headcount on food [register]

Abstract: functionalities. Such systems are then used as building blocks for the fabrication of various emerging technologies. In particular, nanostructured materials synthesized via the bottom–up approach present an opportunity for future generation low cost manufacturing of devices. We focus in particular on recent developments in solar technologies that aim to address the energy challenge, including third generation photovoltaics, solar hydrogen production, luminescent solar concentrators and other optoelectronic devices. 

Bio: Federico Rosei (MSc (1996) and PhD (2001) from the University of Rome “La Sapienza”) holds the Chair of Industrial Chemistry at the Department of Chemical and Pharmaceutical Sciences, University of Trieste since March 2023. Previously he was Full Professor at the Centre Énergie, Matériaux et Télécommunications, Institut National de la Recherche Scientifique, Varennes (QC) Canada, where he served as Director (07/2011–03/2019). He held the Canada Research Chair (Junior) in Nanostructured Organic and Inorganic Materials (2003–2013) and the Canada Research Chair (Senior) in Nanostructured Materials (2016–2023) and the UNESCO Chair in Materials and Technologies for Energy Conversion, Saving and Storage (2013–2023).

[paper] Compact Wide-Band Antenna

A. Anand Babu, K. Thenmalar

Design and Evaluation of a Compact Wide-Band Antenna for Wearable Wireless Applications

Tehnički vjesnik 32, 6(2025), 2437-2442

Original scientific paper DOI: 10.17559/TV-20241128002156

ECE, Vivekanandha College of Technology, Tiruchengode, Tamil Nadu, India
EEE, Vivekanandha College of Engineering for Women, Tiruchengode, Tamil Nadu, India

Abstract: This article presents a compact wide-band antenna designed for emerging wireless applications. The antenna utilizes a fiberglass-reinforced (FR4) substrate material with a thickness of 1.6 mm as its base. By varying the length and side edge dimensions of the antenna element, the design achieves a wide operational bandwidth ranging from 3.2 to 3.8 GHz, covering all new radio bands. Experimental optimization of various parameters has been conducted to ensure precise tuning within the desired frequency range. The antenna exhibits a uniform radiation pattern across its operating band, ensuring stable performance. Specific Absorption Rate (SAR) evaluations, conducted as per the Federal Communications Commission (FCC) guidelines, confirm the SAR values remain within the prescribed safety limit of 1.6 W/kg when the antenna is positioned on a human phantom model. The proposed antenna also demonstrates high radiation efficiency and peak gain, making it suitable for wearable applications where compact size and reliable performance are critical. This innovative design addresses the growing demand for wide-band antennas in wireless communication systems, emphasizing safety, efficiency, and adaptability for wearable technologies.

Fig: Electric field distribution over the radiating circle at (a) 3.45 GHz; (b) 3.7 GHz

(c) - (d) fabricated antenna images

[Free Session] Tokai Rika OpenPDK

Tokai Rika Shuttle Open PDK Commentary Free Session

Saturday, December 13, 2025 13:00~17:00 [and online]

WeWork Hibiya FORT TOWER 9th Floor, Conference Room 9R

1-1 Nishi-Shimbashi, Minato-ku, Tokyo

Time	Speaker	Topic
12:50	ISHI Club	1F Gathering
13:00	ISHI Club	Opening
13:00-13:30	OpenSUSI	Overview of Tokai Rika Shuttle PDK and future plans
13:30-14:30	jun1okamura	Outline of the production of DRC and LVS of Tokai Rika Shuttle PDK and explanation of contents
14:30-15:00	OpenSUSI	Break & Information Exchange
15:00-15:30	Mitch Bailey	Detailed explanation of LVS (Japanese lecture)
15:30-16:00	Hota (SIG's Playground)	How to 🚶 walk through open source PDK: "What is PDK in the first place?" "Where do you want to "read" PDK? "If you want to make your own PDK, where do you start?" and "Examples of what you have done so far".
16:00-16:30	OpenSUSI	PDK Conversation: jun1okamura x Hota x Mitch Bailey: Mr. Hota, an expert in commercial PDK development at a major domestic company, and Mitch Bailey, an expert in open PDK who has been performing structural checks and PDK maintenance of GDS submitted by eFabless, etc.
16:30-17:00	OpenSUSI	PDK Conversation / Honest Edition (No more online streaming will be done from now on): Continuing from the above, we plan to talk about things that cannot be said publicly. In a sense, this may be the real thing.
17:00	ISHI Club	Closing

Discord invitation link 

https://discord.gg/Sj47dJk8x7 

https://discord.gg/RwAWF5mZSR

[Book] Essential Semiconductor Physics

Essential Semiconductor Physics

Mark Lundstrom (Purdue University, USA)

New Era Electronics: A Lecture Notes Series

Pages: 424; October 2025

https://doi.org/10.1142/14454

This book is the fourth volume in the New Era Electronics lecture notes series, a compilation of volumes defining the important concepts tied to the electronics transition happening in the 21st century.

The lectures in this volume are about the underlying physics that makes semiconductor devices possible. The treatment is physical and intuitive; the text is descriptive, not heavily mathematical. The lectures are designed to be broadly accessible to students in science or engineering and to working engineers. They present an electrical engineering perspective, but those in other fields may find them a useful introduction to the approach that has guided the development of semiconductor technology for more than 75 years.

For those who use semiconductor devices, these lectures provide an understanding of the physics that underlies their operation. For those developing semiconductor technologies, these lectures provide a starting point for diving deeper into the physics, chemistry, and materials science relevant to semiconductors. Those who have taken advanced courses will see how specific topics fit into a broader framework. 

Book Sections

Front Matter; pp. i–xvi

Part 1: Materials Properties and Doping

• Lecture 1: Energy Levels to Energy Bands; pp. 3–16
• Lecture 2: Crystalline, Polycrystalline, and Amorphous Semiconductors; pp. 17–27
• Lecture 3: Miller Indices; pp. 29–39
• Lecture 4: Properties of Common Semiconductors; pp. 41–46
• Lecture 5: Free Carriers in Semiconductors; pp. 47–56
• Lecture 6: Doping; pp. 57–75

Part 2: Rudiments of Quantum Mechanics

• Lecture 7: The Wave Equation; pp. 79–99
• Lecture 8: Quantum Confinement; pp. 101–116
• Lecture 9: Quantum Tunneling and Reflection; pp. 117–129
• Lecture 10: Electron Waves in Crystals; pp. 131–145
• Lecture 11: Density of States; pp. 147–164

Part 3: Equilibrium Carrier Concentrations

• Lecture 12: The Fermi Function; pp. 167–177
• Lecture 13: Fermi-Dirac Integrals; pp. 179–190
• Lecture 14: Carrier Concentration vs. Fermi Level; pp. 191–203
• Lecture 15: Carrier Concentration vs. Doping Density; pp. 205–213
• Lecture 16: Carrier Concentration vs. Temperature; pp. 215–228

Part 4: Carrier Transport, Recombination, and Generation

• Lecture 17: Current Equation; pp. 231–250
• Lecture 18: Drift Current; pp. 251–270
• Lecture 19: Diffusion Current; pp. 271–280
• Lecture 20: Drift-Diffusion Equation; pp. 281–288
• Lecture 21: Carrier Recombination; pp. 289–308
• Lecture 22: Carrier Generation; pp. 309–323

Part 5: The Semiconductor Equations

• Lecture 23: The Semiconductor Equations; pp. 327–342
• Lecture 24: Energy Band Diagrams; pp. 343–361
• Lecture 25: Quasi-Fermi Levels; pp. 363–374
• Lecture 26: Minority Carrier Diffusion Equation; pp. 375–396

Back Matter; pp. 397–406

[paper] 28 GHz Wireless Channel for a Quantum Computer at 4K

Ama Bandara∗, Viviana Centritto Arrojo∗, Heqi Deng†, Masoud Babaie†, Fabio Sebastiano†, Edoardo Charbon‡, Evgenii Vinogradov∗, Eduard Alarcon∗, Sergi Abadal∗

28 GHz Wireless Channel Characterization for a Quantum Computer Cryostat at 4 Kelvin

arXiv:2510.16962v1 [quant-ph] 19 Oct 2025

∗Nanonetworking Center in Catalunya, Universitat Politecnica de Catalunya, Barcelona (SP)
† Delft University of Technology (NL)
‡ Ecole Polytechnique F ́ed ́erale de Lausanne (EPFL, CH) 

Abstract: The scalability of quantum computing systems is constrained by the wiring complexity and thermal load introduced by dense wiring for control, readout and synchronization at cryogenic temperatures. To address this challenge, we explore the feasibility of wireless communication within a cryostat for a multi-core quantum computer, focusing on wireless channel characterization at cryogenic temperatures. We propose to place on-chip differential dipole antennas within the cryostat, designed to operate at 28 GHz in temperatures as low as 4 K. We model the antennas inside a realistic cryostat and, using full-wave electromagnetic simulations, we analyze impedance matching, spatial field distribution, and energy reverberation due to metallic structures. The wireless channel is characterized through measured channel impulse response (CIR) across multiple receiver antenna positions. The results demonstrate potential for reliable shortrange communication with high Signal-to-Noise Ratio (SNR) and limited sensitivity to positional variation, at the cost of nonnegligible delay spread, due to significant multipath effects.

Fig: Spatial distribution of the electrical field across the cryostat as observed in the cross-section, 
general top view, and top view at the plane of the antennas.

Acknowledgements: Authors gratefully acknowledge funding from the European Commission via projects with GA 101042080 (WINC) and 101099697 (QUADRATURE).

[IEEE EDS MQ] Trends and Challenges in Microelectronics

IEEE EDS MQ “Trends and Challenges in Microelectronics”

Monday, October 13th, 2025

FACULTY OF ELECTRONIC ENGINEERING

University of Niš

Aleksandra Medvedeva 4, Niš, Serbia

8:00 Registration

8:30   Introductory Remarks and Opening Address

D. Danković, University of Niš, Serbia
Z. Marinković, University of Niš, Serbia

Session I: Chairmen: T. Grasser, V. Davidović

8:45   Device Engineering in E.V.E. Era for Sustainable Nanoelectronics and Nanosystems

S. Deleonibus; CEA/LETI, France

9:10 Neuromorphic Technologies for Autonomous Intelligent Systems at the Edge
[online] A. M. Ionescu; Swiss Federal Institute of Technology, Switzerland

9:30 Coffee break

9:40 Contacts at the Nanoscale and for Nanomaterials

H. Wong; University of Hong Kong, Hong Kong

10:05 Unlocking the Potential of Multifunctional Devices

[online] N. El-Atab; KAUST Saudi Arabia

10:25 Coffee break

Session II: Chairmen: H. Wong, D. Danković

10:35 Steep-slope Devices: Prospects and Challenges

E. Gnani; University of Bologna, Italy

11:00 Modeling FinFETs, Nanowires and Stacked Nanosheets with Temperature

[online] A. Cerdeira; CINVESTAV-IPN, Mexico

11:20 Coffee break

11:30 The IHP OpenPDK Initiative: RoadMap Update

W. Grabinski; IEEE EDS R8 Chair

11:55 A Review of Lambert’s W Function Utilization in Nanodevice Modeling

[online]A. Ortiz-Conde; University Simon Bolivar, Venezuela

12:15 Coffee break

12:25 Benchmarking Insulators for Devices Based on 2D Materials

T. Grasser; Technical University of Vienna, Austria

 

[Internship] Open Source CAD Design Flows

A great opportunity at CEA-Leti in Grenoble, France! This 6-month internship focuses on open source CAD design flows with related PDK, targeting final-year engineering or Master 2 students with an analog/digital design profile.

Description

Are you eager to explore the backstage of microelectronics and learn how to turn a circuit design into a chip ready for fabrication? This internship invites you to take on an exciting challenge: setting up and running a complete open source design flow on related process technology, using an existing SAR ADC design as a motivating example.

The core mission is not to redesign the ADC, but to master the flow that makes such a design possible: installing the tools, configuring the PDKs, and validating each step of the process. How do you configure and launch open source EDA tools? How do you run simulations, placement and routing, and physical verification checks? What are the strengths and limitations of open source technologies in microelectronics design IC? You will be encouraged to explore these questions and propose your own answers.

• Starting date: Spring 2026
• Duration: 5-6 months
• Location: Grenoble, France

Your main tasks will include:

• Installing and configuring the open source design environment (PDK, EDA tools, automation scripts).
• Running the design flow on an existing SAR ADC as a case study.
• Carrying out simulation, synthesis, place-and-route, and DRC/LVS verification.
• Identifying bottlenecks and documenting reproducible solutions.

The student will be supported by an experienced team, with close mentoring and external collaborations to enrich your learning. He won't be left alone with the complexity of the flow – he will be guided, encouraged to test, and empowered to take initiatives. Indicative time allocation: ~30% installation and flow automation, 30% simulation and verification, 30% design adaptation, 10% analysis and scientific dissemination.

Candidate Profile

You are a master's student in microelectronics, embedded systems, or related fields. You have basic knowledge in digital/analog design, simulation, or VLSI concepts. You have basic experience writing scripts in bash/csh and are comfortable working in a Linux environment.

Supervisors: 

Youcef Fellah & Guillaume Regis

To apply, please contact: <youcef.fellah@cea.fr>

[mos-ak] [C4P] ICMTS 2026 Mar. 23-26, 2026 in Matsue, Japan

IEEE International Conference on Microelectronic Test Structures

Mar. 23-26, 2026 at Kunibiki-Messe Convention Center in Matsue, Japan

ICMTS 2026 Call for Papers

Abstract submission deadline: Nov 15, 2025

Looking for the best opportunity to present and discuss your ideas and results about test structures, measurements, and characterization? This is your chance! Join the 38th ICMTS conference.

This conference is co-sponsored by the IEEE Electron Devices Society. All presented papers will be submitted for potential inclusion in IEEE Xplore®. Original papers presenting new developments in topics relevant to ICMTS, include but not limited to test structures, measurements, and results, as outlined below. This one-track technical program will award a Best Paper that will be voted on by the Technical Program Committee. In addition, Tutorial Short Course will precede the main conference while several of the best measurement, equipment design, and manufacturing experts, will participate in the equipment exhibition and presentations.

• Design
• Methodologies, Verification
• Within-die circuits for process characterisation/monitoring
• Design enablement, characterisation and validation of digital and analog libraries
• Devices and Circuit Modelling
• Measurement techniques
• DC, AC and RF measurements: setup, test and analysis
• Reliability test - including thermal stability, failure analysis etc.
• Statistical analysis, variability, throughput increase, smart test strategies
• Use of machine learning and AI in analysis of data sets - parameter extraction etc.
• Wafer probing, within-die measurements, in-line metrology
• Throughput, testing strategies, yield enhancement and process control tests
• Applications
• Emerging memory technologies (single cell, arrays, and application in neural networks)
• Emerging transistor technologies for digital/analog/power applications
• Photonic devices - silicon integration, new displays (OLED, μ-displays)
• Flexible electronics and sensors (organic and inorganic materials)
• M(N)EMS, actuators, sensors, PV cells and other emerging devices

The author's abstract submission consists of up to four pages in PDF format (font-embedded). The first page should include a title, a 50-word summary, author name(s), full address, contact number and e-mail of the lead author, and any preference for oral or poster session presentation. The body of the abstract should consist of one page of text (800 to 1000 words) and up to two pages of major figures and tables.

The selection process will be based on the technical merit and will be highly weighted in favour of abstracts with high test structure content, giving a clear illustration of the test structure and including measurements and data analysis.

Abstract submission deadline: Nov 15, 2025

Notice of paper acceptance will be sent to the selected authors by Jan 17, 2026, with instructions for the expanded manuscript preparation for the conference proceedings. The deadline for submission of the final, camera-ready paper will be Feb 17, 2026.

Please join the ICMTS group at 

https://www.linkedin.com/groups/3804498    

if you have interest in all things, test and measurement.

Details of the venue, hotel, conference registration, etc. are available here.

If you have any questions, please contact the Technical Program Chair:

• Tatsuya OHGURO, tatsuya.ooguro@toshiba.co.jp
• Kejun XIA, kejun.xia@gmail.com

[mos-ak] [Special Issue] 7th International Sino MOS-AK Workshop

Special Issue on the 7th International Sino MOS-AK Workshop

Jun Zhang, Wladek Grabinski, Yuehang Xu (editors)

Int JNM, 38: e70114.

First published: 07 September 2025

https://doi.org/10.1002/jnm.70114

1. College of Integrated Circuit Science and Engineering, Nanjing University, Jiangsu (CN)

2. MOS-AK and GMC Consulting (CH)

3. School of Electronic Science and Engineering, Uni. Chengdu, Sichuan (CN)

As device structures become increasingly complex, with the continuous emergence of novel materials, unconventional architectures, and new physical phenomena, the coupling of multiple physical domains, including thermal, electrical, and optical effects, is becoming ever more prevalent. At the same time, rising development and manufacturing costs place additional demands on modelers to deliver representations that are both accurate and computationally efficient across the entire chain from device physics to circuit behavior. Modeling serves two complementary purposes: Theoretical models provide insight into the operating principles of devices, while also guiding design optimization and enabling engineers to fully exploit intertwined physical effects. Analytical modeling, however, often requires careful trade-offs among accuracy, generality, and simplicity. Models must be predictive enough to inform design while offering meaningful physical insight. In modern semiconductor devices, which often feature three-dimensional geometries, solving the coupled semiconductor physics equations analytically is extremely challenging or even impossible. Closed-form solutions are typically unattainable, so judicious simplifications are necessary to ensure that models remain tractable and practically useful.

The papers in this Special Issue address these challenges by balancing physical fidelity with computational efficiency. They deepen our understanding of device physics while providing models that are both insightful and practical, with applications spanning cryogenic electronics, wide-bandgap devices, and radiation-hardened systems.

Su et al. present a charge-based analytical model for bulk MOSFETs, that is, valid down to 10 mK. Their work clarifies the interface-trap-dominated mechanisms that lead to threshold voltage divergence between NMOS and PMOS devices and quantifies significant analog parameter enhancements, including a 73% increase in PMOS cutoff frequency at 4 K. These findings are essential for quantum-control electronics. Complementing this, Mao et al. provide a comprehensive review of four physics-based compact models for GaN HEMTs, namely MVSG, ASM HEMT, EPFL, and QPZD. They analyze how each model addresses challenges such as trapping effects, self-heating, and process variability, and highlight emerging opportunities for combining physical models with machine learning to accelerate parameter extraction and quantify uncertainties. In the area of radiation-tolerant electronics, Xu et al. introduce a machine-learning approach using an ant-colony-optimized neural network. By adaptively sampling critical waveform regions, their method achieves an RMS error of only 0.82% in predicting single-event transient currents, surpassing the fidelity limits of traditional double-exponential pulse models and enabling high-precision radiation effect simulation for aerospace applications. Meanwhile, Deng et al. demonstrate a practical strategy for AI-assisted SPICE integration. They employ geometry-parameterized scaling laws for spiral inductors and machine-augmented Power MOS trans-conductance models to accelerate parameter extraction by an order of magnitude while preserving full SPICE compatibility. This approach significantly streamlines industrial design workflows.

Collectively, these contributions point to a trend toward physics-informed, data-driven co-design methodologies. By combining rigorous physical insight with computationally efficient, machine learning–aware workflows, they enable robust optimization of devices and circuits across a wide range of applications, from quantum interfaces to aerospace systems.

Future research should prioritize the development of standardized interfaces between AI tools and physical models, the extension of models to three-dimensional integrated wide-bandgap architectures, and the establishment of co-design frameworks for emerging ultra wide–bandgap materials capable of operating in environments ranging from near-zero Kelvin to orbital radiation conditions. We sincerely thank all authors for their outstanding contributions, which have advanced the frontier of semiconductor modeling science.

[Read more...]

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[Deadline] extended to Oct.15 2026

10th IEEE Electron Devices Technology and Manufacturing

(EDTM 2026) Conference

https://ieee-edtm.org/

March 1-4, 2026 Penang, Malaysia 

EDTM2026 paper submission date has been extended to 15th October 2025

Submit your papers today in any of the 13 tracks and see you in Penang, Malaysia from 1st - 4th March 2026.

• Contributed papers will be judged for the best paper award for each technical track
• Each track will have Invited Speakers. Meet prominent Plenary and Keynote Speakers from Industry and academia for research, networking, innovation and commercialization purposes
• Exhibition and sponsorship opportunities to showcase breakthrough technology
• Extended versions of accepted papers to be published in 
• EEE Transactions on Materials for Electron Devices (T-MAT) and 
• Journal of IEEE Electron Devices Society (JEDS)

[workshop] Advances in Semiconductor and Emerging Devices for Chip Design

5-Day Online International Workshop on

Recent Advances in Semiconductor and Emerging Devices for Chip Design

Oct. 6-10, 2025

Organized by the Department of Electronics, Dhanamanjuri University (DMU), Manipur,

in Collaboration with IEEE Silchar Subsection

Upcoming 5-Day International Workshop on “Recent Advances in Semiconductor and Emerging Devices for Chip Design” (6–10 October 2025) organized by Dhanamanjuri University (DMU) Manipur, in collaboration with IEEE Silchar Section. This unique event, led by Dr. Khoirom Johnson Singh, Ph.D. and his dedicated team, brings together global experts from India, Europe, and beyond. Register Online

With speakers covering topics from GaN devices and memristors to cryogenic CMOS, nanosheet FETs, biomedical circuits, and spintronics for novel computing, this workshop will serve as a melting pot of ideas, a platform for young researchers and students to learn, question, and seed new collaborations.

Education equips young minds with the foundations of knowledge, preparing them to understand technological advancements and their role in shaping society. Yet, in research, knowledge alone is not enough. To truly innovate, we must disseminate our work, engage with peers, and foster collaborations across disciplines and borders. This is where the seeds of research truly take root and grow.

Collaboration is more than sharing data or co-authoring papers. It is about bringing together diverse perspectives, connecting physics with engineering, theory with experimentation, and academia with industry. Interdisciplinary approaches not only accelerate breakthroughs, but also open new directions that no single researcher could achieve alone.

Register Online...

[paper] Is there anything left to do in TCAD?

Z. Stanojevic, F. Schanovsky, G. Rzepa, X. Klemenschits, H. Demel, 

O. Baumgartner, C. Kernstock, and M. Karner

Is there anything left to do in TCAD?

SISPAD  in Grenoble, Sept. 24 2025

https://sispad2025.inviteo.fr/

1. Global TCAD Solutions GmbH., Bosendorferstraße 1/12, 1010 Vienna (A) 

Abstract: Over the past decade, the development of commercial technology computer-aided design (TCAD) software has followed an evolutionary rather than revolutionary path. Alongside established continuum and particle-based approaches in both process and device simulation, advanced carrier transport models - such as deterministic bulk and subband Boltzmann transport equation (BTE) solvers and non-equilibrium Green’s functions (NEGF) - have been incorporated into the TCAD toolkit for single-device simulation. At the system level, the field of design-technology co-optimization (DTCO) has expanded to encompass variability, reliability, and the extension of TCAD methodologies from devices to circuits. However, most of these innovations were introduced over a decade ago, prompting the question: What remains to be developed in TCAD? We address this question by analyzing current limitations and potential future directions in TCAD development across three key dimensions: (1) fidelity, (2) integration, and (3) efficiency - each with particular relevance in commercial and industrial contexts. We examine ongoing challenges in classical TCAD, advanced transport modeling, and DTCO flows, and point to potential directions for future developments. Among these, we include various methodologies related to machine learning and hardware accelerators, particularly within the efficiency dimension.

FIG: Device 3D structure generated from a layout (GDSII) and a technology file

See also...

[paper] THz MOST based on aligned carbon nanotube arrays

Jianshuo Zhou, Zipeng Pan, Li Ding, Lin Xu, Xiaohan Cheng, Haitao Li, Fenfa Yao, Chuanhong Jin, Maguang Zhu, Lijun Liu, Huiwen Shi, Zhiyong Zhang and Lian-Mao Peng

Terahertz metal–oxide–semiconductor transistors based on aligned carbon nanotube arrays. 

Nat Electron (2025)

DOI: https://doi.org/10.1038/s41928-025-01463-6

1. Key Laboratory for the Physics and Chemistry of Nanodevices and Center for Carbon-based Electronics, Peking University
2. Hunan Institute of Advanced Sensing and Information Technology, Xiangtan University, Xiangtan, China
3. Chongqing Institute of Carbon-based Integrated Circuits, Peking University, Chongqing, China
4. Academy for Advanced Interdisciplinary Studies, Peking University, Beijing, China
5. State Key Laboratory of Silicon and Advanced Semiconductor Materials, Zhejiang University, Hangzhou, China
6. Frontiers Science Center for Nano-optoelectronics, Peking University, Beijing, China

Abstract: Films of aligned semiconducting carbon nanotubes could be used to build complementary metal–oxide–semiconductor field-effect transistors for digital integrated circuits and radio-frequency transistors for terahertz analogue integrated circuits. However, the operating frequencies of such devices remains too low for potential application in the sixth generation of wireless communications. Here we report metal–oxide–semiconductor field-effect transistors that are based on aligned carbon nanotube films and have a cut-off frequency beyond 1 THz. By optimizing gate structures and fabrication processes, we create devices with a gate length of 80 nm that have a carrier mobility of over 3,000 cm2 V−1 s−1, as well as an on-state current of 3.02 mA µm−1, a peak transconductance of 1.71 mS μm−1 at a bias of −1 V, and a saturation velocity of 3.5 × 107 cm s−1. By introducing a Y-shaped gate, we also create devices with gate lengths of 35 nm that have an extrinsic cut-off frequency (fT) of up to 551 GHz and a maximum oscillation frequency (fmax) of 1,024 GHz. Finally, we use devices with a gate length of 50 nm to fabricate mmWave-band (30 GHz) radio-frequency amplifiers that have a gain of up to 21.4 dB.

Fig: Characteristics of Y-gate structure in A-CNT MOSFETs.

Acknowledgements: This work is supported by the National Key Research & Development Program (grant number 2022YFB4401603 to L.D.) and Natural Science Foundation of China (grant numbers 62171004 to L.D., 92477201 to L.-M.P. and 62225101 to Z.Z.).