[GitHub] Heat Map of Developers in Africa

Commonwealth Report "Open Source Africa" 

by OpenUK

The heatmap illustrates the distribution of developers with GitHub accounts across Africa. It shows that accounts are dispersed in multiple regions throughout the continent. Among the countries highlighted in the OpenUK report, Nigeria has the largest number of users with approximately 1.8 million accounts, followed by Kenya with 666,020 accounts and Rwanda with 85,978 accounts.
[Read More] in recent Commonwealth Report "Open Source Africa" by OpenUK

[paper] ULTRARAM Neuromorphic Memory Device

Abhishek Kumar, Peter D. Hodgson, Manus Hayne, and Avirup Dasgupta

Artificial synapse based on ULTRARAM memory device for neuromorphic applications

Journal of Applied Physics 139, no. 12 (2026)

DOI: 10.1063/5.0314826

1. Department of Electrical Engineering and Computer Sciences, UCB (USA)

2. Department of Physics, Lancaster University, Lancaster LA1 4YB (UK)

3. Quinas Technology Limited, Lancaster LA1 4YB, (UK)

4. Department of Electronics and Communication Engineering, IIT Roorkee (IN)

Abstract: The memory demands of large-scale deep neural networks (DNNs) require synaptic weight values to be stored and updated in off-chip memory, such as dynamic random-access memory, which reduces energy efficiency and increases training time. Monolithic crossbar or pseudo-crossbar arrays using analog non-volatile memories, which can store and update weights on-chip, present an opportunity to efficiently accelerate DNN training. In this article, we present on-chip training and inference of a neural network using an ULTRARAM memory device-based synaptic array and complementary metal–oxide–semiconductor (CMOS) peripheral circuits. ULTRARAM is a promising emerging memory exhibiting high endurance (⁠> 10E7P/E cycles), ultrahigh retention (⁠>1000 years), and ultralow switching energy per unit area. A physics-based compact model of ULTRARAM memory device has been proposed to capture the real-time trapping/de-trapping of charges in the floating gate and utilized for the synapse simulations. A circuit-level macro-model is employed to evaluate and benchmark the on-chip learning performance in terms of area, latency, energy, and accuracy of an ULTRARAM synaptic core. In comparison with CMOS-based design, it demonstrates an overall improvement in area and energy by 1.8x and 1.52x⁠, respectively, with 91% of training accuracy.

FIG: Schematic of an ULTRARAM memory cell and the corresponding transmission electron microscope image of the device’s epilayers

Acknowledgments: This work was supported in part by the Quinas Technology Limited, Lancaster, United Kingdom; Indian Institute of Technology Roorkee, India; and Prime Minister’s Research Fellowship, Ministry of Education, Government of India under Grant No. PM-31-22-773-414.

Data Availability: The data that support the findings of this study are available within the article.

[github] NVC: VHDL compiler and simulator

 

https://cameron-eda.com/

NVC is a VHDL compiler and simulator

https://github.com/kev-cam/nvc

NVC supports almost all of VHDL-2008 with the exception of PSL, and it has been successfully used to simulate several real-world designs. Experimental support for Verilog and VHDL-2019 is under development. NVC has a particular emphasis on simulation performance and uses LLVM to compile VHDL to native machine code. NVC is not a synthesizer. That is, it does not output something that could be used to program an FPGA or ASIC. It implements only the simulation behaviour of the language as described by the IEEE 1076 standard. NVC supports popular verification frameworks including OSVVM, UVVM, VUnit and cocotb. See below for installation instructions.

Vendor Libraries

NVC provides scripts to compile popular verification frameworks and the simulation libraries of common FPGA vendors

• For OSVVM use nvc --install osvvm
• For UVVM use nvc --install uvvm
• For Xilinx ISE use nvc --install ise
• For Xilinx Vivado use nvc --install vivado and additionally nvc --install xpm_vhdl
  if you require simulation models of the XPM macros
• For Altera Quartus use nvc --install quartus
• For Lattice iCEcube2 use nvc --install icecube2
• For Free Model Foundry common packages use nvc --install fmf

[Open Source Survey] From RTL to Fabrication

Emilio Isaac Baungarten-Leon

From RTL to Fabrication: Survey of Open-Source EDA Tools and PDKs

Electronics 2026, 15(5), 1048;

DOI: 10.3390/electronics15051048

* Departamento de Electromecánica, Universidad Autónoma de Guadalajara, Zapopan 45129, Mexico

Abstract: This article aims to synthesize the current ecosystem of open-source tools for Integrated Circuit (IC) design, covering the entire digital design flow from Register-Transfer Level (RTL) description to fabricable layouts. The survey categorizes and analyzes tools across major stages of design, including code-generation tools, logic synthesis, simulation, and physical design flow. Special emphasis is given to the fabricable open-source Process Design Kit (PDK), which enables the physical realization of open-hardware projects. By examining interoperability, limitations, and maturity across this toolchain, the article provides a comprehensive overview of the Electronic Design Automation (EDA) landscape and identifies the research and educational opportunities that arise from democratizing silicon design through open and reproducible workflows.

Fig: (a) IC design flow illustrating the complete process from RTL specification through logic synthesis, physical design (floorplanning, placement, clock tree synthesis, routing), verification, and final GDSII generation for fabrication. (b) FPGA design flow showing the progression from RTL description to synthesis, technology mapping, placement-and-routing on the target FPGA fabric, bitstream generation, and device configuration.

Acknowledgments: The APC was funded by Universidad Autónoma de Guadalajara (UAG), financial support provided through its Fondo Semilla. The author gratefully acknowledges the Universidad Autónoma de Guadalajara (UAG) for the financial support provided through its Fondo Semilla program, which covered the article processing charges and enabled the publication of this work. During the preparation of this manuscript, the authors utilized GPT-5.2 solely to enhance the clarity, grammar, and overall quality of the English text. The author reviewed and edited all AI-assisted content and takes full responsibility for the accuracy, originality, and integrity of the final manuscript.

Table A1. Main open-source EDA tools and their official repositories

Category	Tool	Official Link
Code-Generation Tools	PandA Bambu HLS	https://github.com/ferrandi/PandA-bambu (accessed on 20 January 2026)
	Kiwi Compiler	https://www.cl.cam.ac.uk/~djg11/kiwi/ (accessed on 20 January 2026)
	LegUp HLS	https://github.com/LegUpComputing/legup-examples?tab=readme-ov-file (accessed on 20 January 2026)
	ROCCC	http://roccc.cs.ucr.edu/ (accessed on 20 January 2026)
	PyMTL3	https://github.com/pymtl/pymtl3 (accessed on 20 January 2026)
	Chisel	https://www.chisel-lang.org/ (accessed on 20 January 2026)
	SpinalHDL	https://github.com/SpinalHDL/SpinalHDL (accessed on 20 January 2026)
	Pyverilog	https://github.com/PyHDI/Pyverilog (accessed on 20 January 2026)
	Amaranth HDL	https://github.com/amaranth-lang (accessed on 20 January 2026)
LLM-Based Code Generation	RTLCoder	https://github.com/hkust-zhiyao/RTL-Coder (accessed on 20 January 2026)
	Spec2RTL-Agent	https://cirkitly.kernex.sbs/ (accessed on 20 January 2026)
	OriGen	https://github.com/pku-liang/OriGen (accessed on 20 January 2026)
	AutoChip	https://github.com/shailja-thakur/AutoChip (accessed on 20 January 2026)
	CodeV	https://github.com/cluesmith/codev (accessed on 20 January 2026)
	VeriCoder	https://github.com/Anjiang-Wei/VeriCoder (accessed on 20 January 2026)
	StarCoder	https://github.com/bigcode-project/starcoder (accessed on 20 January 2026)
	CodeLlama	https://github.com/meta-llama/codellama (accessed on 20 January 2026)
	DeepSeek-Coder	https://github.com/deepseek-ai/DeepSeek-Coder (accessed on 20 January 2026)
	CodeQwen	https://github.com/QwenLM/qwen-code (accessed on 20 January 2026)
	Gemini	https://gemini.google.com/ (accessed on 20 January 2026)
	GPT	https://chatgpt.com/ (accessed on 20 January 2026)
	ChatEDA	https://github.com/wuhy68/ChatEDA (accessed on 20 January 2026)
Synthesis Tools	Yosys	https://yosyshq.net/yosys/ (accessed on 20 January 2026)
	ABC (Berkeley)	https://people.eecs.berkeley.edu/~alanmi/abc/ (accessed on 20 January 2026)
	ODIN II (VTR)	https://docs.verilogtorouting.org/en/latest/odin/ (accessed on 20 January 2026)
	GHDL-Yosys Plugin	https://github.com/YosysHQ/yosys (accessed on 20 January 2026)
	Synlig	https://github.com/chipsalliance/synlig (accessed on 20 January 2026)
	Mockturtle (EPFL)	https://github.com/lsils/mockturtle (accessed on 20 January 2026)
Simulation & Verification Tools	Verilator	https://www.veripool.org/verilator/ (accessed on 20 January 2026)
	Icarus Verilog	https://steveicarus.github.io/iverilog/ (accessed on 20 January 2026)
	cocotb	https://www.cocotb.org/ (accessed on 20 January 2026)
	GTKWave	https://gtkwave.sourceforge.net/ (accessed on 20 January 2026)
	Yosys-SMTBMC	https://symbiyosys.readthedocs.io/en/latest/reference.html (accessed on 20 January 2026)
	EQY	https://github.com/YosysHQ/eqy (accessed on 20 January 2026)
	CoSA	https://github.com/cristian-mattarei/CoSA (accessed on 20 January 2026)
	OpenSTA	https://github.com/The-OpenROAD-Project/OpenSTA (accessed on 20 January 2026)
	OpenTimer	https://github.com/OpenTimer/OpenTimer (accessed on 20 January 2026)
	Tatum (VTR)	https://github.com/verilog-to-routing/tatum (accessed on 20 January 2026)
Physical Design Flow Tools	OpenROAD	https://theopenroadproject.org/ (accessed on 20 January 2026)
	OpenLane	https://github.com/The-OpenROAD-Project/OpenLane (accessed on 20 January 2026)
	iEDA	https://github.com/OSCC-Project/iEDA (accessed on 20 January 2026)
	SiliconComp	https://github.com/siliconcompiler/siliconcompiler (accessed on 20 January 2026)
Fabricable PDKs	SKY130	https://github.com/gdsfactory/skywater130 (accessed on 20 January 2026)
	GF180MCU	https://github.com/google/gf180mcu-pdk (accessed on 20 January 2026)
	IHP SG13G2	https://github.com/IHP-GmbH/IHP-Open-PDK (accessed on 20 January 2026)
	ICsprout55	https://github.com/openecos-projects/icsprout55-pdk (accessed on 20 January 2026)

[DATE2026 Panel] Empowering Education through Open-Source Hardware

 #SavetheDate | On April 22, 2026, at 11:00 Norbert Wehn and Lukas Krupp from the RPTU Kaiserslautern-Landau will host a special session at the DATE Conference 2026 in Verona, Italy: “Empowering Education through Open-Source Hardware”.

The session focuses on how open design ecosystems can make chip development more accessible, from first hands-on experiences to full design flows from system level to GDSII. Topics include:

• open-source hardware in education
• hands-on chip design across the full stack
• broader access to PDKs, IP, and EDA tools

Panelists:

• Luca Benini (ETH Zürich)
• Luca Carloni (Columbia University)
• Oscar Gustafsson (Linköping University)
• Patrick Haspel, PhD (Synopsys Inc)
• Prof. Dr.-Ing. Gerhard Kahmen (IHP – Leibniz Institute for High Performance Microelectronics)
• Matt Venn (Tiny Tapeout)

Save the date and learn more about our upcoming stops and events here: 

https://lnkd.in/dgGbnJgn

26th Workshop Analog Circuits

26th Workshop Analog Circuits 

12.03.2026 and 13.03.2026

at Leibniz University Hannover

The workshop series offers a platform to present one's own ideas and discuss results with science and industry. The focus is on integrated analog and mixed-signal circuits.

The workshop will take place on 12.03.2026 and 13.03.2026 in the Royal Horse Stable of the University of Hannover.  Registration - Participation in the workshop is free of charge.

The programme will be compiled after the call for papers has been completed and is avalable online 

In the run-up to the 26th Workshop on Analog Circuits, the DE:Sign cooperation event on the topic of "Open Source Tools for Analog Design" will take place on the morning of 12.03.2026. In this event, the funded projects will present their current status on open design tools and methods for analogue design. Participants will receive an overview of the contribution of the respective projects to the development of technology open, accessible, and sustainable design chains in the sense of the DE:Sign guideline.

If you have any questions, please contact the organizers by e-mail at: analog2026@ims.uni-hannover.de

Aalto Microelectronics Fair

Aalto Microelectronics Fair

March 20, 2026, 9.00-15.30

Aalto Yliopisto, Kandidaattikeskus, H304, Otakaari 1, 02150 Espoo

Time	Session
8:30–9:00	Morning coffee
9:00–9:15	Opening Aleksi Korsman
	Keynotes
9:15–10:00	Keynote 1: “OpenPDK - Global Scholar Platform”, Wladek Grabinski, Open PDK Initiative
10:05–10:50	Keynote 2: “Open Source Design Tools in SME IC Design Companies”, Ari Paasio, Kovilta
	Research overviews
11:00–11:15	Research overview: Kari Stadius
11:15–11:30	Research overview: Prof. Marko Kosunen
11:30–11:45	Research overview: Prof. Kwantae Kim
11:45–12:45	Lunch (and posters)
12:45–13:15	Student talk: “Five years of RISC‑V processor design at Aalto”, Aleksi Korsman
13:15–13:45	Student talk: “Beyond Neural Networks: Overcoming the Symbolic Bottleneck via Approximate Logarithm Acceleration”, Lingyun Yao
	Posters
13:45–14:00	Poster intro
14:00–15:00	Posters with coffee and snacks
15:00–15:30	Feedback and closing

Should you have any questions, please email Marko Kosunen

[mos-ak] Fwd: MIXDES 2026 – Extended Paper Submission Deadline & Workshop Information

Dear Colleagues,

On behalf of the MIXDES 2026 organizing committee, we would like to inform you that the regular paper submission deadline for the MIXDES 2026 Conference has been extended to 15 March 2026. The additional time should be especially helpful for contributors who may also be interested in the full‑day IHP‑Open‑PDK workshop accompanying this year's event.

If you intend to submit a paper, please register it as soon as possible via the MIXDES Conference website (www.mixdes.org) by selecting the "Submit a paper" link. Early registration greatly assists us in initiating the reviewer assignment process. You will be able to update all paper details and upload revised versions of the manuscript until May 15th, 2026.

We are also pleased to announce the workshop "Analog IC Design Using Open Source Tools and IHP OpenPDK", which will take place on June 24th, 2026, at Poznan University of Technology. The workshop will provide practical, hands-on experience with open-source tools such as Xschem, Ngspice, and KLayout, covering core aspects of analog schematic design, simulation, layout, and process fundamentals. Due to the limited number of seats, participation is on a first-come, first-served basis. Requests for attendance should be sent to: mixdes2026@dmcs.p.lodz.pl

More information is available here: https://www.mixdes.org/Mixdes3/tekst/view/openpdk-analog

You are welcome to forward this information to colleagues who may be interested in the conference or workshop. The main conference details can be found in the Call for Papers: https://www.mixdes.org/downloads/call2026.pdf

If you have any questions, do not hesitate to contact directly:

Mariusz Orlikowski, MIXDES 2026 Conference Secretary

Important dates: 

• Paper submission deadline (extended): 15 March 2026 
• Notification of acceptance: 30 April 2026 
• Final paper versions: 15 May 2026
• IHP OpenPDK Workshop: 24 June 2026, Poznań, Poland
• MIXDES 2026 Conference: 25–27 June 2026, Poznań, Poland 

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To view this discussion visit https://groups.google.com/d/msgid/mos-ak/CALp-Rj_ZoyoJ0oE_6-ZpcToygr0frgCC37CX9Bt2Q%2BRnd3bENg%40mail.gmail.com.

[paper] Threshold Engineering in 2D FETs

Dipanjan Sen, Harikrishnan Ravichandran, Safdar Imam, Subir Ghosh, Krishnendu Mukhopadhyay, Md Yasir Bashir, Thomas S. Ie, Vlastimil Mazanek, Jan Luxa, Chen Chen, Joan M. Redwing, Zdenek Sofer, Shubham Sahay, Mercouri G. Kanatzidis and Saptarshi Das

van der Waals dielectrics for threshold engineering in two-dimensional field effect transistors

Nature Communications (2026)

DOI: 10.1038/s41467-026-69089-6

1. Engineering Science and Mechanics, Penn State University, University Park, PA 16802, USA
2. Department of Chemistry, Northwestern University, Evanston, IL 60208, USA
3. Electrical Engineering, Indian Institute of Technology, Kanpur, India
4. Department of Inorganic Chemistry, University of Chemistry and Technology Prague, CzechRepublic
5. 2DCC, Penn State University, University Park, PA 16802, USA
6. Materials Science and Engineering, Penn State University, University Park, PA 16802, USA
7. Electrical Engineering, Penn State University, University Park, PA 16802, USA

Abstract: Two-dimensional (2D) semiconductors are promising for next-generation field-effect transistors (FETs), but their integration into complementary-metal-oxide-semiconductors (CMOS) logic is hindered by improper threshold voltages (Vth), leading to excessive power consumption. While past efforts have focused on improving electrostatics and near-ideal subthreshold swing (𝑺𝑺), systematic Vth engineering in 2D FETs remains unexplored. Here, we investigate high-κ van der Waals (vdW) dielectrics including metal oxyhalides such as LaOBr, BiOBr, and BiOCl, and bimetallic thiophosphates such as LiInP2S6 (LIPS), LiInP2Se6 (LIPSe) and CuInP2S6 (CIPS) and demonstrate that bimetallic thiophosphates enable programmable and non-volatile Vth tuning in both n-type monolayer MoS₂ and p-type bilayer WSe2 FETs. Leveraging ion-mediated Vth tuning, we realize 2DCMOS inverters with nearly three orders of magnitude reduction in static power while maintaining high switching speed. Combining experiments with industry-compatible SPICE modeling, we identify an optimal Vth window that minimizes power without significant delay penalty, enabling built-in power gating and improved power–performance–area metrics without additional sleep transistors.

Fig: LiInP2S6 as a top-gate dielectric for 2D field-effect transistors (FETs). a) angled scanning electron microscope (SEM) image of dual-gated 2D FET with LiInP2S6(LIPS) as top-gate dielectric and 25 nm thick Al2O3 as the back-gate dielectric. Dual-sweep top-gate transfer characteristic of a b) WSe2 FET obtained by sweeping the VTG from -8 V to 8 V at a constant 𝑉𝐵𝐺 = -4 V and 𝑉𝐷𝑆 = 1 V, both exhibiting a counterclockwise (CCW) hysteresis.

Acknowledgements: SD acknowledges funding support from the National Science Foundation for NSF Career under grant number ECCS-2042154, NSF Fuse, under grant number ECCS-2328741, ONR under grant number N00014-24-1-2565, and ARO under grant number W911NF-23-1-0279. The MOCVDTMD films were grown in the 2D Crystal Consortium–Materials Innovation Platform (2DCC-MIP) facility which is supported by the National Science Foundation under cooperative agreement DMR-2039351. The work at Northwestern was supported in part by the National Science Foundation under award number DMR-2305731. ZS was supported by ERC-CZ program (project LL2101) from the Ministry of Education Youth and Sports (MEYS) and by the project Advanced Functional Nanorobots (reg. No. CZ.02.1.01/0.0/0.0/15_003/0000444 financed by the EFRR). JL was supported by Czech Science Foundation (GACR No. 24-11465S). VM was supported by project LUAUS23049 from Ministry of Education Youth and Sports (MEYS). SS acknowledges the Ministry of Education’s Scheme for Transformational and Advanced Research in Sciences (STARS) Project under Grant MoE-STARS/STARS-2/2023-0023, DST Indo-Korea Research Grant INT/Korea/P-66 under Grant E-47691 and the University Grant Commission, Government of India, through the Senior Research Fellowship, student ID: 200510263123

[paper] Ion-Sensitive FET Memory

Henrique Lanfredi Carvalho, Pedro Henrique Duarte, Ricardo Cardoso Rangel 

and Joao Antonio Martino

“Effect of gate capacitance ratio on ion-sensitive FET memory”

Solid-State Electronics (2026) Art. no. 109350.

doi: 10.1016/j.sse.2026.109350

* LSI/PSI/USP, University of Sao Paulo, Sao Paulo, Brazil

Abstract: This paper introduces the ISFET Memory device, which combines nonvolatile memory capabilities with the traditional ISFET functionality for pH sensing applications. The device’s performance is evaluated in both writing and erasing modes, with particular emphasis on how adjusting the gate capacitance ratio (GCR) influences the operating voltages and sensitivity. Results show that optimizing the GCR to 0.43 significantly reduces the voltages required for writing and erasing operations, while also enhancing sensitivity across a broader pH range. The device achieves maximum sensitivities of 1609 mV/pH in the writing state and 940 mV/pH in the erasing state, far exceeding the ideal ISFET sensitivity of 58.2 mV/pH. Furthermore, the device demonstrates adaptability to different pH ranges: the writing mode is better suited for pH values from 2 to 10, whereas the erasing mode is more effective for the remaining pH range.

Fig: Cross section of ISFET Memory (a) and with optimized structure (b)

Acknowledgment: The authors acknowledge CNPq, CAPES (Coordenação de Aperfeiçoamento de Pessoal de Nível Superior – Brazil - Finance Code 001) and São Paulo Research Foundation - FAPESP (under grant #2020/04867-2) for the financial support.

[+] This article is part of a special issue entitled: ‘EuroSOI-ULIS 2025’ published in Solid State Electronics.

[paper] Compact Modeling of Ferroelectric Devices

J. Lee, J. Kim, M. Kim, H. Kim, C. Ra, H. Choi, and J. Jeon,

“Asymmetry-Aware Compact Modeling of Ferroelectric Devices for Circuit-Level Simulation,”

ACS Applied Electronic Materials, Feb. 2026,

doi: 10.1021/acsaelm.5c02300

* Department of Electrical and Computer Engineering, Sungkyunkwan University (SKKU), Suwon 16419 (KR)

Abstract: This paper presents a unified compact model that comprehensively captures nonideal behaviors such as asymmetric hysteresis and minor loops of ferroelectric devices based on hafnium zirconium oxide (HfO2–ZrO2, HZO). The proposed model, based on the Preisach framework, integrates branch-dependent slopes, asymmetric coercive voltages, imprint-induced loop shifts, and low-voltage minor-loop responses into a unified analytical form. Implemented in Verilog-A, the proposed model reproduces measured polarization–voltage (P–V) characteristics of a ferroelectric capacitor (FeCAP) with higher accuracy than conventional symmetric models. Furthermore, using an identical parameter set, it consistently scales from a single device to logic, memory, and neuromorphic circuits, enabling prediction of operating characteristics and read/write margins. Owing to these capabilities, the model serves as a reliable predictive tool for circuit-level design and provides a practical pathway for process–design feedback and co-optimization.

[paper] Cryo FD SOI LNA Design

Giovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Jose Lugo, Joao Azevedo, Sebastien Sadlo, Quentin Berlingard, Mikael Casse, Philippe Galy

Using DC transistor characterization measurements for LNA design at cryogenic temperatures

(2026) researchsquare.com

DOI: 10.21203/rs.3.rs-7754596/v1

1. STMicroelectronics, Crolles (F)
2. Univ. Grenoble Alpes, CNRS, Grenoble-INP, TIMA, Grenoble (F)
3. Univ. Grenoble Alpes, CEA-Leti, Grenoble (F)
4. Univ. Grenoble Alpes, CNRS, Grenoble-INP, IMEP-LAHC, Grenoble (F)

Abstract: The design of Radio Frequency (RF) cryogenic circuits has attracted much interest in recent years due to applications such as quantum computers. Interface electronics with ultra-low levels of power consumption at temperatures as low as 4 K are required. Silicon technologies are being considered for implementation because of the possibility of large-scale qubit integration with energy-efficient readout and control interfaces. However, the design of RF cryogenic circuits is complicated because of the lack of standard design kits with the corresponding component models for their simulation at these temperatures. Alternative approaches to avoid costly design and fabrication cycles are possible, in particular the use of Look-Up-Table (LUT) based techniques that exploit characterization data of circuit components at cryogenic temperature. In this paper, we make use of this approach for the design of a RF Low Noise Amplifier (LNA) using a 28 nm FD-SOI technology that has been characterized at cryogenic temperatures1using DC measurements. Furthermore, we also experimentally demonstrate that the DC measurements used are valid to extract the transistor noise parameters used in the LUT-based analysis.

Fig: Measurement of: (a) transconductance gm, and (b) threshold voltage Vth 

for the 28nm FD-SOI technology, from 300K down to 4K.

Acknowledgements: This work was supported by the French CIFRE program and the Labex MINOS of French program ANR-10-LABX-55-01.

[paper] From RTL to Prompt Coding Chip Design

Lukas Krupp∗, Matthew Venn† and Norbert Wehn∗

From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs

arXiv:2601.13815v1 [cs.AR] 20 Jan 2026

∗RPTU University of Kaiserslautern-Landau, Kaiserslautern, Germany

†Tiny Tapeout

Abstract: This paper presents an LLM-based learning platform for chip design education, aiming to make chip design accessible to beginners without overwhelming them with technical complexity. It represents the first educational platform that assists learners holistically across both frontend and backend design. The proposed approach integrates an LLM-based chat agent into a browser-based workflow built upon the Tiny Tapeout ecosystem. The workflow guides users from an initial design idea through RTL code generation to a tapeout-ready chip. To evaluate the concept, a case study was conducted with 18 high-school students. Within a 90-minute session they developed eight functional VGA chip designs in a 130 nm technology. Despite having no prior experience in chip design, all groups successfully implemented tapeout-ready projects. The results demonstrate the feasibility and educational impact of LLM-assisted chip design, highlighting its potential to attract and inspire early learners and significantly broaden the target audience for the field.

Fig: Overview of the proposed idea-to-GDSII learning workflow integrating the LLM-based chat agent for the RTL implementation, VGA simulation tool, and GitHub-driven backend flow.

Acknowledgments: This paper was funded by the German Federal Ministry of Research, Technology and Space (BMFTR) as part of the “Chipdesign Germany” project under grant number 16ME0890.

ChipFoundry Webinar Recording: New CLI, OpenFrame & Production

ChipFoundry Webinar: New CLI, OpenFrame and Production   Please find the link to the video recording: https://youtu.be/7gIYObtXvPM   You can also find a link to the slides here.   If you have any further questions, please reach out to us at info@chipfoundry.io Cheers, The ChipFoundry Team ­ ­ ChipFoundry

[C4P] ESSERC 2026

ESSERC 2026 PAPERS SUBMISSION DEADLINE 

APRIL 3, 2026

Papers submitted for ESSERC 2026 review must clearly state:

• The purpose of the work
• How and to what extent it advances the state-of-the art
• Specific results and their impact.

Only work that has not been previously published or submitted elsewhere will be considered. Submission of a paper for review and subsequent acceptance is considered as a commitment that the work will not be publicly available prior to the conference. Measurement results or calibration against measured data is required to support the claims of the submitted paper.

ESSERC 2026 Conference Tracks 

1. Advanced Technology, Process and Materials
2. Analog, Power and RF Devices
3. Modelling and Simulation of Electron Devices
4. Analog Circuits
5. Data Converters
6. RF & mm‑Wave Circuits
7. Frequency Generation Circuits
8. Digital Circuits & Systems
9. Power Management
10. Wireless Systems
11. Wireline and Optical Circuits and Systems
12. Emerging Computing Devices and Circuits
13. Architectures and Circuits for AI and ML
14. Devices & Circuits for Sensors, Imagers and Displays

After selection of papers, the authors will be informed about the decision of the Technical Program Committee by e-mail by May 27, 2026.

At the same time, the complete program will be published on the conference website. An oral presentation will be given at the Conference for each accepted paper. No-shows will result in the exclusion of the papers from any conference related publication. The submitted final PDF files must be IEEE Xplore compliant.

Best Paper Award: Papers presented at the conference will be considered for the “Best Paper Award” and “Best Young Scientist Paper Award”. The selection will be based on the results of the paper selection process and the judgment of the conference participants. The award delivery will take place during ESSERC 2027.

For each paper independently, at least one (co-)author is required to register for the conference (one registration one paper policy). Registration fees and deadlines will be available on the conference website.

 

Open Silicon microelectronic bootcamp

Call for leaders to organize an Open Silicon microelectronic bootcamp

Bring Chip Design to Your Community!

Join the global Open Silicon movement and gain hands-on experience in chip design and fabrication. Our Q1 2026 bootcamps provide access, mentoring, and real silicon opportunities for students, educators, and innovators.

The IEEE is seeking passionate leaders from around the world to organize microelectronics design bootcamps in their local communities, under the IEEE division 1 OPEN SILICON initiative.

If you organize a bootcamp between February and May 2026, IEEE will sponsor the fabrication of three of your designs. You'll receive your fabricated chips (tape-out) mounted on a development board for testing and hands-on exploration.

Selected bootcamp leaders will be invited to an online training session with Matt Venn (Tiny Tapeout) during the last week of February.

To be considered, please provide the following information at REGISTRATION FORM

Key Dates:

• Bootcamp Leader Registration Deadline: Sunday, February 22nd, 2026
• Leader Training Session: Last week of February (TBD)
• Bootcamp Period: March–May 2026
• Tapeout Submission Deadline: March 23rd, 2026 / May 1st, 2026
• Development Board Shipping: September 2026 / November 2026

ICMC 2026: Paper Deadline Extended!

Submission Deadline Extended Submit Now IMPORTANT DATES February 16, 2026:   Extended Submission Deadline April 6, 2026:   Acceptance Notification May 10, 2026:   Final Version for Publication   This year, the  International Compact Modeling Conference (ICMC)  especially encourages submissions in the following domains: Electrostatic Discharge (ESD) modeling for protection design Reliability and aging-aware compact models and simulation techniques AI or Machine Learning for model development, parameter extraction, circuit simulation efficiency, etc. We are also seeking submissions in the following domains: Application of Device Models Device Model Development Model Enhancements and Implementations Emerging Devices   Submit Now     Conference Sponsors       Media Sponsors     Industry Sponsors

[C4P] MIXDES 2026

CALL FOR PAPERS

33rd International Conference

MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

MIXDES 2026

25 - 27 June 2026, Poznań, Poland

MIXDES Areas of Interest include:
1. Design of Integrated Circuits and Microsystems

Design methodologies. Digital and analog synthesis. Hardwaresoftware codesign. Reconfigurable hardware. Hardware description languages. Intellectual property-based design. Design reuse.

2. Thermal Issues in Microelectronics

Thermal and electro-thermal modelling, simulation methods and tools. Thermal mapping. Thermal protection circuits.

3. Analysis and Modelling of ICs and Microsystems

Simulation methods and algorithms. Behavioural modelling with VHDL-AMS and other advanced modelling languages. Microsystems modelling. Model reduction. Parameter identification.

4. Microelectronics Technology and Packaging

New microelectronic technologies. Packaging. Sensors and actuators.

5. Testing and Reliability

Design for testability and manufacturability. Measurement instruments and techniques.

6. Power Electronics

Design, manufacturing and simulation of power semiconductor devices. Hybrid and monolithic Smart Power circuits. Power integration.

7. Signal Processing

Digital and analogue filters, telecommunication circuits. Neural networks. Fuzzy logic. Low voltage and low power solutions.

8. Embedded Systems

Design, verification and applications.

9. Medical Applications

Medical and biotechnology applications. Biometrics. Thermography in medicine.10. Artificial Intelligence in Electronic SystemsAI-driven design. AI-driven signal and data processing. Edge AI.

Tutorials and Special Sessions Call for Proposals

Several tutorials/special sessions will be held prior to the conference. Authors willing to propose a tutorial at MIXDES 2026 are invited to send a proposal to the Organizing Committee. The proposal should consist of a three-page summary including tutorial title, name and affiliation of the lecturer(s), tutorial objectives and audience, topical outline and provisional schedule of the tutorial.

Enquiries:
Mariusz Orlikowski (Conference Secretary) e-mail: mixdes2026@dmcs.p.lodz.pl

Lodz University of Technology
Department of Microelectronics and Computer Science (K-22)
ul. Wólczańska 221 (building B18)

93-005 Łódź, Poland

tel.: +48 604397239
fax: +48 426360327

[chapter] Compact/SPICE Modeling

Wladek Grabinski and Daniel Tomaszewski

Compact/SPICE Modeling

In: Rudan, M., Brunetti, R., Reggiani, S. (eds) 

Springer Handbook of Semiconductor Devices

DOI 10.1007/978-3-030-79827-7_34

Abstract: The microelectronics and nano-electronics industry strongly relies on compact models to reduce a new microelectronic product development costs. The goals of this review are to highlight critical issues for the development of compact models for microelectronics and nano-electronics. In this chapter, we’ve covered the main principles of the compact device modeling. Also discussed are the possibilities of integrating compact models into circuit simulation and design tools, with an emphasis on the Verilog-A standardization, which simplify model implementation into EDA tool.