[paper] EKV-gm/ID Design Procedure

Marcello De Matteis

MATLAB-Assisted EKV-gm/ID Design Procedure for Two-Stage Miller-Compensated CMOS OTAs Starting from Closed-Loop Specifications

Journal of Low Power Electronics and Applications 16, no. 4: 53

DOI: 10.3390/jlpea16040053

Department of Physics, University of Milano Bicocca, Piazza della Scienza 3, 20126 Milano, Italy

Abstract: This paper presents a MATLAB-assisted EKV–gm/ID methodology for the systematic synthesis of fully differential two-stage Miller-compensated CMOS OTAs. A sensitivity-based analysis maps the required closed-loop gain, bandwidth, and noise into OTA-level targets. An EKV-inspired analytical model, independently calibrated for nMOS and pMOS devices, provides continuous ID/W, gm/W and gm/ID characteristics with errors below 5% in the design region. Noise-driven sizing explicitly accounts for the different carrier mobilities of the pMOS differential pair and nMOS active load. Transistor parasitic capacitances are estimated from bias-dependent Cgg–VGS characteristics, thereby capturing the reduced gate capacitance of devices operating in moderate or weak inversion. The framework automatically generates transistor dimensions, bias conditions, and Miller-compensation components. These parameters are transferred directly from MATLAB to CADENCE without simulator-assisted resizing or optimization, except for width quantization into 5 μm/300 nm fingers. In 0.18 μm CMOS implementation, MATLAB and nominal commercial CAD simulations predict, respectively, 61.80 and 59.27 dB DC gain, 430.78 and 431.52 MHz unity-gain bandwidth, 69.24° and 68.81° phase margin, 5.0 and 5.3 nV/√Hz input-referred noise at 100 MHz, and 1.426 and 1.314 mW core power. Robustness is assessed over 45 process-voltage-temperature corners, where the nominal solution remains close to the center of the evaluated performance distributions. The results confirm accurate nominal prediction and stable transistor-level behavior across PVT conditions and demonstrate that the proposed methodology accurately designs the OTA operating point, small-signal dynamics, and noise behavior, enabling transistor-level sizing directly from system-level specifications without iterative simulator-assisted optimization.

FIG.1: From Closed-Loop Specifications to a PVT-Verified OTA; MATLAB-Assisted EKV gm-ID Synthesis without Iterative Transistor Level Optimization

FIG.2: Design flow-chart for the two-stage Miller-compensated OTA.

First OpenSUSI MPW

1st OpenSUSI MPW Typeout

Junichi Okamura, Representative Director of OpenSUSI

In October 2025, OpenSUSI, in collaboration with Tokai Rika Co., Ltd., announced the disclosure of PDK information related to the company's 1μm CMOS process. Subsequently, created an environment for open source PDK in OpenSUSI's GitHub repository [1], and launched the open-source semiconductor manufacturing shuttle service "OpenSUSI-MPW" through OpenSUSI's website [1].

For this first OpenSUSI-MPW, by the application deadline on September 18, we received a total of 49 applications from companies, schools, and individuals, exceeding expectations. Users are not limited to individual designers; multiple private companies also use it as a practical tool for developing semiconductor design talent within their in-house structures. In addition, we received two applications for two slots from DX High Schools (key semiconductor schools), as well as many applications from several technical colleges and universities to utilize these slots in semiconductor design education. The manufactured chips are scheduled to be delivered to users around February 2027.

The main goal of OpenSUSI-MPW is not only to establish an open PDK and design environment, but also to provide an environment where everyone can experience manufacturing semiconductors they actually design and actually handling them as actual chips. This first session was the first achievement in which the environment was actually utilized by a diverse range of users, from high schools to companies.

[read more...]

REF:
[1] https://github.com/OpenSUSI/TR-1um
[2] https://www.opensusi.org/mpw-service
[3] YouTube Channel "Ichiken / ICHIKEN": https://www.youtube.com/c/ICHIKEN-video
[4] Recent Invited OpenSUSI Conference Presentation 

IEEE ICTA Special OpenPDK Session; October 22, 2026, Singapore

Contact Information:

General Incorporated Association OpenSUSI

Junichi Okamura (Representative Director)

[ICTA] Special OpenPDK Session

 

The EDS Distinguished Lecturer (DL) Program helps local chapters connect with internationally recognized experts, educators, and authors in the field of electron devices. Through this program, chapters can invite distinguished speakers to deliver high-quality technical lectures and share their knowledge with students, researchers, and industry professionals. The program supports IEEE EDS mission to promote its technical activities, encouraging active participation and IEEE EDS membership, and strengthening local EDS chapters around the world. By bringing leading experts directly to local communities, the DL Program helps foster professional development, knowledge exchange, networking, and greater engagement within the electron devices community.

Wladek Grabinski, IEEE EDS Distinguished Lecturer, visited Singapore recently, it was it was unique opportunity to meet local EDS chapters and the experts in the field of electron devices. 

Here with Yawei Li, Nanyang Assistant Professor at School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore. Previously, Prof. Li was a Lecturer at ETH Zürich, where he worked with Prof. Luca Benini. Prof. Li research focuses on AI efficiency, aiming to accelerate computation, reduce memory footprint, and mitigate power consumption in AI systems. His R&D group research improves AI model efficiency, maps AI models onto targeted hardware, and designs AI hardware to serve AI models for vision, language, and robotic tasks (see: https://ofsoundof.github.io/)

Prof. Yeo Kiat Seng of the Singapore University of Technology and Design (SUTD), Singapore, and Tianjin University, China, officially opened the 9th IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA 2026), held in Singapore on October 21-23, 2026. The conference provided an international IEEE forum for researchers, engineers, students, and industry professionals to present and exchange the latest developments in integrated circuit design, semiconductor technologies, and emerging applications. It also encouraged collaboration across different disciplines to address the challenges of our rapidly changing technological society. During his opening remarks, Prof. Yeo highlighted the growing importance of the OpenPDK initiative and the increasing adoption of FOSS CAD/EDA tools for integrated circuit design. He emphasized the value of these open technologies for both academic research and industrial innovation, helping to make advanced IC design more accessible to a broader community. With the personal support of Prof. Yeo and the full endorsement of the ICTA Organizing Committee, the conference program included a Special OpenPDK Session, providing a dedicated platform to discuss recent progress, challenges, and opportunities in open-source design technologies and ecosystem development. The Special Session was coordinated by local Singapore Section RL07/EP21/ED15 Joint Chapter was open to all the IEEE EDS members.

Special Session “OpenPDK - Global FOSS Scholar Platform" Program

T_1	MOS-AK and Verilog-A Standard Model and OpenPDK Practice Wladek Grabinski, IEEE EDS DL, MOS-AK (EU) IHP OpenPDK (D)
T_2	Open-Source Ecosystem Updates and Semiconductor Design Development Programs in Japan Jun-ichi Okamura, AIST Solutions, OpenSUSI (J)
T_3	Open-Source EDA Meets Industrial IC Design Ehrenfried Seebacher, ams-OSRAM AG (A)
T_4	Building an Open-Source Process Platform, Empowering VLSI Innovation and Development Da Zhang Zhejiang University/CTO, Zhejiang Chuangxin Integrated Process Platform (CN)
T_5	From Silicon to Design: Intelligent Measurement and Modeling for DTCO Yutao Ma, VP of R&D, Primarius Technologies. Ltd. (CN)
T_6	Beyond Moore, Application-Driven IC Innovation International Cooperation Opportunities at NICE Alex Gu, National Innovation Center Par Excellence (NICE) (CN)
T_7	2.5D/3D IC: AI+EDA Reshaping the System-Design-Technology Co-Optimization (STCO) Paradigm for Advanced Packaging Alex Zhao, Founder/CEO Zhuhai SiChip Technology Co., Ltd. (CN)
T_8	Modelling of semiconductor devices: the heart of innovation bridging academia and industrial applications Fujiang Lin, University of Science and Technology of China (USTC) (CN)

[MOS-AK] ESSERC W7 Workshop in Palma

Synopsys: The 23rd MOS-AK/ESSERC Compact Modeling Workshop in Palma de Mallorca brings together the international community advancing SPICE/Verilog-A modeling, OpenPDKs, and open-source IC design flows. Since 2002 ESSEDRC/ESSCIRC in Porto, MOS-AK has been the leading forum connecting technology developers, circuit designers, and FOSS CAD/EDA contributors, supporting knowledge exchange and strengthening the open semiconductor ecosystem. This year's program showcases cutting-edge developments: GaN MOS-HEMT compact models for emerging OpenPDKs, AI/ML-driven modeling workflows replacing manual tuning, cryogenic FD-SOI model libraries, fully open-source RFIC design case studies using IIC-OSIC-TOOLS, reliability insights for advanced CMOS and RF technologies, and a new OpenPDK MOSFET matching matrix IC enabling fast mismatch characterization. The workshop organizers are inviting engineers, researchers, and students who want a clear, practical view of modern device models and open simulation frameworks. It directly supports global OpenPDK adoption and aligns with European ODE4EC-AMS activities, promoting accessible, reproducible, and future-ready IC design methodologies.

9:30 - 11:00	W7 Workshop Opening
T_1	ODE4EC-AMS OpenPDK: the Status and Roadmap Wladek Grabinski IHP OpenPDK (D)
T_2	Advances in Open-Source Verilog-A Compilation and Simulatio> Arpad Buermen Uni. Ljubljana (SL)
T_3	Compact Modeling of GaN MOS-HEMTs for Open PDKs Ashkhen Yesayan EPFL (CH)
T_4	From Manual Tuning to Agentic AI: Transforming Device Modeling with AI/ML Roberto Tinti Keysight (US)
11:00 - 11:30	Coffee Break
T_5	Development of Cryogenic Model Libraries for FD-SOI Transistors Phanish Chava AdMOS (D)
T_6	Open-Source RFIC Design: Case Studies Using IIC-OSIC-TOOLS Georg Zachl JKU Linz (A)
T_7	Reliability topics for the miniaturization and qualification and OpenSilicon perspective Fernando Guarin IEEE EDS D1 (US)
P_1	[Poster] OpenPDK MOSFET Matching Matrix IC Juan Brito CEITEC (BR)
SSCS	Code-a-Chip Award Ceremony Akira Tsuchiya SSCS TC-OSE
13:00-14:00	End of the W7 Workshop and Lunch Break

The MOS-AK workshop was followed by ESSERC W2 Joint Workshop FAMES Pilot Line and SiNANO Institute reviwing the FDSOI Pilot Line Insights and Perspective. W2 was the first to present in-depth technical results obtained through the FAMES Pilot Line project on the development of FD-SOI at 10nm and 7nm nodes, combined with non-volatile memories (NVM) and 3D options, RF components and smart PMIC (Power Management Integrated Circuit), providing a pathway to deliver high-performance, low-power consumption solutions for future chips.

With the highlight talk: Next generations of FD-SOI technology for low-power and RF applications

by Thierry Poiroux (CEA-Leti, FR) and Valeriya Kilchytska (UCLouvain, BE)

IEEE EDS/SSCS/CAS MQ in Palma

IEEE EDS/SSCS/CAS Mini-Colloquium

FRIDAY 11 September

Sa Riera Building

C/ de Miquel dels Sants Oliver, 2

07122 Palma

IEEE EDS/SSCS/CAS MQ PROGRAM

9:00 - 09:05 Opening

9:05-9:15 Tribute to Prof. Michael S. Shur

9:05-9:15 Tribute to Prof. José Epifânio da Franca

​​​​9:15-10:05 Leveraging semiconductor technology for the benefit of society

Fernando Guarin (Director of IEEE Division I)

10:05-10:55 Power efficient WBG devices for the green transition

Mikael Ostling (KTH, SE)

10:55-11:25 Coffee Break

11:25-12:15 Holistic solutions to future computing - not only scaling

Francesca Iacopi (Purdue University, US)

12:15-13:05 Status of the Compact modeling and its Verilog-A standardization

Wladek Grabinski (MOS-AK, CH and IHP OpenPDK, DE)

13:05-14:25 Lunch​​

14:25-15:15 Graphene thin film technology for neural interfaces

José Antonio Garrido (ICN2, Barcelona, Spain)

15:15-16:05Energy-Efficient Analog IC Design: Exploring Solutions at De vice, Circuit and System Levels

Antonio López (Public University of Navarra, Spain)

[paper] Cryo mm-Wave Multifinger nMOSFETs

Adhi Cahyo Wijaya ,Jyh-Chyurn Guo  

Cryogenic mm-Wave Device Optimization and Modeling with Temperature and Layout Dependent Effects in Multifinger nMOSFETs and Si Substrate

Journal of the EDS, Vol. 14, 2026 935

Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu 300, Taiwan
Department of Electrical Engineering, National Yang Ming Chiao Tung University, Hsinchu 300, Taiwan

ABSTRACT: In this paper, cryogenic device optimization aimed at super-450GHz fT and fMAX and new equivalent circuit models with layout- and temperature-dependent effects (LDE and TDE) over 300K∼4K are presented. Open and short pad models incorporating TDE have been developed and verified by experimental data, showing extremely high Si substrate resistance (Rsi) at below 25K and the minimum Rsiat 77K followed by a turn around at above 77K. Interestingly, for active devices at on-state, carriers freezeout in the Si substrate at cryogenic temperature is suppressed, which motivates development of enhanced pad models for accurate deembedding and simulation of on-Si-chip devices and mm-wave circuits over 300K∼4K. For sub-40nm nMOSFETs with respectively optimized multi-finger (MF) layouts, the maximum fT and fMAX at 4K can reach up to 447GHz and 95 GHz.

FIG: (a) The full equivalent circuit model (b) physical representation for a full structure with intrinsic MOSFET model and enhanced pad model by adding Rsi0(g,d) and Csi0(g,d) for accurate simulation and deembedding at cryo-temp.

Acknowledgement: This work was supported in part by the National Science and Technology Council (NSTC) under Grant NSTC-114-2221-E-A49-206.

[paper] Logarithmic Power Detector

Patrick Fath and Harald Pretl

A 44-GHz Logarithmic Power Detector with 62 dB Dynamic Range and –56 dBm Sensitivity 

in 130-nm SiGe BiCMOS Using Open-Source EDA

IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 

Fukuoka, Japan, October 2026

 

Institute for Integrated Circuits and Quantum Computing, JKU Linz, Austria

 

Abstract: This paper presents a 44-GHz logarithmic RF power detector implemented in the open-source IHP SG13G2 130nm SiGe BiCMOS OpenPDK using exclusively open-source EDA tools. The proposed detector is based on a six-stage successive detection logarithmic video amplifier architecture with integrated square-law detectors, followed by a transimpedance amplifier and an output buffer. To achieve both low noise and high speed, two different limiting-amplifier topologies are employed within the successive detection logarithmic video amplifier, namely a low-noise differential common-emitter input stage and high-speed Cherry-Hooper stages. A tunable proportional-to-absolute-temperature constant-gm bias generator is used to reduce the temperature dependency of the amplifier gain, while duty-cycled operation is supported to lower the average power consumption. Post-layout simulations show a passband gain of 64 dB, a frequency range from 0.15 GHz to 44.7 GHz, a sensitivity of-56 dBm, and a dynamic range of 62 dB. In addition, RF stability is verified over the investigated frequency range, and the detector achieves an estimated video bandwidth of 114 MHz. The total power consumption is 95.7 mW in continuous operation and is reduced to 48.1 mW in duty-cycled operation. The active area is 0.43 mm^2, while the die size including pads is 1.4×1.2 mm^2. These results demonstrate that competitive wideband logarithmic RF power detectors extending into the mm-wave range can be realized using open-source design infrastructure.

Fig. (a) Transient response of the detector under duty-cycled operation, showing pon (dashed gray) and Vlog, out (solid blue). (b) Layout of the detector (1.4×1.2 mm^2) with the individual building blocks outlined 

[paper] Cryo 1T1R HfO2-Based RRAM

Emilio Pérez-Bosch Quesada, Alberto Mistroni, Ruolan Jia, Keerthi Dorai Swamy Reddy, Markus Fritscher, Felix Reichmann, Oliver Skibitzki, Juan Bautista Roldán, Helena Castán, Salvador Dueñas, Christian Wenger, Eduardo Pérez

Enabling Quantum-Compatible Nonvolatile Memory: Cryogenic Evaluation 

of 1T1R HfO2-Based RRAM From 300 to 1.5K

Advanced Electronic Materials 12, no. 19 (2026): e00798

DOI: 10.1002/aelm.202500798

ABSTRACT: To enable compact quantum computing systems, cryogenically compatible CMOS-based non-volatile memories are required. In this work, we investigate 1-transistor–1-resistor (1T1R) resistive random-access memory (RRAM) devices over an extended temperature range, including previously unexplored cryogenic regimes. To enhance storage density, we explore a multilevel-cell approach via multilevel programming. As temperature decreases, the low-resistance state (LRS) effective conductance increases, improving state separation but also leading to higher LRS currents and increased reset voltages required for reliable switching to the high-resistance state (HRS), resulting in incomplete filament rupture and a broader HRS distribution. Through independent characterization of the access nMOS transistor, we identify transistor temperature dependence as the dominant factor governing LRS evolution, while extraction of the intrinsic metal–insulator–metal (MIM) behavior reveals an opposite trend, with decreasing conductivity at lower temperatures. Based on these insights, we implement an optimized programming strategy for cryogenic operation by tuning the nMOS gate bias during set, reducing LRS currents, particularly in intermediate and high conductance states, while preserving state separation, narrowing the HRS distribution, and lowering reset voltages. Overall, this work establishes a robust and scalable approach for reliable 1T1R operation at cryogenic temperatures and provides a key step toward nonvolatile memory integration in quantum computing architectures.

FIG: a) Cryogenic setup used to characterize the RRAM devices under study, b) RRAM array containing a total of 32 1T1R devices individually addressable, and c) schematic description of the forming, set, and reset operations carried out during this work.

Acknowledgments: This work was financially supported by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) under Project 551916740.

[Innovation Showcase] European Reference Fab Blueprint at SEMICON Europa 2026

N. Herfurth, S. Reith, R. Scholz

From Pilot-Line Readiness to Trusted Deployment: A Cloneable Manufacturing Blueprint 

for European Semiconductor Resilience

SEMICON Europa 2026

Innovation Showcase (pre-recorded talk), Executive Forum, Hall C1

Friday, 13 November 2026, 11:15

1) IHP GmbH - Leibniz Institute for High Performance Microelectronics, Technology, Frankfurt/Oder, (D)
2) Hochschule Rhein Main, University of Applied Sciences and Arts, Wiesbaden (D)

 

The talk is presented by Anna Herfurth on behalf of the authors: Norbert Herfurth, Arnd Weber, Steffen Reith, Anna Herfurth, Rene Scholz, Wladek Grabinski and Torsten Grawunder. It is an independent concept, published through the HEP Alliance and supported by Swissbit AG and Hochschule RheinMain (RheinMain University of Applied Sciences). Version 1 (concept paper, executive summary and Q&A) is online, and Version 2 is in preparation, coming in the next weeks

Abstract: Europe’s semiconductor ecosystem faces a deployment gap. RTOs and pilot lines are essential for developing new technologies, but many security-, safety- and long-lifecycle applications require something different: stable, auditable and repeatable manufacturing capacity at mature nodes, combined with advanced packaging, test and traceability. This contribution presents the European Reference Fab concept as a non-commercial manufacturing blueprint to close that gap: a cloneable 300-mm infrastructure model for 130 nm with an optional evolution path to 65 nm, integrating front-end manufacturing, packaging, chiplet integration, test, open design enablement and auditable process and data flows.The news is not another pilot line or a single national flagship fab. The proposed Reference Fab is an industrial deployment architecture. It defines how mature process modules, open PDKs/ADKs, documented tool flows, traceability mechanisms, MPW and small-series access, and packaging/test capabilities can be combined into a governed manufacturing environment. Clone sites could be implemented as front-end lines, assembly/test hubs or combined facilities, depending on regional and sectoral needs.The concept addresses several bottlenecks in semiconductor adoption. First, it provides a trusted manufacturing route for defence, critical infrastructure, automotive, industrial, med-tech and aerospace applications that do not necessarily require leading-edge nodes but do require long-term availability, provenance and auditability. Second, it creates an industrial endpoint for RTO and pilot-line results, helping promising technologies move from readiness to deployment. Third, it lowers access barriers for SMEs, start-ups and system integrators through open design kits, harmonised design interfaces and fair MPW/small-series schemes. Fourth, it embeds smart-manufacturing principles such as MES-based traceability, inline metrology, SPC/ML-assisted control, documented audit trails and secure data flows from design through manufacturing and final test.The presentation will outline the core architecture of the Reference Fab, the rationale for the 130 nm to 65 nm pathway, the role of packaging-first system integration, and the mechanisms by which open design enablement, auditable manufacturing and workforce development can support trusted electronics, supply-chain resilience and European semiconductor competitiveness.

Biography: Dr.-Ing. Norbert Herfurth is a research group leader, programme coordinator and semiconductor technologist with more than ten years of experience at the interface of microelectronics research, collaborative R&D programmes, open-source chip design, failure analysis and semiconductor strategy. He currently leads the Diagnostics, Sensors & Emerging Modules group at IHP – Leibniz Institute for High Performance Microelectronics in Frankfurt (Oder), Germany, where he is responsible for building and managing a newly established interdisciplinary unit with activities in diagnostics, sensors, photonic and emerging module technologies.His work combines technical depth in semiconductor devices and failure analysis with strategic programme leadership. Before taking on his current group-leader role, he initiated, structured and coordinated several publicly funded collaborative R&D projects in the field of open-source microelectronics, open PDKs and trusted electronics. He has contributed to the development and positioning of Europe’s open-source chip-design ecosystem, including work around IHP’s open 130 nm PDK activities and European discussions on open-source EDA, design access and semiconductor sovereignty. Norbert Herfurth earned his doctorate in electrical engineering from Technische Universität Berlin, where his research focused on semiconductor devices and silicon-level failure analysis. During his academic work, he operated and developed advanced diagnostic and failure-analysis methods, including photon-emission microscopy, thermal and optical techniques, probing methods and cleanroom-based experimental workflows. Since 2024, he has also been a lecturer at Technische Universität Berlin for the course “Debug of Integrated Circuits on Silicon Level”, which combines IC debug, failure analysis and hands-on diagnostic methods. In addition to his technical work, he has extensive experience in consortium building, project governance and strategic technology communication. He has led or coordinated multiple BMBF-funded collaborative projects, developed R&D work programmes, managed milestone- and review-driven project structures and worked with partners from research organisations, SMEs, industry, funding bodies and public-sector stakeholders. His current activities include the development of strategic concepts for open and trustworthy semiconductor ecosystems, especially where design enablement, manufacturing access, packaging, test, traceability and trusted electronics intersect. Norbert Herfurth is one of the contributors to the European Reference Fab / Transparent Reference Fab concept, a proposed open, cloneable manufacturing blueprint for trustworthy mature-node semiconductor production in Europe. In this context, he focuses on the connection between open design enablement, auditable manufacturing, trusted electronics, chiplet-aware system integration and the transition from pilot-line readiness to industrial deployment. He is also a founding member of the VDE ITG expert group on trustworthy electronics. His professional interest lies in translating complex semiconductor technology topics into actionable strategies for research, industry and policy stakeholders. This includes open PDKs and open EDA, trusted manufacturing, semiconductor resilience, system-level integration, failure analysis, photonic and electronic diagnostics, and the role of public-interest infrastructure in strengthening Europe’s semiconductor ecosystem.

[workshop] Open Source Analog Chip Design

AT-C³ Training: Introduction to Open Source Analog Chip Design

SILICON ALPS Cluster

24-25 November 2026 

TU Graz, Campus Inffeldgasse

Inffeldgasse 33, 8010 Graz, Austria

This workshop is an excellent opportunity for engineers, researchers, and students who want to gain practical experience in open-source analog chip design and contribute to the emerging open-source semiconductor ecosystem.

About the Training

AT-C³ is launching one of its first hands-on training events, focused on a question that many electronic engineers are asking today: Can an analog integrated circuit be designed, simulated, laid out, and verified using only open-source EDA tools? During this two-day workshop, hosted by Symbiotic EDA, participants will answer this question through practical, hands-on experience. The training guides attendees through the complete analog IC design flow, from schematic capture to a verified physical layout, using modern open-source design tools.

Why Attend?

• Learn the complete open-source analog IC design workflow
• Gain hands-on experience with professional-grade EDA tools
• Explore schematic design, simulation, layout, and verification
• Network with engineers, researchers, and students interested in open-source chip design
• Discover the growing ecosystem around open-source silicon development

Registration Free of Charge

Organizer: SILICON ALPS Cluster

[paper] Cryo MOSFET Gate Capacitance

Sadık İlik, Masoud Babaie, Andrei Vladimirescu and Fabio Sebastiano

Characterization and Modeling of MOSFET Gate Capacitance Under Cryogenic Operation

IEEE Journal of the Electron Devices Society (2026)

DOI 10.1109/JEDS.2026.3745897

1 Delft University of Technology, 2628 CJ Delft (NL)

2 Qutech, 2628 CJ Delft (NL)

3 University of California at Berkeley, CA (US)

Abstract—The modeling of incomplete ionization is a key element for a reliable and scalable cryogenic transistor model. Despite the increasing interest in cryo-CMOS modeling, capacitance–voltage (CV) characteristics remain relatively unexplored, even though they are less sensitive to secondary effects, such as mobility variations, than DC measurements. While the experimental data in the literature are few and limited, a clear discrepancy is observed between model predictions and capacitance–voltage (CV) measurements. To address these limitations, this paper presents a new, accurate, and scalable capacitance model including an incomplete ionization model that predicts cryogenic behavior more accurately than existing models, along with a corresponding charge model derived from the proposed formulation. The model accurately reproduces all CV features, including the field-dependent ionization–induced flatband voltage dip, the depletion-region capacitance, the trap related threshold voltage humps, and the inversion region. Extensive CV characterizations over multiple device geometries, frequencies, AC excitation voltages, and temperatures are finally used to validate the model.

Fig: Inversion capacitance at 4.2 K for PMOS (a)–(d) and NMOS (e)–(h) devices with varying geometries. In (a), (b), (d), (e), (f), and (h), identical small-sized devices are connected in parallel to enable characterization with sufficient SNR.

[Open Hardware] CfP: FOSDEM 2027 Open Hardware and CAD/CAM Devroom

The Open Hardware and CAD/CAM "devroom" at FOSDEM 2027

is an opportunity for developers of Open Hardware projects and related software tools to gather and share their work, meet developers from other projects, network, and learn from one another.The 2027 devroom is once again being coordinated by Chris Hennes (@chennes, chennes@freecad.org) and Jo Hinchliffe (@concretedog, jo@concretedog.xyz). We carry on the tradition developed over the many years of this DevRoom's existence of a dynamic, interactive room full of interesting presentations and projects.

Call for Participation 

 We are pleased to announce the CfP for the Open Hardware and CAD/CAM devroom at FOSDEM 2027, 30 & 31 January 2027 in Brussels, Belgium. The devroom will take place on Sunday 09:00–13:00, 31 January 2027 at [ULB (Campus Solbosch)]. We hope you'll join us for a half day of talks, demos and interesting discussions on designing, modeling and testing hardware using Open Source tools. We welcome any talk proposals about the design and creation of physical objects. Topics of interest include, but are not limited to: 

- Open Hardware Projects 

* Open circuits 

* Product design 

* The business of open hardware 

- Circuit Design

* Printed circuit board design tools 

* Circuit simulation 

- 3D modeling and analysis

* Solid modeling tools

* Meshing, modeling and transforming physical representations

* Finite element analysis 

- 3D printing

* 3d slicing tools 

* Motor control 

- Machine design and integration

* Open Hardware projects

* ECAD/MCAD integration

* Thermal analysis

* Wire modeling 

- Physical Model Data storage

* Data representation and optimization

* Version control in hardware data storage

* Collaborative and team-based hardware design techniques 

Talk slots will be 20 minutes **total**, inclusive of time for questions. Presenters are encouraged to plan to speak for about 15 minutes, to ensure enough time for what is often a very lively Q&A segment. Note that this is shorter than previous years, since the 2027 edition is only a half day: talk fast! 

Important Dates 

* Submission deadline: 4 December 2026 

* Acceptance notifications: 11 December 2026 

* Final schedule announcement: 14 December 2026 

* Devroom: Sunday 31 January 2027 ## The submission process 

Please submit your proposal at the FOSDEM pretalx site before 4 Dec 2026. Select the "Open Hardware and CAD/CAM" session. Please note that the "Open Source Design" track, while a lovely group of wonderful hackers, is not the same. 

Please include the following information with your submission: 

- Abstract 

- Speaker bio 

- Link to any hardware / code /slides for the talk 

 

Fill in at least a title and abstract for the proposed talk. Keep in mind that much of the value in these meetings comes from the discussions, so please allot at least 20% of the talk time for questions and answers. 

Questions? 

If you have any questions or need guidance on any aspect of submitting, preparing or presenting, please e-mail channels at freecad.org. 

Volunteering 

If you are interested in helping the devroom run smoothly, please reach out to Chris Hennes (@chennes) or Jo Hinchliffe (@concretedog) and we'll be very happy to have your assistance! 

Recordings 

The talks will be recorded and live-streamed during FOSDEM'27. The recordings will be
published under the same licence as all FOSDEM content (CC-BY-4.0). Only presentations and
Q&A will be recorded, not informal discussions and whatever happens during breaks between
presentations. We require affirmative consent to this license. 

Please include the following statement in your submission notes: `

`` If my presentation is accepted for FOSDEM, I hereby agree to license all recordings, slides, and other associated materials under the Creative Commons Attribution Share-Alike 4.0 International License. Sincerely, <NAME> ``` 

Chris Hennes (@chennes)
The FreeCAD Project Association AISBL
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TSMC Europe OIP Ecosystem Workshop

Meet Dolphin Semiconductor at  TSMC Europe OIP Ecosystem Workshop Book a meeting! 📅 November 24, 2026 📍 Booth, Hilton Munich Airport, Germany   Come to our booth to learn how our TSMC-based, ultra-low-power, and smart IP solutions can shorten your design cycle and thus accelerate your Time-to-Market.   Book a meeting with us now to secure a dedicated slot before the show fills up. We look forward to seeing you at TSMC Open Innovation Platform Ecosystem Forum and sharing a glimpse into the future of our technology with you!

[chipfoundry] December Shuttle (CI2612)

Commitment and 50% payment due November 4. Tapeout December 7. Plus new drop-in analog IP for your design.‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­‌   ­

Hello , A quick reminder that the December 2026 chipIgnite shuttle (CI2612) is coming up fast, and the commitment deadline is now about two weeks away.   Key dates November 4, 2026: Commitment deadline (50% payment due) December 7, 2026: Tapeout submission   If you already have a reservation, now is the time to lock in your spot. If you are still deciding, get in touch and we will help you scope your design for this run. Secure Your December Spot New: Commercial IPs now available on the marketplace The commercial analog and mixed-signal blocks we previewed in August are now live on the ChipFoundry marketplace for SkyWater 130nm. You can install them with ipm and drop them straight into your December design.   Highlights include: Data converters: 12-bit SAR ADC, delta-sigma modulator ADC, 8-bit voltage/current DAC Clocking: 100 MHz system PLL, 24 MHz RC oscillator, crystal oscillator interface Power and reference: 1.8 V LDO, bandgap reference, voltage monitor, POR sequencer Signal chain: Class AB amplifier, continuous-time comparator, high-Z input buffer, analog mux, switched-capacitor filter   Each block comes with abstract views for place-and-route, and ChipFoundry substitutes the full protected layout at tapeout, so you integrate it like any other macro. Browse the IP Catalog Questions about adding an IP to your December tapeout? Just reply to this email or contact us at info@chipfoundry.io. We are here to help.   Best regards, The ChipFoundry Team ChipFoundry You've received it because you've subscribed to our newsletter. Unsubscribe

[paper] ACM3 Compact MOSFET Model

Deni Germano Alves Neto; Márcio Cherem Schneider; Manuel J. Barragan; 

Sylvain Bourdel; Carlos Galup-Montoro,

ACM3 - An Advanced Compact MOSFET Model for Analog IC Design and Simulation

in IEEE Access, DOI: 10.1109/ACCESS.2026.3742180

1.) Federal University of Santa Catarina, 88040-900 Florianópolis (BR)

2.) Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA F-38000 Grenoble (F)

Abstract: This paper presents ACM3, an advanced compact MOSFET model that extends the designoriented ACM2 formulation by introducing gate-voltage dependencies for the slope factor n, the draininduced barrier lowering (DIBL) coefficient σ, and inversion charge dependence for the specific current IS. ACM3 preserves a single-piece, charge-based description of the drain current, valid from weak to strong inversion and from the linear to the saturation regions, while relying on an efficient analytical approximation of the Lambert W -function suitable for Verilog-A implementation. A robust yet straightforward parameterextraction flow is proposed, in which all eight DC parameters (VT 0, IS0, Φ, γ, θ, σWI , σSI and ζ) are obtained directly from ID–VGB and ID–VDS curves through a differential evolution (DE) algorithm that minimizes the root-mean-square percentage error between the reference and the modeled drain current. A distinctive feature of this flow is that the reference curves may originate either from silicon measurements or from another compact model, making the extraction equally applicable to measured and simulated data. At the device level, the parameters are extracted from silicon measurements of an open-source 130 nm BiCMOS technology, yielding agreement with the measured data for both short- and long-channel transistors across all regions of operation. At the circuit level, ACM3 is validated through simulations of a common-source amplifier, a self-biased current source, and a CMOS latch in a 180 nm CMOS technology, where the ACM3 parameters are extracted from BSIM4-generated characteristics and the results are compared against the foundry BSIM4 model. Representative process, voltage, and temperature (PVT) robustness is also evaluated against BSIM4. The ACM3 model has been implemented in Verilog-A and integrated into open-source circuit simulators, via OpenVAF, enabling accurate and intuitive analog IC design within fully open design flows.

TAB: Comparison of ACM3 with representative industrial 

and design-oriented compact MOSFET models

Aknowlegements: This study was financed in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior, (BRAZIL), Conselho Nacional de Desenvolvimento Científico e Tecnológico, (BRAZIL), and TIMA laboratory, Grenoble (FRANCE).