Oct 24, 2017
Cryogenic characterization of CMOS technologies
Oct 19, 2017
#opensource Summit Europe 2017 https://t.co/c1TgRIgzVE https://t.co/RZqPRisbbS
#opensource Summit Europe 2017 https://t.co/c1TgRIgzVE http://pic.twitter.com/RZqPRisbbS
— Wladek Grabinski (@wladek60) October 18, 2017
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October 18, 2017 at 11:41PM
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Oct 17, 2017
A Compact QS Terminal Charge and Drain Current #Model for DG Junctionless Transistors and Its Circuit Validation https://t.co/hTsw5blL8f
A Compact QS Terminal Charge and Drain Current #Model for DG Junctionless Transistors and Its Circuit Validation https://t.co/hTsw5blL8f
— Wladek Grabinski (@wladek60) October 17, 2017
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October 17, 2017 at 11:26AM
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[paper] Accurate diode behavioral model with reverse recovery
- The complex robust time and area scalable Verilog-A model of diode containing reverse recovery effect has been developed.
- Due to implemented reverse recovery effect the model is useful especially for high-speed or high-voltage power devices.
- The model can be used as stand-alone 2-terminal diode or as a parasitic p-n junction of more complex lumped macro-model.
- Two methods of model parameter extraction or model validation have been demonstrated.
ABSTRACT: This paper deals with the comprehensive behavioral model of p-n junction diode containing reverse recovery effect, applicable to all standard SPICE simulators supporting Verilog-A language. The model has been successfully used in several production designs, which require its full complexity, robustness and set of tuning parameters comparable with standard compact SPICE diode model. The model is like standard compact model scalable with area and temperature and can be used as a stand-alone diode or as a part of more complex device macro-model, e.g. LDMOS, JFET, bipolar transistor. The paper briefly presents the state of the art followed by the chapter describing the model development and achieved solutions. During precise model verification some of them were found non-robust or poorly converging and replaced by more robust solutions, demonstrated in the paper. The measurement results of different technologies and different devices compared with a simulation using the new behavioral model are presented as the model validation. The comparison of model validation in time and frequency domains demonstrates that the implemented reverse recovery effect with correctly extracted parameters improves the model simulation results not only in switching from ON to OFF state, which is often published, but also its impedance/admittance frequency dependency in GHz range. Finally the model parameter extraction and the comparison with SPICE compact models containing reverse recovery effect is presented [read more...]
Oct 15, 2017
Software #model multi-level #photonic #IC designs https://t.co/24rtqqVTBH
Software #model multi-level #photonic #IC designs https://t.co/24rtqqVTBH
— Wladek Grabinski (@wladek60) October 14, 2017
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October 15, 2017 at 01:05AM
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Oct 12, 2017
5 #benefits of contributing to #opensource projects https://t.co/qKsBgkR9Uh
5 #benefits of contributing to #opensource projects https://t.co/qKsBgkR9Uh
— Wladek Grabinski (@wladek60) October 12, 2017
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October 12, 2017 at 09:30AM
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Oct 9, 2017
Intern/Student in SW Eng. for Power Management f/m
Your main tasks in this full time position min 5 months up to 12 months will be to:
- Create several functions/add-ons enhancing entry interface
- Develop a compiler to better explore new chip architectures-Integrate compiler output with existing tools
- Implement sanity checkers detecting
- Develop test scenarios and requirements for chip validation
- Contribute to the reporting and documentation for other teams and management
Oct 7, 2017
#Linux Now Has its First #OpenSource #RISC-V Processor https://t.co/cdM2NNXBoE
#Linux Now Has its First #OpenSource #RISC-V Processor https://t.co/cdM2NNXBoE
— Wladek Grabinski (@wladek60) October 7, 2017
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October 07, 2017 at 11:33PM
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Oct 5, 2017
#Apple #Opensource-d the #iOS Kernel for #ARM CPUs https://t.co/LUUYUnRSm2 https://t.co/91YMe1jKV1
#Apple #Opensource-d the #iOS Kernel for #ARM CPUs https://t.co/LUUYUnRSm2 http://pic.twitter.com/91YMe1jKV1
— Wladek Grabinski (@wladek60) October 5, 2017
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October 05, 2017 at 12:06PM
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Oct 2, 2017
[paper] A Novel Reconfigurable sub-0.25V Digital Logic Family Using the Electron-Hole Bilayer TFET
Sep 26, 2017
[mos-ak] [press note] 15th MOS-AK Workshop at ESSDERC/ESSCIRC September 11, 2017 Leuven
- 10th International MOS-AK Workshop in Silicon Valley (US) Dec. 2017
- Spring MOS-AK Workshop in Strasbourg (F) March 2018
- 3rd Sino MOS-AK Workshop in Beijing (CN) June, 2018
- 16th MOS-AK ESSDERC/ESSCIRC Workshop in Dresden (D) Sept, 2018
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Sep 19, 2017
A Large-Signal Monolayer Graphene Field-Effect Transistor Compact #Model for RF-Circuit Applications https://t.co/zoPkw74IK2
A Large-Signal Monolayer Graphene Field-Effect Transistor Compact #Model for RF-Circuit Applications https://t.co/zoPkw74IK2
— Wladek Grabinski (@wladek60) September 19, 2017
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September 19, 2017 at 03:55PM
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Conduction Mechanisms in Metal-Base Vertical Organic Transistors by DC and LF-Noise Measurements https://t.co/ZSiOLFMquC #paper
Conduction Mechanisms in Metal-Base Vertical Organic Transistors by DC and LF-Noise Measurements https://t.co/ZSiOLFMquC #paper
— Wladek Grabinski (@wladek60) September 19, 2017
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September 19, 2017 at 03:07PM
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#Modeling of #Electromechanical Sensors & Systems https://t.co/K40OGzRV4U https://t.co/rdih9lNeei https://t.co/748KTEgqk7
#Modeling of #Electromechanical Sensors & Systems https://t.co/K40OGzRV4U http://pic.twitter.com/rdih9lNeei https://t.co/748KTEgqk7
— Wladek Grabinski (@wladek60) September 19, 2017
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September 19, 2017 at 12:08PM
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#Modeling of #Electromechanical Sensors & Systems https://t.co/K40OGzRV4U https://t.co/rdih9lNeei
#Modeling of #Electromechanical Sensors & Systems https://t.co/K40OGzRV4U http://pic.twitter.com/rdih9lNeei
— Wladek Grabinski (@wladek60) September 19, 2017
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September 19, 2017 at 12:08PM
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Sep 18, 2017
[paper] Design techniques for low-voltage analog integrated circuits
Sep 15, 2017
[paper] Principles and Trends in Quantum Nano-Electronics and Nano-Magnetics for Beyond-CMOS Computing
Principle 1: Beyond-CMOS circuits require CMOS as an integral part. They will work alongside and augment CMOS computing blocks.
Principle 2: Some devices utilize collective states; this confers advantages of non-volatility or more energy efficient operation.
Principle 3: The choice for an optimal beyond-CMOS device will be determined by compatibility with an efficient and effective interconnect.
Principle 4: Low voltage devices – most direct way to low energy operation.
Principle 5: Start benchmarking with bottom up modeling of devices, build up from simple to more complicated circuits.
Principle 6: Majority gates (if easily implemented in a certain technology) enable more efficient circuits, especially for more complex computation functions.
Principle 7: Use electrical interconnects for longer propagation spans.
Principle 8: To convince the wider community, a non- volatile computing paradigm needs to be general enough to prove that it is valid for more than one architecture; while it needs to be specific enough to dispel claims that an essential aspect is missed.
Principle 9: Neuromorphic computing can be done more efficiently with beyond-CMOS circuits.
Sep 12, 2017
[book] Systematic Design of Analog CMOS Circuits
Cambridge University Press; 31 Oct 2017; 342pp
Sep 11, 2017
Current state of the art in #modeling heating effects in nanoscale devices - Books - IOPscience https://t.co/E0UlkDDJVk
Current state of the art in #modeling heating effects in nanoscale devices - Books - IOPscience https://t.co/E0UlkDDJVk
— Wladek Grabinski (@wladek60) September 11, 2017
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September 11, 2017 at 06:43PM
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Aug 31, 2017
#2D Semiconductor Process and Device Simulator #MicroTec: #modeling Development Status Update... https://t.co/OycWKSCKXj
#2D Semiconductor Process and Device Simulator #MicroTec: #modeling Development Status Update... https://t.co/OycWKSCKXj
— Wladek Grabinski (@wladek60) August 31, 2017
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August 31, 2017 at 08:08AM
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#2D Semiconductor Process and Device Simulator #MicroTec: #modeling Development Status Update… https://t.co/fZy9zm34yX
#2D Semiconductor Process and Device Simulator #MicroTec: #modeling Development Status Update https://t.co/do3ZxocZ5z http://pic.twitter.com/h11HndXXX5
— Wladek Grabinski (@wladek60) August 31, 2017
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August 31, 2017 at 08:08AM
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Aug 30, 2017
[paper] Surface Potential Equation for Low Effective Mass Channel Common Double-Gate MOSFET
Aug 29, 2017
levmar : Levenberg-Marquardt nonlinear least squares algorithms in C/C++
VALint: the NEEDS Verilog-A Checker
Aug 28, 2017
[paper] Nanoscale MOSFET Modeling
Part 1: The Simplified EKV Model for the Design of Low-Power Analog Circuits
Aug 25, 2017
Physics-Based Multi-Bias RF Large-Signal GaN HEMT #Modeling and Parameter Extraction Flow - IEEE Xplore Document... https://t.co/tT8gOLBa9k
Physics-Based Multi-Bias RF Large-Signal GaN HEMT #Modeling and Parameter Extraction Flow - IEEE Xplore Document... https://t.co/tT8gOLBa9k
— Wladek Grabinski (@wladek60) August 25, 2017
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August 25, 2017 at 11:37AM
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Physics-Based Multi-Bias RF Large-Signal GaN HEMT #Modeling and Parameter Extraction Flow - IEEE Xplore Document… https://t.co/xwC7X2oxYm
Physics-Based Multi-Bias RF Large-Signal GaN HEMT #Modeling and Parameter Extraction Flow - IEEE Xplore Document https://t.co/sds4WvM9TZ http://pic.twitter.com/EmSfD8SUZO
— Wladek Grabinski (@wladek60) August 25, 2017
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August 25, 2017 at 11:37AM
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An Analytical #Model for the Gate C–V Characteristics of UTB III—V-on-Insulator MIS Structure - IEEE Xplore... https://t.co/Fe1Fqwu5BJ
An Analytical #Model for the Gate C–V Characteristics of UTB III—V-on-Insulator MIS Structure - IEEE Xplore... https://t.co/Fe1Fqwu5BJ
— Wladek Grabinski (@wladek60) August 25, 2017
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August 25, 2017 at 11:39AM
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An Analytical #Model for the Gate C–V Characteristics of UTB III—V-on-Insulator MIS Structure - IEEE Xplore Documen… https://t.co/oeYfcvWNvI
An Analytical #Model for the Gate C–V Characteristics of UTB III—V-on-Insulator MIS Structure - IEEE Xplore Document https://t.co/W0W0Yhy0Ci http://pic.twitter.com/bWq1erxitj
— Wladek Grabinski (@wladek60) August 25, 2017
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August 25, 2017 at 11:38AM
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Aug 23, 2017
Modeling and simulation of biological systems using SPICE language
doi: 10.1371/journal.pone.0182385
GeNeDA results from the collaboration between three laboratories:
The Laboratory of Engineering Sciences, Computer Sciences and Imaging, ICube, UMR7357, CNRS / Université de Strasbourg, France (Morgan MADEC, Yves GENDRAULT, Elise ROSATI and Christophe LALLEMENT)
The Laboratory of Therapeutic Innovation, LIT, UMR 7200, CNRS / Université de Strasbourg, France (Jacques HAIECH)
The Laboratory of Computer Sciences of Paris 6, LIP6, UMR7606, CNRS / Université Pierre et Marie Curie, Paris, France (François PECHEUX)
Relared papers has been published recently
[1] M. Madec, F. Pêcheux, Y. Gendrault, E. Rosati, C. Lallement and J. Haiech, "GeNeDA: An Open-Source Workflow for Design Automation of Gene Regulatory Networks Inspired from Microelectronics", Journal of Computational Biology, June 2016. doi:10.1089/cmb.2015.0229.
[2] M. Madec et al., "Reuse of Microelectronics Software for Gene Regulatory Networks Design Automation", 1st international conference of the GDB BioSynSys, Paris (FR), Sept. 2016.
[3] M. Madec et al., "EDA inspired Open-source Framework for Synthetic Biology", IEEE 2013 BioCAS Conference, Rotterdam (NL), Nov. 2013.
Germany’s RWTH Aachen University and AMO launch joint Aachen Graphene & 2D-Materials Center
- Prof. Christoph Stampfer, RWTH Aachen University (Spokesman)
- Prof. Max Lemme, RWTH Aachen University/AMO GmbH
- Prof. Markus Morgenstern , RWTH Aachen University
- Prof. Renato Negra, RWTH Aachen University
- Dr. Daniel Neumaier, AMO GmbH
Aug 19, 2017
Performance Assessment of A Novel Vertical Dielectrically Modulated TFET-Based Biosensor - IEEE Xplore #paper https://t.co/jRvJS3MUTs
Performance Assessment of A Novel Vertical Dielectrically Modulated TFET-Based Biosensor - IEEE Xplore #paper https://t.co/jRvJS3MUTs
— Wladek Grabinski (@wladek60) August 19, 2017
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August 19, 2017 at 10:11AM
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