Nov 14, 2012
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Oct 29, 2012
[mos-ak] [2nd announcement] 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012
730 Montgomery StreetSan Francisco, CA 94111, USA
- Call for Papers - Oct. 2012
- on-line abstract submission: <http://www.mos-ak.org/sanfrancisco_2012/abstracts.php>
- Submission deadline - Nov. 15, 2012
- Final Workshop Program - Nov. 30 2012
- free on-line registration: <http://www.mos-ak.org/sanfrancisco_2012/registration.php>
- MOS-AK/GSA Workshop - Dec. 12, 2012
- Advances in semiconductor technologies and processing
- Compact Modeling (CM) of the electron devices
- Verilog-A language for CM standardization
- New CM techniques and extraction software
- CM of passive, active, sensors and actuators
- Emerging Devices, CMOS and SOI-based memory cells
- Microwave, RF device modeling, high voltage device modeling
- Nanoscale CMOS devices and circuits
- Technology R&D, DFY, DFT and IC Designs
- Foundry/Fabless Interface Strategies
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Oct 22, 2012
[mos-ak] [Call for Papers] 10th International Workshop on Compact Modeling
- Compact modeling for all kinds of devices
- Parameter extraction methodology and strategy
- Circuit simulation techniques and methods
Chair: H. J. Mattausch (Hiroshima University, Japan)Co-Chair: M. Chan (Hong Kong University of Science & Technology, H.K.)
Y. Cao (Arizona State University, USA)W. Grabinski (EPFL, Switzerland)J. He (Peking University, China)J. J. Liou (University of Central Florida, USA)T. Nakagawa (AIST, Japan)D. Navarro (Silvaco, Japan)M. Miura-Mattausch (Hiroshima University, Japan)Y. J. Park (Seoul National University, Korea)Z. Yu (Tsinghua University, China)
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Oct 5, 2012
QucsStudio 1.4.2
- some corrections in help system
- component names in noise contribution analysis with subcircuit prefix
- reduced time step warnings in transient analysis
- bugfix: differential voltages in equations
- in equations: allow suffix in node names
- bugfix: directory MinGW\mingw32\bin\ exists again
- bugfix: crash in diagram dialog if clicking on empty variable area
- new component: photodiode
- new equation function: stoa()
- bugfix: spaces allowed between function name and "("
- added InP permittivity in property list
- bugfix: correct text in C++ symbol string
- error message for wrong index in equation variables
QucsStudio can be downloaded from the QucsStudio homepage at http://www.mydarc.de/DD6UM/QucsStudio/qucsstudio.html
Contact: Mike Brinson
[mos-ak] MOS-AK/GSA Bordeaux workshop press release
MOS-AK/GSA Modeling Working Group Holds Summer Workshop in Bordeaux
Experts Share Insight on Compact Device Modeling with Emphasis on Simulation-Aware Models
http://www.gsaglobal.org/2012/10/mos-akgsa-modeling-working-group-holds-summer-workshop-in-bordeaux/
The workshop's three sessions focused on the nanowire TFET and organic TFT technologies, advanced compact modeling for analog/RF IC design application, computer-aided design (CAD), EDA simulations highlighting recent developments of Verilog-A compact models and its standardization. The 10th MOS-AK/GSA ESSDERC/ESSCIRC workshop was opened by invited researchers highlighting active women contributions to compact modeling R&D. The speakers discussed: the EKV model for LC-VCO optimization (M. H. Fino, UNL); physics-based analytical model of nanowire TFETs (E. Gnani, Uni. Bologna); analytical models for disordered and polycrystalline organic TFTs (M. Raja, Uni. Liverpool); Hall effect sensors performance assessment using 3D physical simulations (M.-A. Paun, EPFL); and physical compact model of a CBRAM cell (M. Reyboz, CEA/LETI).
Afterward invited international modeling experts presented: device modeling DC measurements challenges (F. Sischka, Agilent Technologies); surface-potential-based compact model of AlGaN/GaN HEMT power transistors (P. Martin, CEA/LETI); millimeter-wave CMOS device modeling and issues (K. Okada, TITech); measurement and modeling of CMOS devices in short millimeter wave (M. Fujishima, Hiroshima University); thermal network extraction in ultra-thin-body SOI MOSFETs (Y. S. Chauhan, UC Berkeley); compact modeling of SiC JFET power devices (M. Bucher, TUC Chania); SMASH-ACMI for integration and validation of Verilog-A compact models in a SPICE simulator (G. Depeyrot, Dolphin Integration); parametric yield-oriented IC design based on cumulative distribution function and open-source EDA tools (D. Tomaszewski, ITE); analytical calculation of surface-potential in AlGaAs/GaAs and AlGaN/GaN HEMT devices (S. Khandelwal analytical 2D model for source/drain band-to-band tunneling in silicon double-gate TFETs (M. Graef, THM) gate-level modeling for CMOS circuit simulation with ultimate FinFETs (N. Chevillon, InESS). The session oral and poster presentations are available for download at http://mos-ak.org/bordeaux/
The MOS-AK/GSA Modeling Working Group coordinates several upcoming modeling events: a winter Q4/2012 MOS-AK/GSA meeting in San Francisco, CA, USA, followed by a spring Q2/2013 MOS-AK/GSA meeting in Munich, a special compact modeling session at the MIXDES Conference in Gdynia, Poland (https://www.mixdes.org); and an autumn Q3/2013 MOS-AK/GSA workshop in Bucharest, Romania.
About MOS-AK/GSA Modeling Working Group:
In January 2009, GSA merged its efforts with MOS-AK, a well-known industry compact modeling volunteer group primarily focused in Europe, to re-activate its Modeling Working Group. Its purpose, initiatives and deliverables coincide with MOS-AK's purpose, initiatives and deliverables. The Modeling Working Group plays a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact model standardization and related tools for model development, validation/implementation and distribution.www.gsaglobal.org/working-groups/analog-mixed-signal
About GSA:
The Global Semiconductor Alliance mission is to accelerate the growth and increase the return on invested capital of the global semiconductor industry by fostering a more effective ecosystem through collaboration, integration and innovation. It addresses the challenges within the supply chain including IP, EDA/design, wafer manufacturing, test and packaging to enable industry-wide solutions. Providing a platform for meaningful global collaboration, the Alliance identifies and articulates market opportunities, encourages and supports entrepreneurship, and provides members with comprehensive and unique market intelligence. Members include companies throughout the supply chain representing 30 countries across the globe.www.gsaglobal.org
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Oct 2, 2012
[mos-ak] C4P: 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012
730 Montgomery StreetSan Francisco, CA 94111, USA
- Call for Papers - Oct. 2012
- Submission deadline - Nov. 15, 2012
- Final Workshop Program - Nov. 30 2012
- MOS-AK/GSA Workshop - Dec. 12, 2012
- Advances in semiconductor technologies and processing
- Compact Modeling (CM) of the electron devices
- Verilog-A language for CM standardization
- New CM techniques and extraction software
- CM of passive, active, sensors and actuators
- Emerging Devices, CMOS and SOI-based memory cells
- Microwave, RF device modeling, high voltage device modeling
- Nanoscale CMOS devices and circuits
- Technology R&D, DFY, DFT and IC Designs
- Foundry/Fabless Interface Strategies
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[mos-ak] MOS-AK/GSA Bordeaux workshop on-line publications
The workshop's three sessions focused on the nanowire TFET and organic TFT technologies, advanced compact modeling for analog/RF IC design application, computer-aided design (CAD), EDA simulations highlighting recent developments of Verilog-A compact models and its standardization. The 10th MOS-AK/GSA ESSDERC/ESSCIRC workshop was opened by fifth invited female researchers highlighting active women contribution to compact modeling R&D. Afterward invited international modeling experts presented their recent modeling work. The session oral and poster presentations are available for download at http://mos-ak.org/bordeaux/
- winter Q4/2012 MOS-AK/GSA meeting in San Francisco, CA (USA) <http://www.mos-ak.org/sanfrancisco_2012/>
- spring Q2/2013 MOS-AK/GSA meeting in Munich (D)
- special compact modeling session at the MIXDES Conference in Gdynia, (PL) <https://www.mixdes.org>
- autumn Q3/2013 MOS-AK/GSA workshop in Bucharest, (RO)
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Sep 13, 2012
Power & Performance: GSS Sees SOI Advantages for FinFETS
Power & Performance: GSS Sees SOI Advantages for FinFETS
Are FinFETs better on SOI? In a series of papers, high-profile blogs and subsequent media coverage, Gold Standard Simulations (aka GSS) has indicated that, yes, FinFETs should indeed be better on SOI.
To those of us not deeply involved in the research world, much of this may seem to come out of nowhere. But there’s a lot of history here, and in this blog we’ll take a look at what it’s all about, and connect a few dots.
The GSS IEDM ’11 Paper
GSS is a recent spin-off of Scotland’s University of Glasgow – but there’s nothing new to the research community about these folks. The core GSS-U.Glasgow team has been presenting important papers on device modeling at IEDM (which is one of the most prestigious of our industry’s conferences) and elsewhere for many years.At the risk of stating the obvious, accurate simulations are incredibly important. Technologists need to be able to predict what results they can expect from different possible transistor design options before selecting the most promising ones. Then they also need to provide reliable models to designers who will use them before committing chips to silicon. One of the biggest challenges is predicting variability, which as we all know is getting worse as transistors scale to ever-smaller dimensions.
At IEDM ’11 last December, GSS-U.Glasgow presented Statistical variability and reliability in nanoscale FinFETs. This covered “A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping…”. Essentially they concluded that scaling FinFETs on SOI should be no problem – and in fact the statistical variability of a 10nm FinFET on SOI would be about the same as the industry’s currently seeing in 45nm bulk CMOS.
That paper was based on work that the GSS-U.Glasgow team had done on two major European projects: the EU ENIAC MODERN project, and the EU FP7 TRAMS project. It’s perhaps worth looking a little more closely at what those projects are about – and who’s involved:
- A key objective of the MODERN (for Modeling and Design of Reliable, process variation-aware Nanoelectronic devices, circuits and systems) is to develop “effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance”. Other partners in the project include ST, Leti, NXP, Infineon, Numonyx (now Micron) and Synopsys.
- The objective of the TRAMS (for ‘Tera-scale Reliable Adaptive Memory Systems’) project is “to investigate in depth potential new design alternatives and paradigms, which will be able to provide reliable memory systems out of highly unreliable nanodevices at a reasonable cost and design effort”. Other partners in the project include Intel, imec, and UPC/BarcelonaTech.
READ MORE AT THE SOURCE
Sep 2, 2012
CMRF Workshop (at BCTM)
CMRF Workshop (at BCTM)
Wednesday October 3, 2012, in Portland, Oregon, USA
Session Chair: Colin McAndrew
1:00–1:30 PM – Advanced SiGe HBT Modeling with HICUM Level 0 (v1.3) for RF and mmW Applications
D. Celi and N. Derrier
1:30–2:00 PM – Dynamic Ageing Modeling for Reliability Simulation
B. Ardouin
2:00–2:30 PM – End-to-End Modeling for Handset Power Amplifiers – It’s Not Just Two Transistors!
P. Zampardi, Y. Yang, K. Kwok, B. Li, A. Metzger, C. Cismaru, H. Shao, W. Sun, and M. Fredriksson
2:50–3:20 PM – Practical Modeling: When Less is More
A. DiVergilio
3:20–4:20 PM – Forum: “Grand Challenges in Modeling”
Queen Marie Ballroom
Participants:
- Bertrand Ardouin (XMOD technologies)
- Adam DiVergilio (Tektronix)
- Mikhail Shirokov (Triquint Semiconductor)
- Peter Zampardi (Skyworks Solutions)
- Colin McAndrew (Moderator; Freescale)
Aug 13, 2012
CTFT 2012
- Physics of TFTs and operating principles
- Compact TFT device models for circuit simulation
- Model implementation and circuit analysis techniques
- Model parameter extraction techniques
- Applications of compact TFT models in emerging products
- Compact models for interconnects in active matrix flat panels
The workshop organizers:
Department of Engineering, University of Cambridge, Cambridge, UK
Technical School of Engineering, University Rovira i Virgili, Tarragona, Spain
Jul 24, 2012
[mos-ak] Final Program: 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012
Why- and how- to integrate Verilog-A compact models in SPICE simulators
Why- and how- to integrate Verilog-A compact models in SPICE simulators
This article presents a fast and accurate way to integrate and validate Verilog-A compact models in SPICE-like simulators. Modifications in the models' Verilog-A source code may be required prior to their conversion into low-level C language by a code generator. The most common of these modifications is discussed. The generated C code is then directly compiled in the target simulator resulting in an equivalent SPICE model. The comparison between Verilog-A and SPICE models in the same simulation environment, for simple and complex circuits, validates the procedure. Performance tests for demanding designs are carried out for both models. Results highlight the higher simulation speed and lower memory consumption of SPICE models. Copyright © 2012 John Wiley & Sons, Ltd.
Jul 9, 2012
Birthday (61) of the JUNCTION transistor
Sources vary as to when the formal announcement was actually made, July 4, 1951, or July 5, 1951.
At the time, Shockley was with Bell Labs’ solid state physics group, a unit to which he was a group head and a unit that saw much internal competition.
This new type of transistor overcame problems created by earlier point-contact transistors, developed by Bell Labs’ Joe Bardeen and Walter Brattain without Shockley but based in part on his previous work. It is said that when the patent process began for the point-contact transistor, Shockley made an effort to have his name only placed on the patent and made sure his fellow engineers knew of that effort.
Shockley has been described as having a “tremendous ego” by his co-workers. He was also known as having openly racist views.
Although Shockley is often known as “the inventor” of the transistor and despite his reported ego, he was often noted as correcting such misstatement and noting that he led the effort with others involved. Notes made during the development of the junction transistor can be viewed here.
Shockley left Bell Labs a few years after working on the junction transistor and eventually became a professor emeritus of electrical engineering at Stanford. He died on campus in 1989 at the age of 79.
For more moments in tech history, see this blog.
Jul 2, 2012
NANOTEC-Tutorial at ESSCIRC/ESSDERC in Bordeaux on 09/17/2012
Jun 21, 2012
[mos-ak] C4P: Special Issue of IEEE TED on Advanced Modeling of Power Devices and Their Applications
1. Compact modeling of power devices such as high-voltage MOSFETs, Bipolar, Thyristor and IGBT forcircuit applications from a few volts up to beyond 10kV.2. Modeling of passive elements such as Diode, Inductor, Resistor.3. Investigations on new material such as SiC and GaN and their applications.4. Circuit simulation for real applications of power devices together.5. Investigation for computation efficiency for circuit simulation
http://mc.manuscriptcentral.com/ted
Paper Submission Deadline: July 15, 2012Scheduled Publication Date: February, 2013
Mitiko Miura-Mattausch, Hiroshima University, mmm@hiroshima-u.ac.jpNarain Arora, Silterra Malaysia, narain@silterra.comEhrenfried Seebacher, Austriamicrosystems AG, ehrenfried.seebacher@austriamicrosystems.comSamar K. Saha, SuVolta, Inc., samar@ieee.org
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Jun 20, 2012
5th "Micro&Nano2012" Kokkini Hani, Heraklion, 7-10 October 2012
on Micro - Nanoelectronics, Nanotechnologies and MEMs
Aquis Arina Sand Hotel, Kokkini Hani, Heraklion
7-10 October 2012
The Scariest Graph
The Scariest Graph I've Seen Recently
But I have always pointed out that this is not what drives the semiconductor industry. It is much better to look at Moore's Law the other way around, namely that the cost of any given functionality implemented in semiconductors halves every couple of years. It is this which has meant that you can buy (or even your kid can buy) a 3D graphics console that contains graphics way beyond what would have cost you millions of dollars 20 years ago in a state of the art flight simulator.
But look at this graph:
This shows the cost for a given piece of functionality (namely a million gates) in the current process generation and looking out to 20nm and 14nm. It is flat (actually perhaps getting worse). This might not matter too much for Intel's server business since those have such high margins that they can probably live with a price that doesn't come down as much as it has done historically. And they can make real money by putting more and more onto a chip. But it is terrible for businesses like mobile computing that don't live on the bleeding edge of the maximum number of transistors on a chip. If you are not filling up your 28nm die and a 20nm die costs just the same (and is much harder to design) why bother? Just design a bigger 28nm die (there may be some power savings but even that is dubious since leakage is typically an increasing challenge).
If this graph remains the case, then Moore's Law carries on in the technical sense that you can put twice as many transistors on your chip if you can think of something clever to do with them and can find a way to keep enough of them powered on. But it means there is no longer an economic driver to move to a new process unless you have run out of space on the old one.
Since EDA mostly makes money on designs in new processes (because they need new tools which can be sold at a premium) this is bad for EDA. It actually doesn't make money on the first few designs coming through a new process because there is so much corresponding engineering to be done. But if the mainstream never moves, the cash-cow aspect of selling EDA tools to the mainstream won't happen. And just like there is no business selling "microprocessor design tools" since there are too few groups who would buy them and their needs are too different, there might never be a big enough market for "14nm design tools" to justify the investment.
So that's why this is the scariest graph in EDA.
Jun 18, 2012
[mos-ak] [2nd announcement] 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012
http://mos-ak.org/bordeaux/
Together with the Organizing Committee, Extended MOS-AK/GSA TPC Committee, and the IEEE EDS French Branch, the the technical program sponsor, we have pleasure to invite to the 10th MOS-AK/GSA Compact Modeling Workshop at the ESSDERC/ESSCIRC Conference in Bordeaux, Sept. 21, 2012.
http://www.mos-ak.org/bordeaux/registration.php
- Preannouncement - April 2012
- Call for Papers - May 2012
- Abstract submission deadline - July 2012
- On-line abstract submission (open on June 18):
- http://mos-ak.org/bordeaux/abstracts.php
- Final Workshop Program - Aug. 2012
- MOS-AK/GSA Workshop - Sept. 21, 2012 http://www.mos-ak.org/bordeaux/
- Morning Session
- Panel Discussion: "Status and Next Decade of European Compact Modeling"
- Poster Session
- Afternoon Session
Prof. Maria Helena Fino, Universidade Nova Lisboa, PProf. Lidia Lukasiak, TU Warsaw, PLProf. Androula Nassiopoulou, IMEL Demokritos, GRProf. Elena Gnani, University of Bologna, IMunira Raja. Uni. Liverpool, UKMaria-Alexandra Paun, EPFL, CHSadayuki Yoshitomi, Toshiba, JPYogesh S. Chauhan, UC Berkeley, USAPatrick Martin, Minatec, FDaniel Tomaszewski, ITE Warsaw, PL
- with regards - WG (for the MOS-AK/GSA Committee)
Special IETE issue on Compact Modeling
- A Hybrid Verilog-A and Equation-defined Subcircuit Approach to MOS Switched Current Analog Cell Simulation p. 181
Mike E Brinson, Stefan Jahn, H Nabijou - Aging Model for a 40 V Nch MOS, Based on an Innovative Approach p. 191
Filippo Alagi, Roberto Stella, Emanuele Viganó - Complex 2D Electric Field Solution in Undoped Double-gate MOSFETs p. 197
Mike Schwarz, Thomas Holtij, Alexander Kloes, BenjamÃn IñÃguez - 2D Analytical Calculation of the Parasitic Source/Drain Resistances in DG-MOSFETs Using the Conformal Mapping Technique p. 205
Thomas Holtij, Mike Schwarz, Alexander Kloes, BenjamÃn IñÃguez - RF Compact Modeling of High-voltage MOSFETs p. 214
Antonios Bazigos, François Krummenacher, Jean-Michel Sallese, Matthias Bucher, Ehrenfried Seebacher, Werner Posch, Kund Molnár, Mingchun Tang - HSPICE Model of the Physical Resistor p. 222
Petr Beták, Petr Zavrel - Enhanced Non-quasi-static Lauritzen Diode Model p. 226
Lenka Sochová, Petr Beták, Ján Plojhár - Self-heating Parameter Extraction of Power Metal-oxide-silicon Field Effect Transistor Based on Transient Drain Current Measurement p. 230
Risho Koh, Takahiro Iizuka - Extraction of Scalable Electrical Model for HV (600/800 V) MOS Transistors p. 237
Lorenzo Labate, Simona Angela Cozzi, Roberto Stella
Jun 10, 2012
450mm Impact Report Now Available For Free Download
Jun 6, 2012
[mos-ak] 2nd Training Course on Compact Modeling: Registration Open
- 2nd Training Course on Compact Modeling (June 28-29)
- 8th ICOE International Conference on Organic Electronics (June 25-27)
- 10th Graduate Student Meeting (June 21-22)
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Jun 5, 2012
10th Graduate Student Meeting on Electronic Engineering in Tarragona (Spain)
The 10th Graduate Student Meeting on Electronic Engineering will be held at the Campus of the Universitat Rovira (Tarragona, Spain) from June 22 to 23 2012. Registration is free.
So we encourage graduated students working in the topics:
- Nanoelectronics and Nanophotonics
- Micro and Nanosystems
- Power Electronics & Renewable Energy Systems
- Signal Processing and Data Mining
- Automatic Control
Registration is free!
The invited lectures and lecturers will be:
As you can see, some of the lectures are related to device modeling.
Besides, the 10th Graduate Student Meetiong will be held in conjunction with two more interesting events, which also will take place in Tarrgona:
1) The 8th International Conference on Organic Electronics (ICOE): June 25-27 2012.
2) The 2nd Training Course on Compact Modeling (TCCM), June 28-29 2012.
2nd Training Course on Compact Modeling: Registration open
The Training Course on Compact Modeling will consist of 12 of lectures addressing relevant topics in the compact modeling of advanced electron devices. These lectures will be conducted by top experts in the field. Most of the lectures will target compact modeling issues applicable to many electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.
REGISTRATION IS OPEN. It is quite cheap:
Advanced Registration (before June 16)
Students: 100 euro
Non-Students: 130 euro
COMON Members: FREE
On-Site Registration (after June 16)
Students: 150 euro
Non-Students: 180 euro
COMON Members: FREE
The Training Course on Compact Modeling is an event sponsored by the FP7 “COMON” (COmpact MOdelling Network) IAPP Project (which is coordinated by the Universitat Rovira i Virgili) in collaboration with the IEEE EDS Compact Modeling Technical Committee.
The programme of the 2nd Training Course on Compact Modeling is:
Thursday, June 28 | |
8:30 | Benjamin Iñiguez - Universitat Rovira i Virgili (Tarragona, Spain) |
Training Courses Opening Session | |
8:55 | Raphaël Clerc - Institut National Polytechnique de Grenoble (Grenoble, France) |
"Tunnel and quasi-ballistictransport modelling in nanoscale MOS devices" | |
10:05 | Jamal Deen - McMaster University (Hamilton, Ontario, Canada) |
"High frequency noise modeling" | |
11:15 | Coffee Break |
11:40 | Romain Ritzenthaler - IMEC (Leuven, Belgium) |
"3D analytical modelling techniques for Tri-Gate MOS structures" | |
12:50 | Franz Sischka - Agilent Technologies (Böblingen, Germany) |
"S-parameter and nonlinear RF modelling" | |
14:00 | Lunch |
15:15 | Frédéric Martinez - Université de Montpellier 2 (Montpellier, France) |
"Low frequency noise modeling" | |
16:25 | David Jiménez - Universitat Autònoma de Barcelona (Barcelona, Spain) |
"Quantum confinement models for nanoelectronic devices" | |
20:30 | Gala Dinner |
Friday, June 29 | |
8:45 | Giovanni Ghione - Politecnico di Torino (Torino, Italy) |
"Thermal modelling of RF and microwave devices" | |
9:55 | Colin C. McAndrew - Freescale Semiconductors (Phoenix, AZ, USA) |
"Statistical modelling techniques" | |
11:05 | Coffee Break |
11:30 | Antonio Cerdeira - CINVESTAV (Mexico D.F., Mexico) |
"Design-oriented compact modelling for Multi-Gate MOS devices" | |
12:50 | Mike Brinson - Metropolitan University of London (London, UK) |
"QucsStudio: A second generation Qucs software package for compact semiconductor devicemodel development based on interactive and compiled equation-defined modellingtechniques plus circuit simulation" | |
14:00 | Lunch |
15:15 | Thomas Gneiting - AdMOS GmbH (Frickenhausen, Germany) |
"Flicker noise measurements and characterization" | |
16:25 | Peter Lee - Elpida Memory (Japan) and vice-chair of the Compact Modeling Council |
"World-wide Model Standardization at the CMC, and DRAM Modeling Needs" | |
17:35 | Conclusions and announcements |
Besides, on June 25-27 the same group at URV will organize 8th International Conference on Organic Electronics (ICOE 2012) also in Tarragona. Participants to this Training Course will have a reduced fee for ICOE 2012.
Last but not least, the 10th Graduate Student Meeting on Electronic Engineering will be hels at URV Campus, Tarragona, from June 21 to 22. This event consist of two days of plenary talks given by invited prestigious researchers about selected topics related to electronic engineering, short talk given by last year Doctoral students presenting their last research results and a poster sessions were master and PhD students in this field presented their work. With this format, the Graduated Student Meeting has become a very useful forum for Master and PhD students as well as researchers in the field of Electronic Engineering.
Therefore, if you are interested in the three events, you can stay in Tarragona from June 22 to 29, and spoend the weekend there. The night from June 23 to 24 is the St. John's eve, which is well celebrated in Tarragona (in particular, on the beach) as well as in the rest of Catalonia.
Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (its Roman name) was one of the most important cities in the Roman Empire.
On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of TÃ rraco a World Heritage Site.
Tarragona can be easily reached from Barcelona Airport by bus and train. It is about 100 Km South from Barcelona. Besides, Reus Airport (less than 15 Km from Tarragona) receives flights from many European cities in the summer.
Tarragona can be easily reached from Barcelona Airport by bus and train. It is about 100 Km South from Barcelona. Besides, Reus Airport (less than 15 Km from Tarragona) receives flights from many European cities in the summer.
Speaking about Tarraco's climate, the famous Roman poet Virgil wrote: "The climate blends and confuses the seasons singularly, so that all the year seems an eternal spring." Thanks to its temperate climate, with an average yearly temperature of 23ºC, its clean beaches with fine and gloden sand, and its singular artistic and architectural heritage, Tarragona is one of the most important tourism hubs in Europe.
I strongly encourage all people interested in compact modeling to attend the 2nd Training Course on Compact Modeling!
May 18, 2012
Intel's FinFETs are less fin and more triangle
EE Times staff -- EDN, May 17, 2012
The ICs were 64-bit, four-core Xeon E3-1230 CPUs intended for the server market, which Chipworks (Ottawa, Ontario) said it obtained in Hong Kong, China.
The triangular section is markedly different to the idealized rectangular section that Intel had shown previously in 2011. However, it is not clear whether the non-vertical sides to the fins are a non-critical manufacturing artifact or are deliberately engineered by Intel and have a critical impact on electron mobility or yield.
Gold Standard Simulations Ltd (or GSS base in Glasgow, Scotland), a spin-off from the University of Glasgow led by Professor Ase Asenov as CEO, responded by saying on its Web site: "There is a lot of speculation about the possible advantages and disadvantages of the trapezoidal, or almost triangular, shaped 'bulk' FinFET." GSS has performed a simulation analysis of the FinFET using its statistical 3-D TCAD simulator called Garand.
Comparison of the TEM image of one of the FinFETs from Figure 6 of the Chipworks blog (linked above) with the Garand simulation domain of Gold Standard Simulations.
GSS' simulation was used to explore the dependence of threshold voltage on gate length for the trapezoidal Intel transistor and an equivalent rectangular-fin transistor. "Clearly the rectangular fin has better short channel effects. Still, the million-dollar question is if the almost-triangular shape is on-purpose design, or is this, what bulk FinFET technology can achieve in terms of the fin etching?"
The comparisons between dimensionally comparable rectangular and trapezoidal FinFETs are not markedly different but as GSS had no knowledge of doping profiles it assumed a lightly doped channel. At the same time GSS acknowledged that there is a high doping concentration stopper below the fin in the shallow trench isolation (STI) region. "Clearly FinFETs are more complicated devices in terms of understanding and visualization compared to the old bulk MOSFETs," GSS concluded.
This story was originally posted by EE Times.
May 17, 2012
[mos-ak] C4P 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012
http://mos-ak.org/bordeaux/
Together with the Organizing Committee and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the 10th MOS-AK/GSA Compact Modeling Workshop at the ESSDERC/ESSCIRC Conference in Bordeaux, Sept. 21, 2012.
The terms of participation, intending participants and authors should also note the following dates:
- Preannouncement - April 2012
- Call for Papers - May 2012
- Abstract submission deadline - June 2012
- Final Workshop Program - July 2012
- MOS-AK/GSA Workshop - Sept. 21, 2012
Email contact: <workshops@mos-ak.org>
- with regards - WG (for the MOS-AK/GSA Committee)
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May 16, 2012
[mos-ak] MOS-AK/GSA Dresden workshop on-line publications
The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, held its annual spring workshop on April 26-27, 2012 at the Design Automation Division EAS of the Fraunhofer Institute for Integrated Circuits IIS in Dresden, Germany. More than 50 international academic researchers and modeling engineers attended four sessions to hear 16 technical compact modeling talks and poster presentations. The MOS-AK/GSA Modeling Working Group organized the event supported by Joachim Haase Fraunhofer IIS/EAS in Dresden, and a complementary X-FAB clean room visit, poster session and open networking event was hosted by Alexander Petr, X-FAB in Dresden.
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May 11, 2012
Programme of the 2nd Training Course on Compact Modeling
It will be organized by the NEPHOS Group, of the Department of Electronic, Electrical and Automatic Control Engineering at the Universitat Rovira i Virgili (Tarragona)..
The General Chairman is myself, Prof. Benjamin Iñiguez.
The Training Course on Compact Modeling will consist of l2 lectures addressing relevant topics in the compact modeling of advanced electron devices. These lectures will be conducted by top experts in the field. Most of the lectures will target compact modeling issues applicable to many electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.
Attendees will get very useful information on the different aspects of advenced device modelling. This training course is therefore recommended to Master and Ph D students, as well as postdocs and early stage researchers in companies, and not necessarily doing research on modelling.
Here is the final programme of the Training Course on Compact Modeling
8:30 Training
Courses Opening Session
Benjamin Iniguez (Universitat Rovira i Virgili, Tarragona, Spain)
8:55 "Tunnel and quasi-ballistic transport modelling in
nanoscale MOS devices".
Raphaël Clerc (Institut
National Polytechnique de Grenoble, France)
11:15 Coffee break
11:40 "3D analytical modelling techniques for Tri-Gate MOS
structures"
Romain Ritzenthaler
(IMEC, Belgium)
12:50 "S-parameter and nonlinear RF modelling"
Franz Sischka (Agilent Technologies, Böblingen, Germany)
14:00 Lunch
15:15 "Low frequency noise modeling"
Frédéric Martinez (Université de Montpellier 2, France)
16:25 Quantum
confinement models for nanoelectronic devices
David Jiménez
(Universitat Autònoma de Barcelona, Spain)
20:30 Gala dinner
June 29 2012
8:45 "Thermal modelling of RF and microwave devices"
Giovanni Ghione (Politecnico di Torino, Italy)
9:55 "Statistical modelling techniques"
Colin C. McAndrew (Freescale Semiconductors, Phoenix,
AZ, USA)
11:05 Coffee break
11:30 High
frequency noise modeling
Jamal Deen (McMaster University,
Canada)
12:50 "QucsStudio: A second generation Qucs software package
for compact semiconductor device model development based on interactive and
compiled equation-defined modelling techniques plus circuit simulation"
Mike Brinson (Metropolitan University of London, UK)
14:00 Lunch
15:15 "Flicker noise measurements and characterization"
Thomas Gneiting (AdMOS GmbH, Frickenhausen, Germany)
16:25 "World-wide Model Standardization at the CMC, and DRAM
Modeling Needs"
Peter Lee (vice-chair of the Compact Modeling Council, Elpida Memory, Japan)
http://compactmodelling.eu/ The Training Course on Compact Modeling is an event sponsored by the FP7 “COMON” (COmpact MOdelling Network) IAPP Project (which is coordinated by the Universitat Rovira i Virgili) in collaboration with the IEEE EDS Compact Modeling Technical Committee.
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