MOS-AK/GSA Modeling Working Group Holds Summer Workshop in Bordeaux
Experts Share Insight on Compact Device Modeling with Emphasis on Simulation-Aware Models
The workshop's three sessions focused on the nanowire TFET and organic TFT technologies, advanced compact modeling for analog/RF IC design application, computer-aided design (CAD), EDA simulations highlighting recent developments of Verilog-A compact models and its standardization. The 10th MOS-AK/GSA ESSDERC/ESSCIRC workshop was opened by invited researchers highlighting active women contributions to compact modeling R&D. The speakers discussed: the EKV model for LC-VCO optimization (M. H. Fino, UNL); physics-based analytical model of nanowire TFETs (E. Gnani, Uni. Bologna); analytical models for disordered and polycrystalline organic TFTs (M. Raja, Uni. Liverpool); Hall effect sensors performance assessment using 3D physical simulations (M.-A. Paun, EPFL); and physical compact model of a CBRAM cell (M. Reyboz, CEA/LETI).
Afterward invited international modeling experts presented: device modeling DC measurements challenges (F. Sischka, Agilent Technologies); surface-potential-based compact model of AlGaN/GaN HEMT power transistors (P. Martin, CEA/LETI); millimeter-wave CMOS device modeling and issues (K. Okada, TITech); measurement and modeling of CMOS devices in short millimeter wave (M. Fujishima, Hiroshima University); thermal network extraction in ultra-thin-body SOI MOSFETs (Y. S. Chauhan, UC Berkeley); compact modeling of SiC JFET power devices (M. Bucher, TUC Chania); SMASH-ACMI for integration and validation of Verilog-A compact models in a SPICE simulator (G. Depeyrot, Dolphin Integration); parametric yield-oriented IC design based on cumulative distribution function and open-source EDA tools (D. Tomaszewski, ITE); analytical calculation of surface-potential in AlGaAs/GaAs and AlGaN/GaN HEMT devices (S. Khandelwal analytical 2D model for source/drain band-to-band tunneling in silicon double-gate TFETs (M. Graef, THM) gate-level modeling for CMOS circuit simulation with ultimate FinFETs (N. Chevillon, InESS). The session oral and poster presentations are available for download at http://mos-ak.org/bordeaux/
The MOS-AK/GSA Modeling Working Group coordinates several upcoming modeling events: a winter Q4/2012 MOS-AK/GSA meeting in San Francisco, CA, USA, followed by a spring Q2/2013 MOS-AK/GSA meeting in Munich, a special compact modeling session at the MIXDES Conference in Gdynia, Poland (https://www.mixdes.org); and an autumn Q3/2013 MOS-AK/GSA workshop in Bucharest, Romania.
About MOS-AK/GSA Modeling Working Group:
In January 2009, GSA merged its efforts with MOS-AK, a well-known industry compact modeling volunteer group primarily focused in Europe, to re-activate its Modeling Working Group. Its purpose, initiatives and deliverables coincide with MOS-AK's purpose, initiatives and deliverables. The Modeling Working Group plays a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact model standardization and related tools for model development, validation/implementation and distribution.www.gsaglobal.org/working-groups/analog-mixed-signal
The Global Semiconductor Alliance mission is to accelerate the growth and increase the return on invested capital of the global semiconductor industry by fostering a more effective ecosystem through collaboration, integration and innovation. It addresses the challenges within the supply chain including IP, EDA/design, wafer manufacturing, test and packaging to enable industry-wide solutions. Providing a platform for meaningful global collaboration, the Alliance identifies and articulates market opportunities, encourages and supports entrepreneurship, and provides members with comprehensive and unique market intelligence. Members include companies throughout the supply chain representing 30 countries across the globe.www.gsaglobal.org
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