Monday, June 18, 2012

Special IETE issue on Compact Modeling

Special IETE issue (May-June 2012 Volume 58; Issue 3 Page Nos. 179-242) on Compact Modeling: "Compact Modeling as a Bridge between Scaled Semiconductor Technologies and Advanced Designs of the Integrated Circuits" is available on-line with following articles:
  1. A Hybrid Verilog-A and Equation-defined Subcircuit Approach to MOS Switched Current Analog Cell Simulation p. 181
    Mike E Brinson, Stefan Jahn, H Nabijou
  2. Aging Model for a 40 V Nch MOS, Based on an Innovative Approach p. 191
    Filippo Alagi, Roberto Stella, Emanuele Viganó
  3. Complex 2D Electric Field Solution in Undoped Double-gate MOSFETs p. 197
    Mike Schwarz, Thomas Holtij, Alexander Kloes, Benjamín Iñíguez
  4. 2D Analytical Calculation of the Parasitic Source/Drain Resistances in DG-MOSFETs Using the Conformal Mapping Technique p. 205
    Thomas Holtij, Mike Schwarz, Alexander Kloes, Benjamín Iñíguez
  5. RF Compact Modeling of High-voltage MOSFETs p. 214
    Antonios Bazigos, François Krummenacher, Jean-Michel Sallese, Matthias Bucher, Ehrenfried Seebacher, Werner Posch, Kund Molnár, Mingchun Tang
  6. HSPICE Model of the Physical Resistor p. 222
    Petr Beták, Petr Zavrel
  7. Enhanced Non-quasi-static Lauritzen Diode Model p. 226
    Lenka Sochová, Petr Beták, Ján Plojhár
  8. Self-heating Parameter Extraction of Power Metal-oxide-silicon Field Effect Transistor Based on Transient Drain Current Measurement p. 230
    Risho Koh, Takahiro Iizuka
  9. Extraction of Scalable Electrical Model for HV (600/800 V) MOS Transistors p. 237
    Lorenzo Labate, Simona Angela Cozzi, Roberto Stella

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