Blog dedicated to the world of compact/SPICE modeling and its Verilog-A standardization. We are discussing the most recent developments and also a bit of history. Obviously, all comments are welcome.
Monday, 2 July 2012
NANOTEC-Tutorial at ESSCIRC/ESSDERC in Bordeaux on 09/17/2012
The NANO-TEC project will held a half day tutorial at the ESSDERC/ESSCIRC Conference in Bordeaux on Monday, September 17, 2012. This Tutorial will be on the ECOSYSTEMS TECHNOLOGY and DESIGN for NANOELECTRONICS in Europe and will present the current outcome of the EU project NANOTEC [read more...]