Golden List of Reviewers for 2020
Dec 2, 2020
Dec 1, 2020
[paper] THz characterization and modeling of SiGe HBTs
Sebastien Fregonese, Marina Deng, IEEE member, Marco Cabbia, Chandan Yadav*, IEEE member, Magali De Matos, and Thomas Zimmer, Senior Member, IEEE
THz characterization and modeling of SiGe HBTs
review (invited)
IEEE J-EDS, 2020, pp.1-1
DOI:10.1109/JEDS.2020.3036135
hal-03014869
IMS Laboratory, University of Bordeaux (F)
*Department of Electronics and Communication Engineering, National Institute of Technology Calicut (IN)
Abstract: This paper presents a state-of-art review of on-wafer S-parameter characterization of THz silicon transistors for compact modelling purpose. After, a brief review of calibration/deembedding techniques, the paper focuses on the on-wafer calibration techniques and especially on the design and dimensions of lines built on advanced silicon technologies. Other information such as the pad geometry, the ground plane and the floorplan of the devices under test are also compared. The influence of RF probe geometry on the coupling with the substrate and adjacent structures is also considered to evaluate the accuracy of the measurement, especially using EM simulation methodology. Finally, the importance of measuring above 110 GHz is demonstrated for SiGe HBT parameter extraction. The validation of the compact model is confirmed thanks to an EM-spice cosimulation that integrates the whole calibration cum deembedding procedure.
Fig: EM probe models based on Picoprobe GGB (a) 1 GHz -110 GHz, (b) WR5, (c) WR3 and d) WR2.2. In all models, white=coaxial insulator, gray=solder, yellow=metal.
A complete description of probe topology and technology is given in:
A. Rumiantsev et R. Doerner; RF Probe Technology: History and Selected Topics; IEEE Microw. Mag., vol. 14, no 7, p. 46‑58, Nov. 2013, DOI: 10.1109/MMM.2013.2280241
Aknowledgement: This work is partly funded by the French Nouvelle-Aquitaine Authorities through the FAST project. The authors also acknowledge financial support from the EU under Project Taranto (No. 737454). The authors would like to thank STM for supplying the silicon wafer.
Nov 30, 2020
[paper] SPICE-level Crossbar-array Circuit Simulator
Fan Zhang1 and Miao Hu2
CCCS: Customized SPICE-level Crossbar-array Circuit Simulator
for In-Memory Computing
IEEE/ACM International Conference on Computer-Aided Design
(ICCAD ’20) November 2– 5, 2020, Virtual Event, USA.
ACM, New York, NY, USA, 8 pages.
DOI: 10.1145/3400302.3415627
1Arizona State University Tempe, Arizona2Binghamton University Binghamton, New York
ABSTRACT: Resistive crossbar arrays are known for their unique structure to implement analog in-memory vector-matrix-multiplications (VMM). However, general-purpose circuit simulators, such as HSPICE and HSIM, are too slow for large scale crossbar array simulations with consideration of circuit parasitics. Although there are some specific simulators designed for crossbar arrays, they mainly focus on area/power/delay estimation rather than accurate SPICE-level simulation, thus could not model its functionality on analog in-memory computing. In this paper, we firstly give a SPICE-level modeling of resistive crossbar array with consideration of circuit parasitics in MATLAB. We also propose efficient methods to further speedup simulations by model simplifications. Last but not least, ResNet-20 on CIFAR-10 is applied to demonstrate the work. With the proposed model simplification methods, simulation speed can be improved by ~31X with tolerable errors, and more than 5X speedup is achieved on ResNet-20 while the accuracy drop is 6%.
Figure: Implement the ResNet on the crossbar with sub-block optimization.
RELATED WORK: Other than general-purpose circuit simulators, specific simulation platforms have been proposed for crossbar-based application analysis; examples include:
[MNSIM] L. Xia, B. Li, T. Tang, P. Gu, X. Yin, W. Huangfu, P. Chen, S. Yu, Y. Cao, Y. Wang, Y. Xie, and H. Yang. MNSIM: Simulation platform for memristor-based neuromorphic computing system. In 2016 Design, Automation Test in Europe Conference Exhibition (DATE). 469–474.
[NeuroSim] P. Chen, X. Peng, and S. Yu. 2018. NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, 12 (Dec 2018), 3067–3080.
#Urban Explorers Reveal A #Treasure Trove Of #Soviet #Computing Power
#Urban Explorers Reveal A #Treasure Trove Of #Soviet #Computing Power https://t.co/5dLGxTSMRF#semi
— Wladek Grabinski (@wladek60) November 30, 2020
from Twitter https://twitter.com/wladek60
November 30, 2020 at 07:55PM
via IFTTT
[paper] The advantages of p-GaN channel/Al2O3 gate insulator
Maria Ruzzarin,1, Carlo De Santi,1 Feng Yu,2 Muhammad Fahlesa Fatahilah,2 Klaas Strempel,2 Hutomo Suryo Wasisto,2 Andreas Waag,2 Gaudenzio Meneghesso,1 Enrico Zanoni,1
and Matteo Meneghini1
Highly stable threshold voltage in GaN nanowire FETs: The advantages of p-GaN channel/Al2O3 gate insulator
Appl. Phys. Lett. 117, 203501 (2020);
DOI: 10.1063/5.0027922
Published Online: 16 November 2020
1 Department of Information Engineering, University of Padova, via Gradenigo 6/b, 35131 Padova, Italy
2 Institute of Semiconductor Technology (IHT) and Laboratory for Emerging Nanometrology (LENA), Technische Universitat Braunschweig, Langer Kamp 6a/b, 38106 Braunschweig, Germany
Abstract: We present an extensive investigation of the charge-trapping processes in vertical GaN nanowire FETs with a gate-all-around structure. Two sets of devices were investigated: Gen1 samples have unipolar (n-type) epitaxy, whereas Gen2 samples have a p-doped channel and an n-p-n gate stack. From experimental results, we demonstrate the superior performance of the transistor structure with a p-GaN channel/Al2O3 gate insulator in terms of dc performance. In addition, we demonstrate that Gen2 devices have highly stable threshold voltage, thus representing ideal devices for power electronic applications. Insight into the trapping processes in the two generations of devices was obtained by modeling the threshold voltage variations via differential rate equations.
Fig. a) The p-channel device (Gen2) comprises a 2.5 lm n-GaN buffer layer, a 0.5 lm p-GaN channel layer, 0.73 lm n-GaN and 0.5 lm n p-GaN as the top layer, and 25 nm-Al2O3 as the gate dielectric.
b) SEM images of a nanowire of the p-channel device (Gen2) and bird’s-eye view of vertically aligned n-p-n GaN nanowire (NW) arrays with top contacts.
Aknowledgement: This work was supported in part by NoveGaN (Univ. of Padova) through the STARS CoG Grants call. Ack prog. Eccellenza. This research was partly performed within project INTERNET OF THINGS: SVILUPPI METODOLOGICI, TECNOLOGICI E APPLICATIVI and co-funded (2018–2022) by the Italian Ministry of Education, Universities and Research (MIUR) under the aegis of the “Fondo per il finanziamento dei dipartimenti universitari di eccellenza” initiative (Law 232/2016). Financial support from the German Research Foundation (DFG) of 3D GaN project and the Lower Saxony Ministry of Science and Culture (N-MWK) of LENA-OptoSense group is highly acknowledged for the development of vertical GaN nanowire FETs.
Nov 29, 2020
#top10 Hottest Semiconductor #Startups Of #2020
#top10 Hottest Semiconductor #Startups Of #2020 https://t.co/wIJrk3NU6b #semi
— Wladek Grabinski (@wladek60) November 29, 2020
from Twitter https://twitter.com/wladek60
November 29, 2020 at 08:50PM
via IFTTT
Nov 28, 2020
[paper] How Objective is Peer Review?
By Hannah Bast
November 18, 2020
In 2014, the organizers of the Conference on Neural Information Processing Systems (NeurIPS, then still called NIPS) made an interesting experiment.1 They split their program committee (PC) in two and let each half independently review a bit more than half of the submissions. That way, 10% of all submissions (166 papers) were reviewed by two independent PCs. The aimed at acceptance rate per PC was 23%. The result of the experiment was that among these 166 papers, the set of accepted papers from the two PCs overlapped by only 43%. That is, more than half of the papers accepted by one PC were rejected by the other. This led to a passionate flare-up of the old debate of how effective or random peer-reviewing really is and what we should do about it. [read more...]
My bottom line: The reputation of the peer review process is tarnished. Let us work on this with the same love and attention we give to our favorite research problems. Let us do more experiments to gain insights that help us make the process more fair and regain some trust. And let us create powerful incentives, so that whatever we already know is good is actually implemented and carried over from one PC to the next.
References:
1 https://cacm.acm.org/blogs/blog-cacm/181996-the-nips-experiment provides a short description of the NIPS experiment and various links to further analyses and discussions.
2 https://github.com/ad-freiburg/esa2018-experiment
3 There are other experiments, like the single-blind vs. double-blind experiment at WSDM'17, which investigated a particular aspect of the reviewing process: https://arxiv.org/abs/1702.00502
Nov 27, 2020
#Brazilian Senate approves #tax exemption for #IoT devices
#Brazilian Senate approves #tax exemption for #IoT devices | ZDNet https://t.co/TYKRem4tcR#semi
— Wladek Grabinski (@wladek60) November 27, 2020
from Twitter https://twitter.com/wladek60
November 27, 2020 at 05:40PM
via IFTTT
£20m for Turing Fellowships
£20m for Turing Fellowships:
New Turing #AI Acceleration #Fellowships will give fifteen of the UK’s top AI innovators the resources to drive forward research from speeding up medical diagnosis to increasing workplace productivity. https://t.co/9nIjr67rwE#semi pic.twitter.com/9opCVAFWGi
— Wladek Grabinski (@wladek60) November 27, 2020
from Twitter https://twitter.com/wladek60
November 27, 2020 at 03:26PM
via IFTTT
[paper] Trillion-transistor chip breaks speed record
Kamil Rocki∗, Dirk Van Essendelft†, Ilya Sharapov∗, Robert Schreiber∗, Michael Morrison∗, Vladimir Kibardin∗, Andrey Portnoy∗, Jean Francois Dietiker†‡, Madhava Syamlal†
and Michael James∗
Fast Stencil-Code Computation on a Wafer-Scale Processor
Online SC20 Supercomputing Conference
arXiv:2010.03660 [cs.DC] (2020)
∗ Cerebras Systems Inc., Los Altos, California, USA
† National Energy Technology Laboratory, Morgantown, West Virginia, USA
‡ Leidos Research Support Team, Pittsburgh, Pennsylvania, USA
Abstract: The performance of CPU-based and GPUbased systems is often low for PDE codes, where large, sparse, and often structured systems of linear equations must be solved. Iterative solvers are limited by data movement, both between caches and memory and between nodes. Here we describe the solution of such systems of equations on the Cerebras Systems CS-1, a wafer-scale processor that has the memory bandwidth and communication latency to perform well. We achieve 0.86 PFLOPS on a single wafer-scale system for the solution by BiCGStab of a linear system arising from a 7-point finite difference stencil on a 600 × 595 × 1536 mesh, achieving about one third of the machine’s peak performance. We explain the system, its architecture and programming, and its performance on this problem and related problems. We discuss issues of memory capacity and floating point precision. We outline plans to extend this work towards full applications.
Fig: CS-1 Wafer Scale Engine (WSE). A single wafer (rightmost) contains one CS-1 processor. Each processor is a collection of dies arranged in a 2D fashion (middle). Dies are then further subdivided into a grid of tiles. One die hosts thousands of computational cores, memory and routers (leftmost). There is no logical discontinuity between adjacent dies and there is no additional bandwidth penalty for crossing the die-die barrier. In total, there are 1.2 trillion transistors in an area of 462.25 cm2.
Acknowledgement: The authors would like to thank Natalia Vassilieva for initiating the collaboration between Cerebras Systems and NETL and for her subsequent help with the project.
Nov 26, 2020
[book] MEMS Fundamentals
MEMS Fundamentals
with ANSYS simulation of basic sensors and actuators
Michał Szermer, Andrzej Napieralski (Eds.)
ISBN eBook: 978-83-66287-64-8, 9788366287648
Wydawnictwo Politechniki Łódzkiej
Intro: The purpose of this book is to help universities and individuals extend their traditional microelectronics education into the MEMS area. It is organized in a set of tutorials primarily aimed at electronic engineering students and practicing engineers. Based on carefully selected examples of sensors and actuators, it introduces the reader to device operating principles, modeling approaches, simulation tools and design methodologies.
Book Contents
PrefaceChapter 1. INTRODUCTION
1.1. Program description
1.2. References
Chapter 2. SILICON MEMBRANE
2.1. Introduction
2.2. Modeling
2.2.1. Getting started
2.2.2. Setting system of units
2.2.3. Selecting finite element types
2.2.4. Setting material properties
2.2.5. Defining geometry
2.2.6. Meshing
2.2.7. Selecting analysis type
2.2.8. Applying boundary conditions
2.2.9. Running analysis
2.2.10. Viewing simulation results
2.3. Tasks for students
2.4. References
Chapter 3. THERMAL ACTUATOR
3.1. Introduction
3.2. Modeling
3.2.1. Getting started
3.2.2. Defining geometry
3.2.3. Setting material properties
3.2.4. Setting finite element types
3.2.5. Meshing
3.2.6. Selecting analysis type
3.2.7. Applying boundary conditions
3.2.8. Running analysis
3.2.9. Viewing simulation results
3.3. Automation of MEMS thermal actuator design
3.3.1. Simulation of thermal actuator with varying heater temperature
3.3.2. Viewing and saving simulation results using POST1 postprocessor
3.3.3. Plotting relationships
3.3.4. Tasks for students
3.4. References
Chapter 4. ELECTROTHERMAL ACTUATOR
4.1. Introduction
4.2. Modeling
4.2.1. Getting started
4.2.2. Defining geometry
4.2.3. Setting finite element types
4.2.4. Setting material properties
4.2.5. Meshing
4.2.6. Applying boundary conditions
4.2.6.1. Clamp
4.2.6.2. Temperature
4.2.6.3. Voltage
4.2.7. Selecting analysis type
4.2.8. Running analysis
4.2.9. Viewing simulation results
4.2.9.1. Displacement
4.2.9.2. Voltage
4.2.9.3. Temperature
4.3. Tasks for students
4.4. References
Chapter 5. ACCELEROMETER
5.1. Introduction
5.2. Modeling
5.2.1. Getting started
5.2.2. Defining geometry
5.2.3. Setting finite element types
5.2.4. Setting material properties
5.2.5. Meshing
5.2.6. Applying boundary conditions
5.2.7. Selecting analysis type
5.2.8. Running analysis
5.2.9. Viewing simulation results
5.3. Tasks for students
5.4. References
Chapter 6. SILICON MEMBRANE IN WORKBENCH
6.1. Membranes
6.2. Membrane modeling
6.3. Design and modeling of the membrane
6.3.1. Introduction to ANSYS
6.3.2. Getting started
6.3.3. Defining geometry
6.3.4. Setting up the simulation
6.3.5. Results processing
6.4. Exercises for Students
6.4.1. Laboratory tasks
6.4.2. Individual tasks
6.5. References
Chapter 7. MICROBOLOMETER IN WORKBENCH
7.1. Microbolometer principle
7.2. Microbolometer design with ANSYS Workbench
7.2.1. Getting started
7.2.2. Defining geometry
7.2.3. Adding materials’ data to the project
7.2.4. Electrical simulation
7.2.5. Thermal simulation
7.2.6. Exercises for students
7.2.7. Transient thermal simulation
7.2.8. Exercises for students
7.3. References
Nov 25, 2020
[GUEST EDITORIAL] Women in Circuits
GUEST EDITORIAL
Zeynep Toprak-Deniz
Women in Circuits
IEEE SOLID-STATE CIRCUITS MAGAZINE FALL 2020
DOI 10.1109/MSSC.2020.3021864 (18 November 2020)
The “Rising to the Top in Industry” career panel touched upon topics including mentoring, setting career goals, filing patents, and management versus technical tracks.
At the 2020 International Solid-State Circuits Conference (ISSCC), the Women in Circuits (WiC) Committee hosted the first-ever Rising Stars workshop for graduate and undergraduate students as well as young professionals who have graduated within the last two years and are interested in learning how to excel in academic and industry careers in computer science and electrical engineering. Twenty individuals were selected to attend a special dinner featuring a keynote speech by Prof. Anantha P. Chandrakasan - already a risen star - and a mentoring session with committee members. The event also included two panels. The “Rising to the Top in Industry” career panel touched upon topics including mentoring, setting career goals, filing patents, and management versus technical tracks. The “Navigating the Assistant Professorship” panel addressed topics related to applying for a faculty position, tenure review, and managing day-to-day life in academia. The panels were open to all ISSCC 2020 attendees and the public and attracted more than 300 participants. This Fall 2020 issue of IEEE SolidState Circuits Magazine on WiC follows the tradition of previous issues since 2017, enabling more exposure to female leaders through exposition of their work in circuits on a variety of important topics. The following IEEE Solid-State Circuits Society members were asked to contribute tutorials for this issue:
- Jane Gu, associate professor at the University of California, Davis, and member of the Technical Program Committee (TPC) for the IEEE Radio Frequency Integrated Circuits Symposium, Custom Integrated Circuits Conference (CICC), and ISSCC, is an associate editor of IEEE Microwave and Wireless Components Letters and VLSI Journal of Integration and guest editor of IEEE Journal of Solid-State Circuits (JSSC).
- Ulkuhan Guler, assistant professor at Worcester Polytechnic Institute, is a senior member of JSSC and serves on the CICC TPC.
- Alicia Klinefelter, senior research scientist in the ASIC and VLSI research group at NVIDIA, has served on the ISSCC TPC since 2018.
- Yan Li, vice president for memory design at Western Digital, leading the design of advanced 3D NAND as well as other nonvolatile memories and new innovation initiatives, serves on the ISSCC Machine Learning TPC.
- Rabia Yazicigil, assistant professor in the Department of Electrical and Computer Engineering at Boston University and visiting scholar at the Massachusetts Institute of Technology, was vice-chair of the 2020 Rising Stars workshop.
- Maneesha Yellepeddi, manager of the Programmable Solutions Group at Intel, is an alumnus of the 2020 Rising Stars workshop.
ISSCC 2021 will continue this tradition by hosting another Sunday evening workshop bringing together experts in cloud-connected biosensors, advance algorithms, and artificial intelligence to discuss our preparedness for combating the spread of infectious diseases now and in the future. The “ICs in PandemICs” panel will feature recent work on remote patient monitoring and data analysis with related security and privacy concerns. I hope to see you all there!
Fwd: Online Skill Enhancement Program for SCIENCE Students to be held during December 02 - 08, 2020 from 05:00 pm - 06:30 pm daily.
On behalf of the DBT Star College Program and Department of Electronics
We invite all FIRST AND SECOND Year science students of your institution to join
the Online Skill Enhancement Program
to be held during
December 02 - 08, 2020 from 05:00 pm - 06:30 pm daily
Kindly register via Zoom Link No Registration Fees:
https://us02web.zoom.us/webinar/register/WN_gug93-ABQr-IoAGdW_juoQ
The objective of the program is to make the students first feel comfortable in their new environment, open them up, create bonding and to connect, learn new things about sensors, mechanics, control, programming the microcontroller to see how it works and controls various aspects be they of biology, zoology, chemistry, physics, mathematics or computers. So this workshop will be useful for all science students to help them explore their knowledge in their fields as well as other fields. Today there is a need to take the concepts of various fields together. This is to skill them in the basic concepts of programming the robotic and control aspects of various applications and sensitize them towards exploring their academic interest and activities.
This program will provide an opportunity for all the science stream students to get some experience in the new way and enhance their knowledge towards interdisciplinary learning. All students having a passion to learn and explore a new world of automation and control and start experimenting with robotic applications are most welcome to participate.
Organizing Committee
Dr. Poonam Kasturi
The objective of the program is to make the students first feel comfortable in their new environment, open them up, create bonding and to connect, learn new things about sensors, mechanics, control, programming the microcontroller to see how it works and controls various aspects be they of biology, zoology, chemistry, physics, mathematics or computers. So this workshop will be useful for all science students to help them explore their knowledge in their fields as well as other fields. Today there is a need to take the concepts of various fields together. This is to skill them in the basic concepts of programming the robotic and control aspects of various applications and sensitize them towards exploring their academic interest and activities.
This program will provide an opportunity for all the science stream students to get some experience in the new way and enhance their knowledge towards interdisciplinary learning. All students having a passion to learn and explore a new world of automation and control and start experimenting with robotic applications are most welcome to participate.
Kindly register via Zoom Link: https://us02web.zoom.us/webinar/register/WN_gug93-ABQr-IoAGdW_juoQ
Organizing Committee
Dr. Poonam Kasturi
Convener-DBT Star College Program (Electronics)Teacher-in-Charge, Department of ElectronicsDeen Dayal Upadhyaya CollegeUniversity of Delhi
Dr. Manoj Saxena | डॉ मनोज सक्सेना
Program Coordinator - DBT Star College Program (DDUC)Associate Professor | सह - आचार्यDepartment of Electronics | इलेक्ट्रॉनिक्स विभागDeen Dayal Upadhyaya College | दीन दयाल उपाध्याय कॉलेजUniversity of Delhi | दिल्ली विश्वविद्यालयDwarka Sector-3, New Delhi-110078 | द्वारका क्षेत्र -३, नई दिल्ली -११००७८India | भारत
Nov 24, 2020
[paper] Compact Models for Sizing Based on ANN
Husni Habal, Dobroslav Tsonev, Matthias Schweikardt
Compact Models for Initial MOSFET Sizing Based on Higher-order Artificial Neural Networks
ACM/IEEE Workshop on Machine Learning for CAD (MLCAD ’20)
Nov. 16–20, 2020, Virtual Event, Iceland. ACM, pp. 111-116
DOI: 10.1145/3380446.3430632
1Infineon Technologies AG Munich, Germany
2LogiqWorks Ltd. Sofia, Bulgaria
3Reutlingen University Reutlingen, Germany
2LogiqWorks Ltd. Sofia, Bulgaria
3Reutlingen University Reutlingen, Germany
Abstract: Simple MOSFET models intended for hand analysis are inaccurate in deep sub-micrometer process technologies and in the moderate inversion region of device operation. Accurate models, such as BSIM6 model, are too complex for use in hand analysis and are intended for circuit simulators. Artificial neural networks (ANNs) are efficient at capturing both linear and non-linear multivariate relationships. In this work, a straightforward modeling technique is presented using ANNs to replace the BSIM model equations. Existing open-source libraries are used to quickly build models with error rates generally below 3%. When combined with a novel approach, such as the gm/Id systematic design method, the presented models are sufficiently accurate for use in the initial sizing of analog circuit components without simulation.
Figure: ANN Model Architecture.
Nov 23, 2020
[paper] Noise Modeling of Gate Leakage Current in Nanoscale MOSFETs
Jonghwan Lee*
Noise Modeling of Gate Leakage Current in Nanoscale MOSFETs
Journal of the Semiconductor & Display Technology,
Vol. 19, No. 3. September 2020
*Department of System Semiconductor Engineering, Sangmyung University
Abstract: The physics-based compact gate leakage current noise models in nanoscale MOSFETs are developed in such a way that the models incorporate important physical effects and are suitable for circuit simulators, including QM (quantummechanical) effects. An emphasis on the trap-related parameters of noise models is laid to make the models adaptable to the variations in different process technologies and to make its parameters easily extractable from measured data. With the help of an accurate and generally applicable compact noise models, the compact noise models are successfully implemented into BSIM (Berkeley Short-channel IGFET Model) format. It is shown that the noise models have good agreement with measurements over the frequency, gate-source and drain-source bias ranges.
Fig: Implementation of the gate leakage current and noise
models into the BSIM model
Input deck to simulate MOSFET Noise*m1 2 1 0 0 mod1 L=10u W=10u*vgs 1 0 dc 1.4 ac 1vds 3 0 dc 0.3rdd 2 3 1*.include model.TI_nmos.op.dc vgs 1 5 0.5.print dc igd(vgs)*.ac dec 10 1 100Meq.noise v(2) vgs dec 10 1 100Meg 1.plot noise onoisa inoise*.end
[conference] SISPAD 2020 Technical Program
1st group; (from 9:00 am on Sep. 23 to 11:59 pm on Sep. 28, JST)
Opening and Welcome Remarks Yoshinari Kamakura; (Osaka Inst. Tech., Japan)
Session 1: Plenary Chairperson: Tatsuya Kunikiyo; (Renesas, Japan)
[1-1] Invited Talk "Forefront of Silicon Quantum Computing"; Kohei M. Itoh; (Keio Univ., Japan) pp.1
[1-2] Invited Talk "Ab-initio quantum transport with a basis of unit-cell restricted Bloch functions and the NEGF formalism"; Marco Pala; (CNRS, Univ. Paris-Sud, France) pp.3
[1-3] Invited Talk "Future of Power Electronics from TCAD Perspective"; Terry Ma; (Synopsys, U.S.A.) pp.7
Session 2: Band Structure Chairperson: Chioko Kaneta; (Tohoku Univ., Japan)
[2-1] Invited Talk "Computics Approach toward Clarification of Atomic Reactions during Epitaxial Growth of GaN"; Atsushi Oshiyama; (Nagoya Univ., Japan) pp.11
[2-2] "Estimation of Phonon Mean Free Path in Small-Scaled Si Wire by Monte Carlo Simulation"; Y. Suzuki1, Y. Fujita1, K. Fauziah2, T. Nogita2 H. Ikeda2, T. Watanabe3, Y. Kamakura1; (1 Osaka Inst. Tech., 2 Shizuoka Univ., 3 Waseda Univ., Japan) pp.15
[2-3] "First-principles study of dopant trap level and concentration in Si(110)/a-SiO2 interface"; G.Kang, J. Jeon, J. Kim, H. Ahn, I. Jang, D. Kim; (Samsung Electronics, Korea) pp.19
[2-4] "Energy Band Calculation of Si/Si0.7Ge0.3 Nanopillars in k Space"; M-H Chuang, Y. Li; (National Chiao Tung Univ., Taiwan) pp.23
[2-5] "Full Band Monte Carlo simulation of phonon transfer at interfaces"; N. D. Le1, B. Davier1,2, P. Dollfus1, M. Pala1, A. Bournel1, J. Saint-Martin1; (1 Universite Paris-Saclay, CNRS, France, 2 Univ. Tokyo, Japan) pp.27
[2-6] "First Principle Simulations of Electronic and Optical Properties of a Hydrogen Terminated Diamond Doped by a Molybdenum Oxide Molecule"; J.McGhee, V. P. Georgiev; (Univ. Glasgow, U.K.) pp.31
Session 3: Computational Methodology Chairpersons: Yiming Li; (National Chao Tung Univ., Taiwan)Victor Moroz; (Synopsys, U.S.A.)
[3-1] "High-sigma analysis of DRAM write and retention performance: a TCAD-to-SPICE approach"; S. M. Amoroso1, J. Lee1, A. R. Brown1, P. Asenov1, X. W. Lin2, T. Yang3, V. Moroz2; (1 Synopsys Europe, U.K., 2 Synopsys, U.S.A., 3 Synopsys Taiwan, Taiwan) pp.35
[3-2] "Generative Model Based Adaptive Importance Sampling for Flux Calculations in Process TCAD"; A. Scharinger1, P. Manstetten1, A. Hossinger2, J. Weinbub1; (1 TU Wien, Austria, 2 Silvaco Europe, U.K.) pp.39
[3-3] "Implant heating contribution to amorphous layer: a KMC approach"; P. L. Julliard1,2, P. Dumas1, F. Monsieur1, F. Hilario1, D. Rideau1, A. Hemeryck2, F.Cristiano2; (1 STMicroelectronics, France, 2 LAAS-CNRS, Univ. Toulouse, France) pp.43
[3-4] "Automatic Modeling of Logic Device Performance Based on Machine Learning Utilizing Feature Engineering"; S. Kim, K. Lee, Y. Shin, K. Chang, J. Jeong, S. Baek, M. Kang, K. Cho, D. Kim; (Samsung Electronics, Korea) pp.47
[3-5] "Gummel-cycle Algebraic Multigrid Preconditioning for Large-scale Device Simulations"; H. Koshimoto1, H. Ishimabuchi2, J. Yoo2, Y. Kayama1, S. Yamada1, U. Kwon2, D. S. Kim2; (1 Samsung R&D Inst. Japan, Japan, 2 Samsung Electronics, Korea) pp.51
[3-6] "A continuous cellular automaton method with flux interpolation for two-dimensional electron gas electron transport analysis"; K.Fukuda1, J. Hattori1, H. Asai1, J. Yaita2, J. Kotani2; (1 AIST, Japan, 2 Fujitsu, Japan) pp.55
[3-7] "Geometric Advection Algorithm for Process Emulation"; X.Klemenschits, S. Selberherr, L. Filipovic; (TU Wien, Austria) pp.59
Session 4: Nanowire Chairperson: Susanna Reggiani; (Univ. Bologna, Italy)
[4-1] "Performance and Leakage Analysis of Si and Ge NWFETs Using a Combined Subband BTE and WKB Approach"; Z. Stanojevic, K. Steiner, G. Strof, O. Baumgartner, G. Rzepa, M. Karner; (Global TCAD Solutions, Austria) pp.63
[4-2] "Molecular Dynamics Modeling of the Radial Heat Transfer from Silicon Nanowires"; I. Bejenari1, A. Burenkov1, P. Pichler1, I. Deretzis2, A. La Magna2; (1 Fraunhofer IISB, Germany, 2 CNR-IMM, Italy) pp.67
[4-3] "Advanced simulations on laser annealing: explosive crystallization and phonon transport corrections"; A. Sciuto1,2, I. Deretzis1, S. F. Lombardo1, M. G. Grimaldi2, K. Huet3, B. Curvers3, B. Lespinasse3, A. Verstraete3, I. Bejenari4, A. Burenkov4, P. Pichler4, A. La Magna1; (1 CNR-IMM, Italy, 2 Univ. Catania, Italy, 3 LASSE laser systems and solutions of Europe, France, 4 Fraunhofer IISB, Germany) pp.71
[4-4] "Effect of Unit-Cell Arrangement on performance of Multi-Stage-planar Cavity-free Unileg Thermoelectric Generator Using Silicon Nanowires"; K. Abe1, K. Oda1, M. Tomita1, T. Matsukawa2, T. Matsuki1,2, T. Watanabe1; (1 Waseda Univ., Japan, 2 AIST, Japan) pp.75
[4-5] "Characteristics of Gate-All-Around Silicon Nanowire and Nanosheet MOSFETs with Various Spacers"; S. R. Kola, Y. Li, N. Thoti; (National Chiao Tung Univ., Taiwan) pp.79
Session 5: Material and Geometry Impact Chairpersons: Jun’ichi Hattori; (AIST, Japan)William Vandenberghe; (Univ. Texas at Dallas, U.S.A.)
[5-1] Invited Talk "On the Physical Mechanism of Negative Capacitance Effect in Ferroelectric FET"; Masaharu Kobayashi; (Univ. Tokyo, Japan) pp.83
[5-2] "Undoped SiGe material calibration for numerical laser annealing simulations"; A-S. Royet1, L. Dagault1,2, S. Kerdiles1, P. Acosta-Alba1, J. P. Barnes1, F. Cristiano2, H. Huet3; (1 Univ. Grenoble Alpes, France, 2 LAAS, CNRS Univ. Toulouse, France, 3 Laser Systems & Solutions of Europe, France) pp.89
[5-3] "TCAD simulation for transition metal dichalcogenide channel Tunnel FETs consistent with ab-initio based NEGF calculation"; H. Asai1, T. Kuroda2, K. Fukuda1, J. Hattori1, T. Ikegami1, N. Mori2; (1 AIST, Japan, 2 Osaka Univ., Japan) pp.93
[5-4] "Ab Initio Study of Magnetically Intercalated Tungsten Diselenide"; P. D. Reyntjens1,2,3, S. Tiwari1,2,3, M. L. Van de Put1, B. Sor´ee2,3,4, W. G. Vandenberghe1; (1 Univ. Texas at Dallas, U.S.A., 2 Imec, Belgium, 3 KU Leuven, Belgium, 4 Univ. Antwerp, Belgium) pp.97
[5-5] "A Study of Wiggling AA modeling and Its Impact on Device Performance in Advanced DRAM"; Q.Wang, Y. D. Chen, J. Huang, W. Liu, E. Joseph; (Lam Research, China) pp.101
[5-6] "Reactive Force-Field Molecular Dynamics Study of the Silicon-Germanium Deposition Processes by Plasma Enhanced Chemical Vapor Deposition"; N. Uene1, T. Mabuchi1, M. Zaitsu2, S. Yasuhara2, T. Tokumasu1; (1 Tohoku Univ., Japan, 2 Japan Advanced Chemicals, Japan) pp.105
2nd group; (from 9:00 am on Sep. 28 to 11:59 pm on Oct. 3, JST)
Session 6: Reliability Chairpersons: Markus Karner; (Global TCAD Solutions, Austria)Hajime Tanaka; (Kyoto Univ., Japan)[6-1] "Universal Feature of Trap-Density Increase in Aged MOSFET and Its Compact Modeling"; F. Avila Herrera1, M. Miura-Mattausch1, T. Iizuka1, H. Kikuchihara1, H. J. Mattausch1, H.Takatsuka2; (1 Hiroshima Univ., Japan, 2 USJC, Japan) pp.109
[6-2] "TCAD Incorporation of Physical Framework to Model N and P BTI in MOSFETs"; R. Tiwari, N. Chowdhury, T. Samadder, S. Mukhopadhyay, N. Parihar, S. Mahapatra; (Indian Inst. Tech., India) pp.113
[6-3] "Benchmarking Charge Trapping Models with NBTI, TDDS and RTN Experiments"; S.Bhagdikar, S. Mahapatra; (Indian Inst. Tech., India) pp.117
[6-4] "A TCAD Framework for Assessing NBTI Impact Under Drain Bias and Self-Heating Effects in Replacement Metal Gate; (RMG)p-FinFETs"; U.Sharma, S. Mahapatra; (Indian Inst. Tech., India) pp.121
[6-5] "Model analysis for effects of spatial and energy profiles of plasma process-induced defects in Si substrate on MOS device performance"; T.Hamano, K. Urabe, K. Eriguchi; (Kyoto Univ., Japan) pp.125
Session 7: Power and Optoelectronic Devices Chairpersons: Blanka Magyari-Kope; (TSMC at U.S.A., U.S.A.)Hideki Minari; (Sony Semiconductor Solutions, Japan)
[7-1] Invited Talk "Modeling and Simulation of Si IGBTs"; Naoyuki Shigyo; (Tokyo Inst. Tech., Japan) pp.129
[7-2] "Full Band Monte Carlo simulations of GaAs p-i-n Avalanche PhotoDiodes: What are the Limits of Nonlocal Impact Ionization Models?"; A. Pilotto1, F. Driussi1, D. Esseni1, L. Selmi2, M. Antonelli3, F. Arfelli3,4, G. Biasiol5, S. Carrato3, G. Cautero6,4, D. De Angelis6, R. H. Menk6,4, C. Nichetti6,3, T. Steinhartova5, P. Palestri1; (1 Univ. Udine, Italy, 2 Univ. Modena and Reggio Emilia, Italy, 3 Univ. Trieste, Italy, 4 INFN, Italy, 5 IOM CNR, Italy, 6 Elettra-Sincrotrone, Italy) pp.131
[7-3] "A technique for phase-detection auto focus under near-infrared-ray incidence in a back-side illuminated CMOS image sensor pixel with selectively grown germanium on silicon"; T. Kunikiyo, H. Sato, T. Kamino, K. Iizuka, K. Sonoda, T. Yamashita; (Renesas Electronics, Japan) pp.137
[7-4] "Investigation of the relationship between current filament movement and local heat generation in IGBTs by using modified avalanche model of TCAD"; T.Suwa; (Toshiba Electronic Devices & Storage, Japan) pp.141
[7-5] "Verilog-A model for avalanche dynamics and quenching in Single-Photon Avalanche Diodes"; Y. Oussaiti1,2, D. Rideau1, J. R. Manouvrier1, V. Quenette1, H. Wehbe-Alause1, B. Mamdy1, A. Lopez1, G. Mugny1, M. Agnew1, E. Lacombe1, J. Grebot1, P. Dollfus2, M. Pala2; (1 STMicroelectronics, France, 2 Centre de Nanosciences et de Nanotechnologies, France) pp.145
[7-6] "A Novel Full-Band Monte Carlo Device Simulator with Real-Space Treatment of the Short-Range Coulomb Interactions for Modeling 4H-SiC Power Devices"; C-Y. Cheng, D. Vasileska; (Arizona State Univ., U.S.A.) pp.149
[7-7] "Tight-binding simulation of optical gain in h-BCN for laser application"; D.Maki, M. Ogawa, S. Souma; (Kobe Univ., Japan) pp.153
[7-8] "Predictive Compact Modeling of Abnormal LDMOS Characteristics Due to Overlap Length Modification"; T. Iizuka1, D. Navarro1, M. Miura-Mattausch1, H. Kikuchihara1, H. J. Mattausch1, D.R. Nestor2; (1 Hiroshima Univ., Japan, 2 Allegro MicroSystems, U.S.A.) pp.157
Session 8: Non-Volatile Memory I Flash and Phase Change Memory Chairperson: Kentaro Kukita; (Kioxia, Japan)
[8-1] "A TCAD Study on Mechanism and Countermeasure for Program Characteristics Degradation of 3D Semicircular Charge Trap Flash Memory"; N. Kariya, M. Tsuda, T. Kurusu, M. Kondo, K. Nishitani, H. Tokuhira, J. Shimokawa, Y. Yokota, H. Tanimoto, S. Onoue, Y. Shimada, T. Kato, K. Hosotani, F. Arai, M. Fujiwara, Y.Uchiyama, K. Ohuchi; (Kioxia, Japan) pp.161
[8-2] "Impact of Random Phase Distribution in 3D Vertical NAND Architecture of Ferroelectric Transistors on In-Memory Computing"; G.Choe, W. Shim, J. Hur, A. I. Khan, S. Yu; (Georgia Inst. Tech., U.S.A.) pp.165
[8-3] "TCAD Modeling and Optimization of 28nm HKMG ESF3 Flash Memory"; A. Zaka, T. Herrmann, R. Richter, S. Duenkel, R. Jain; (GLOBALFOUNDRIES, Germany) pp.69
[8-4] "Coupling the Multi Phase-Field Method with an Electro-Thermal Solver to Simulate Phase Change Mechanisms in Ge-rich GST based PCM"; R. Bayle1,2,3, O. Cueto1, S. Blonkowski1, T. Philippe3, H. Henry3, M. Plappa3; (1 CEA-LETI, France, 2 STMicroelectronics, France, 3 Ecole Polytechnique, France) pp.173
Session 9: Transport Chairperson: Christoph Jungemann; (Univ. Aachen, Germany)
[9-1] "Efficient partitioning of surface Green’s function: toward ab initio contact resistance study"; G. Gandus1,2, Y. Lee2, D. Passerone1, M. Luisier2; (1 nanotech@surfaces; (EMPA), Switzerland, 2 Integrated Systems Laboratory; (ETH Zurich), Switzerland) pp.177
[9-2] "Quantum transport in Si: P δ-layer wires"; J. P. Mendez, D. Mamaluy, X. Gao, L. Tracy, E. Anderson, D. Campbell, J. Ivie, T.-M. Lu, S.Schmucker, S. Misra; (Sandia National Laboratories, U.S.A.) pp.181
[9-3] "Analytical Formulae for the Surface Green’s Functions of Graphene and 1T’ MoS2 Nanoribbons"; H.Kosina, V. Sverdlov; (TU Wien, Austria) pp.185
[9-4] "Numerical Solution of the Constrained Wigner Equation"; R.Kosik, J. Cervenka, H. Kosina; (TU Wien, Austria) pp.189
[9-5] "Calibrated Si Mobility and Incomplete Ionization Models with Field Dependent Ionization Energy for Cryogenic Simulations"; H. Y. Wong; (San Jose State Univ., U.S.A.) pp.193
Session 10: Non-Volatile Memory II ReRAM and MRAM Chairperson: Uihui Kwon; (Samsung, Korea)
[10-1] "Monte Carlo Simulation of a Three-Terminal RRAM with Applications to Neuromorphic Computing"; A.Balasingam, A. Levy, H. Li, P. Raina; (Stanford Univ., U.S.A.) pp.197
[10-2] "Fully Analog ReRAM Neuromorphic Circuit Optimization using DTCO Simulation Framework"; A. Nguyen1, H. Nguyen1, S. Venimadhavan1, A. Venkattraman2, D. Parent1, H. Y. Wong1; (1 San Jose State Univ., U.S.A., 2 Univ. California Merced, U.S.A.) pp.201
[10-3] "Effect of Shape Deformation due to Edge Roughness in Spin-Orbit Torque Magnetoresistive Random-Access Memory"; Byun, D. H. Kang, M. Shin; (KAIST, Korea) #205
[10-4] "Computation of Torques in Magnetic Tunnel Junctions through Spin and Charge Transport Modeling"; S. Fiorentini1, J. Ender1, M. Mohamedou1, R. Orio1, S. Selberherr1, W. Goes2, V. Sverdlov1; (1 TU Wien, Austria, 2 Silvaco Europe, U.K.) pp.209
[10-5] "Efficient Demagnetizing Field Calculation for Disconnected Complex Geometries in STT-MRAM Cells"; J. Ender1, M. Mohamedou1, S. Fiorentini1, R. Orio1, S. Selberherr1, W. Goes2, V. Sverdlov1; (1 TU Wien, Austria, 2 Silvaco Europe, U.K.) pp.213
[10-6] "Properties of Conductive Oxygen Vacancies and Compact Modeling of IV Characteristics in HfO2 Resistive Random-Access-Memories"; J.Park, M.-J. Kim, J.-H. Jang, S.-M. Hong; (Gwangju Inst. Sci. Tech., Korea) pp.217
Session 11: High Speed Switching Devices Chairpersons: Akira Hiroki; (Kyoto Inst. Tech., Japan)Sebastien Martinie; (CEA-LETI, France)
[11-1] "MOS-like approach for compact modeling of HEMT transistor"; A. Vaysset, S. Martinie, F. Triozon, O. Rozeau, M.-A. Jaud, R. Escoffier, T. Poiroux; (CEA, LETI, Univ. Grenoble Alpes, France) pp.221
[11-2] "Compact modeling of gate leakage phenomenon in GaN HEMTs"; K. Li1,3, E. Yagyu2, H. Saito2, K. H. Teo1; (1 Mitsubishi Electric Research Labs, U.S.A., 2 Mitsubishi Electric Corp., Japan, 3 Univ. Illinois at Urbana-Champaign, U.S.A.) pp.225
[11-3] "Effect of Atomic Interface on Tunnel Barrier in Ferroelectric HfO2 Tunnel Junctions"; J.Seo, M. Shin; (KAIST, Korea) pp.229
[11-4] "Surge Current Capability in lateral AlGaN/GaN Hybrid Anode Diodes with p-GaN/Schottky Anode"; G. Atmaca1, M.-A. Jaud1, J. Buckley1, R. Gwoziecki1, A. Yvon2, E. Collard2, M. Plissonnier1, T.Poiroux1; (1 CEA, LETI, Univ. Grenoble Alpes, France, 2 STMicroelectronics, France) pp.233
[11-5] "Dynamic Simulation of Write ‘1’ Operation in the Bi-stable 1-Transistor SRAM Cell"; T. Dutta1, F. Adamu-Lema1, A. Asenov1, Y. Widjaja2, V. Nebesnyi3; (1 Semiwise, U.K., 2 Zeno Semiconductor, 3 MCPG) pp.237
[11-6] "Simulation of gated GaAs-AlGaAs resonant tunneling diodes for tunable terahertz communication applications"; V. Georgiev, A. Sengupta, P. Maciazek, O. Badami, C. Medina-Bailon, T. Dutta, F.Adamu-Lema, A. Asenov; (Univ. Glasgow, U. K.) pp.241
[11-7] "Theoretical Study of Double-Heterojunction AlGaN/GaN/InGaN/δ-doped HEMTs for Improved Transconductance Linearity"; T.-H. Yu; (Inforsight Computing, Taiwan) pp.245
[11-8] "Nanoscale FET: How To Make Atomistic Simulation Versatile, Predictive, and Fast at 5nm Node and Below"; P. Blaise1, U. Kapoor1, M. Townsend1, E. Guichard1, J. Charles2, D. A. Lemus2, T. Kubis2; (1 Silvaco, U.S.A., 2 Purdue Univ., U.S.A.) pp.249
3rd group; (from 9:00 am on Oct. 1 to 11:59 pm on Oct. 6, JST)
Session 12: Emerging Devices Chairpersons: Andres Godoy; (Univ. Granada, Spain)Sung-Ming Hong; (Gwangju Inst. Sci. Tech., Korea)[12-1] Invited Talk "TCAD-Assisted MultiPhysics Modeling & Simulation for Accelerating Silicon Quantum Dot Qubit Design"; Fahd Ayyalil Mohiyaddin; (imec, Belgium) pp.253
[12-2] "Physics-augmented Neural Compact Model for Emerging Device Technologies"; Y.Kim, S. Myung, J. Ryu, C. Jeong, D. S. Kim; (Samsung Electronics, Korea) pp.257
[12-3] "A Modeling Study on Performance of a CNOT Gate Devices based on Electrode-driven Si DQD Structures"; H.Ryu, J.-H. Kang; (Korea Inst. Sci. Tech. Info., Korea) pp.261
[12-4] "Simulation and Evaluation of Plasmonic Circuits"; M.Fukuda, Y. Ishikawa; (Toyohashi, Univ. Tech., Japan) pp.265
[12-5] "Numerical study of surface chemical reactions in 2D-FET based pH sensors"; A. Toral-Lopez1, E. G. Marin1, J. Cuesta1, F. G. Ruiz1, F. Pasadas2, A. Mediana-Rull1, A.Godoy1; (1 Univ. Granada, Spain, 2 Univ. Autonoma Barcelona, Spain) pp.269
[12-6] "A Combined First Principle and Kinetic Monte Carlo Study of Polyoxometalates Based Molecular Memory Devices"; P. Lapham, O. Badami, C. Medina-Bailon, F. Adamu-Lema, T. Dutta, V. Georgiev, A.Asenov; (Univ. Glasgow, U.K.) pp.273
[12-7] "Modeling Assisted Room Temperature Operation of Atomic Precision Advanced Manufacturing; (APAM)Devices"; X. Gao, L. Tracy, E. Anderson, DeAnna Campbell, J. Ivie, T.-M. Lu, D. Mamaluy, S.Schmucker, S. Misra; (Sandia National Lab., U.S.A.) pp.277
Session 13: 2D and Nano System I Chairperson: Jeff Wu; (TSMC, Taiwan)
[13-1] "Effects of the Dielectric Environment on Electronic Transport in Monolayer MoS2: Screening and Remote Phonon Scattering"; M. L. Van de Put, G. Gaddemane, S. Gopalan, M. V. Fischetti; (Univ. Texas at Dallas, U.S.A.) pp.281
[13-2] "Impact of Schottky Barrier on the Performance of Two-Dimensional Material Transistors"; S.-K. Su, J. Cai, E. Chen, L.-J. Li, H.-S. Philip Wong; (TSMC, Taiwan) pp.285
[13-3] "AC NEGF Simulation of Nanosheet MOSFETs"; S.-M. Hong, P.-H. Ahn; (Gwangju Inst. Sci. Tech., Korea) pp.289
[13-4] "Enhanced Capabilities of the Nano-Electronic Simulation Software; (NESS)"; C. Medina-Bailon, O. Badami, H. Carrillo-Nunez, T. Dutta, D. Nagy, F. Adamu-Lema, V.Georgiev, A. Asenov; (Univ. Glasgow, U.K.) pp.293
[13-5] "Electrostatic Potential Profile Generator for Two-Dimensional Semiconductor Devices"; S.-C. Han, J. Choi, S.-M. Hong; (Gwangju Inst. Sci. Tech., Korea) pp.297
Session 14: FET Devices and Design Technology Co-Optimization Chairpersons: Mehdi Bazizi,; (Applied Materials, U.S.A.)Lado Filipovic; (TU Wien, Austria)
[14-1] Invited Talk "Agile Pathfinding Technology Prototyping: the Hunt for Directional Correctness"; Daniel Chanemougame; (TEL at Albany, U.S.A.) pp.301
[14-2] "Self-Aligned Single Diffusion Break Technology Optimization Through Material Engineering for Advanced CMOS Nodes"; A. Pal, E. M. Bazizi, L. Jiang, M. Saremi, B. Alexander, B. Ayyagari-Sangamalli; (Applied Materials, U.S.A.) pp.307
[14-3] "L-UTSOI: A compact model for low-power analog and digital applications in FDSOI technology"; S. Martinie1, O. Rozeau1, T. Poiroux1, P. Scheer1, S. E. Ghouli2, M. Kang3, A. Juge2, H. Lee3; (1 CEA, LETI, Univ. Grenoble Alpes, France, 2 STMicroelectronics, France, 3 Samsung, Korea) pp.311
[14-4] "Electromigration Model for Platinum Hotplates"; L.Filipovic; (TU Wien, Austria). pp.315
[14-5] "Compact Modeling of Radiation Effects in Thin-Layer SOI-MOSFETs"; M. Miura-Mattausch, H. Kikuchihara, D. Navarro, T. Iizuka, H. J. Mattausch; (Hiroshima Univ., Japan). pp.319
[14-6] "Complementary FET Device and Circuit Level Evaluation Using Fin-Based and Sheet-Based Configurations Targeting 3nm Node and Beyond"; L. Jiang, A. Pal, E. M. Bazizi, M. Saremi, R. He, B. Alexander, B. Ayyagari-Sangamalli; (Applied Materials, U.S.A.) pp.323
[14-7] "Via Size Optimization for Optimum Circuit Performance at 3 nm node"; S. Mittal1, A. Pal2, M. Saremi2, E. M. Bazizi2, B. Alexander2, B. Ayyagari-Sangamalli2; (1 Applied Materials, India, 2 Applied Materials, U.S.A.) pp.327
[14-8] "Time-Resolved Mode Space based Quantum-Liouville type Equations applied onto DGFETs"; L.Schulz, D. Schulz; (TU Dortmund, Germany) pp.331
Session 15: Machine Learning Chairpersons: Satofumi Souma; (Kobe Univ., Japan)Hiuyung Wong; (San Jose State Univ., U.S.A.)
[15-1] Invited Talk "Power Device Degradation Estimation by Machine Learning of Gate Waveforms"; Makoto Takamiya; (Univ. Tokyo, Japan) pp.335
[15-2] "Machine Learning Prediction of Formation Energies in a-SiO2"; D.Milardovich, M. Jech, D. Waldhoer, M. Waltl, T. Grasser; (TU Wien, Austria) pp.339
[15-3] "Novel Optimization Method using Machine-learning for Device and Process Competitiveness of BCD Process"; J. Kim, J.-H. Yoo, J. Jung, K. Kim, J. Bae, Y.-S. Kim, O.-K. Kwon, U.-H. Kwon, D.-S. Kim; (Samsung Electronics, Korea) pp.343
[15-4] "Real-Time TCAD: a new paradigm for TCAD in the artificial intelligence era"; S. Myung, J. Kim, Y. Jeon, W. Jang, J. Kim, S Han, K.-H. Baek, J. Ryu, Y.-S. Kim, J. Doh, C.Jeong, D. -S. Kim; (Samsung Electronics, Korea) pp.347
[15-5] "Application of Noise to Avoid Overfitting in TCAD Augmented Machine Learning"; S. S. Raju1, B. Wang2, K. Mehta1, M. Xiao2, Y. Zhang2, H.-Y. Wong1; (1 San Jose Univ., U.S.A., 2 Virginia Polytech. Inst. State Univ., U.S.A.) pp.351
[15-6] "Automatic Device Model Parameter Extractions via Hybrid Intelligent Methodology"; C.-C. Liu, Y. Li, Y.-S. Yang, C.-Y. Chen, M.-H. Chuang; (National Chiao Tung Univ., Taiwan) pp.355
[15-7] "Physics-Informed Graph Neural Network for Circuit Compact Model Development"; X. Gao, A. Huang, N. Trask, S. Reza; (Sandia National Lab., U.S.A.) pp.359
Session 16: 2D and Nano System II Chairperson: Frank Register; (Univ. Texas at Austin, U.S.A.)
[16-1] "Theoretical study of electronic transport in monolayer SnSe"; S. Gopalan1, G. Gaddemane2, M. L. Van de Put1, M. V. Fischetti1; (1 Univ. Texas at Dallas, U.S.A., 2 imec, Belgium) pp.363
[16-2] "Transient simulation of graphene FET gated by electrolyte medium"; K. Arihori1, M. Ogawa1, S. Souma1, J. Sato-Iwanaga2, M. Suzuki2; (1 Kobe Univ., Japan, 2 Panasonic, Japan) pp.367
[16-3] "Quantum Transport Simulations of Phosphorene Nanoribbon MOSFETs: Effects of Metal Contacts, Ballisticity and Series Resistance"; M.Poljak, Mislav Matic; (Univ. Zagreb, Croatia) pp.371
[16-4] "High-Performance Metal-Ferroelectric-Semiconductor Nanosheet Line Tunneling Field Effect Transistors with Strained SiGe"; N. Thoti1, Y. Li1, S. R. Kola1, S. Samukawa2; (1 National Chaio Tung Univ., Taiwan, 2 Tohoku Univ., Japan) pp.375
[16-5] "A First-Principles Study on the Strain-induced Localized Electronic Properties of Dumbbell-shape Graphene Nanoribbon for Highly Sensitive Strain Sensors"; Q.Zhang, K. Suzuki, H. Miura; (Tohoku Univ., Japan) pp.379
Late News Chairperson: Tatsuya Kunikiyo; (Renesas Electronics, Japan)
LN "Multiband Phase Space Operator for Narrow Bandgap Semiconductor Devices"; L.Schulz, D. Schulz; (TU Dortmund, Germany) pp.383
[conference] CADTFT2020 Final Program
Final Program
11th International Conference on Computer Aided Design for Thin-Film Transistor Technologies
November 9-11, 2020
http://www.cadtft2020.org/
2020/11/09 Monday Day 1 (1/3)
Tutorial Session 1 (Chair: Kai Wang)
[T1] Karim S. Karim Uni. Waterloo; Canada;"Next Generation Diagnostic X-ray Imagers for Scalable and Sustainable Healthcare"
[T2] Samar Saha IEEE Electron Device Society "What can we learn from Fin-FET?"
Poster Session (Chair: Di Geng)
[P1] Guan Ying Wang Uni. Toronto; Canada;"Electrolyte-gated Field Effect Transistors in Biological Sensing"
[P2] Mihir Srivastava Avantika University; India;"A Simple Approach to Estimate Performance Deteriorations of Circuits with Non-Ohmic TFTs"
[P3] Zhaohan Peng National Center for Nanoscience and Technology CAS; China;"High Electrical and Mechanical Stability of IGZO Transistor Arrays on Flexible Substrate"
[P4] Penglong Chen Chongqing Uni. Posts and Telecommunications; China;"A New Voltage-Programming IGZO TFT AMOLED Pixel Compensation Circuit"
[P5] Fengjing Liu National Center for Nanoscience and Technology CAS; China;"Organic-inorganic Hybrid Complementary Inverter Based Photodetector with Amplified Voltage-output"
[P6] Eva Bestelink Uni. Surrey; UK;"Source-Gated Transistor Current Mirrors with Negative Temperature Dependence"
Tutorial Session 2 (Chair: Xiaojun Guo)
[T3] Sanjiv Sambandan Indian Institute of Science; India;"Challenges and Solutions to Analog Integrated Circuit Design with Thin Film Transistors"
[T4] Arokia Nathan Uni. Cambridge; UK;"TFT Circuits for Signal Processing"
[T5] Yvan Bonnassieux Ecole Polytechnique; France;"Compact Modeling of Organic Field-Effect Transistors"
[T6] Slobodan Mijalkovic Silvaco Europe; UK;"Compact Modeling of Hysteretic Phenomena"
2020/11/10 Tuesday Day 2 (2/3)
Opening Plenary Session 1 (Ling Li)
[P1] Feng Qin Tianma Microelectronics; China;"TFT Foundry Multi-Project"
[P2] Yanfeng Li Primarius Technologies; China;"Enabling DTCO with a Complete EDA Ecosystem from Data to Simulation"
Session 1 Device Modeling and Characterization (Chair: Liling Zhang)
[1-1] Ta-Ya Chu National Research Council; Canada;"Pinch-Off Mobility Extraction for Organic Thin-Film Transistors"
[1-2] Sungyeop Jung Seoul National University; South Korea;"Organic Thin-Film Transistor Compact Modeling"
[1-3] Wanling Deng Jinan University; China;"Modelling Method based on BP Neural Network and Artificial Bee Colony Algorithm for Metal-oxide Thin-Film Transistors"
[1-4] Jumbum Park Ecole Polytechnique; France;"Validation of Power-law Drain Current Model for Coplanar OFETs at Various Temperatures"
[1-5] Mingxiang Wang Soochow University; China;"Comparative Study of Dynamic Degradation of Oxide TFTs in ESL or EMMO Structure"
Session 2 Device Design and Technology (Chair: Chuan Liu)
[2-1] Paddy Chan The Uni. Hong Kong; China;"Solution Processed Organic Monolayer Field Effect Transistors"
[2-2] Sanjiv Sambandan Indian Institute of Science; India;"Adaptive Dielectric Thin Film Transistors - A New Interface Device for Large Area, Flexible and Wearable Electronics"
[2-3] Aiming Song Uni. Manchester; UK;"Thin Film Transistors Based on Semiconductors and Semimetals"
[2-4] Andrew Flewitt Uni. Cambridge; UK;"Quantitative Analysis of the Bias Stress-Induced Threshold Voltage Shift in TFTs incorporating Disordered Materials"
Session 3 Device and Circuit Interaction (Chair: Chair: Xueqing Li)
[3-1] Niko Muenzenrieder Free University Bolzano; Italy;"Tools and Strategies to Optimize the Electrical and Mechanical Properties of Flexible TFTs"
[3-2] Ya-Hsiang Tai NCTU "Acquiring Differential Light Signal with TFT Sensing Array"
[3-4] Radu Sporea Uni. Surrey; UK;"Multimodal Thin-film Transistors: an Opportunity for Analog Signal Processing and Computation"
[3-5] Chen Jiang Uni. Cambridge; UK;"All-Inkjet-Printed Ultra-low-Power Organic Thin-Film Transistors for Electrophysiological Monitoring"
[3-6] Gerwin Gelinck Holst Centre, TNO; Netherland;"Organic Photodiodes for Imaging and Sensing Applications"
Plenary Session 2 ( Chair: Arokia Nathan)
[P3] Zhigang Shuai Tsinghua University; China;"First-principles Methods for Investigating Carrier Transport and Light-Emitting in Organic Semiconductors"
[P4] Ahmed Nejim Silvaco Europe; UK;"Modelling Thin Film Electronics - Recent TCAD Developments"
2020/11/11 Wednesday Day 3 (3/3)
Plenary Session 3 (Chair: Ling Li)
[P5] Jin Jang Kyung Hee University; South Korea;"Mechanical Stabilities of TFTs on Flexible Substrate"
[P6] Tim Cheng Hong Kong Uni. Science and Technology; China;"Ultra-thin and Robust Skin Electronics for High Quality and Continuous Skin-Sensor-Silicon Interfacing"
Session 4 Material Design & Processing ( Chair: Hang Zhou)
[4-1] Simon Rongdeau-Gagne Uni. Windsor; Canada;"Design of Stretchable and Self-healable Polymers for Fabrication of Stretchable Transistors"
[4-2] Myung-Gil Kim Sungkyunkwan University; South Korea;"Solution-Processing of Hybrid Materials for Flexible Electronics and Sensors"
[4-3] Min Zhang Peking University; China;"High-Performance Intrinsically Soft Thin Film Transistors"
[4-4] Xiaochen Ren Tianjin University; China;"Solution Processed Organic Crystalline Arrays for High-performance Organic Field-effect Transistors"
Session 5 Circuit Design (Chair: Hanbin Ma)
[5-1] Yuanfeng Chen Kyung Hee University; South Korea;"Gate Driver using Low-Temperature Poly-Si Oxide TFTs with Mobility Compensation"
[5-2] Congwei Liao Peking University; China;"Thin-film Transistor Integrated Gate Driver Circuit Design for in-Cell Touch Display"
[5-3] Seung-Woo Lee Kyung Hee University; South Korea;"Fault-tolerant Integrated Scan Driver Circuit for Implantable Bio-sensor Systems"
[5-6] Hongge Li Beihang University; China;"A High-precision Low Power Driver Circuit for Printed Display"
Session 6 Emerging Applications (Chair: Kai Wang)
[6-1] Xueqing Li Tsinghua University; China;"Organized by: Co-organized by: Technical Sponsor: "Emerging Ferroelectric Memory and Computing"
[6-2] Hanbin Ma SIBET CAS; China;"Active Matrix Digital Microfluidics Lab-on-a-Chip with Drain-offset a-Si TFTs"
[6-3] Xiao Gong National Uni. Singapore; Singapore;"Amorphous Metal Oxide-based TFTs for 3D Monolithic Integration Nano-electronic Systems"
[6-4] Zhe Liu Hangzhou LinkZill Technology Co. Ltd; China;"TFT-based System for Beyond-display Applications"
[6-5] Hang Zhou Peking University Shenzhen Graduate School; China;"Perovskite-IGZO Hybrid Phototransistor for Photodetection and Image Sensor"
Plenary Session 4 (Chair: Arokia Nathan)
[P7] Benjamin Iñiguez Universitat Rovirai Virgili; Spain;"Modeling of Low Frequency Noise in Organic and Oxide TFTs"
China-Europe Dialogue on TFT Compact Modeling
- Benjamin Iñiguez Universitat Rovirai Virgili; Spain; "European DOMINO Project on TFT Compact Modeling"
- Shijia Lin Huada Empyrean Software; China; "Advances in TFT Device and Reliability Modeling"
Closing Remarks
Nov 21, 2020
[mos-ak] [Final Program] 13th International MOS-AK Workshop; Silicon Valley, Dec.10-11 2020
Together with THM Giessen, the MOS-AK workshop online host and IEEE Young Professionals (Germany), technical program promoter as well as all the Extended MOS-AK TPC Committee, we have the pleasure to invite to consecutive, 13th International MOS-AK Workshop is Silicon Valley which will be Virtual/Online event using Zoom platform.
Scheduled, subsequent 13th MOS-AK SPICE/Compact Modeling Workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors.
The MOS-AK workshop program is available online:
Venue: Virtual/Online Workshop on Zoom platform
- virtual session 11:00 - 14:00 (PST) on Dec.10, 2020
- virtual session 11:00 - 14:00 (PST) on Dec.11, 2020
Online free Registration is open, now. Registered participant will receive Zoom meeting invitation.
(any related enquiries can be sent to registration@mos-ak.org)
Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special Solid State Electronics issue on compact modeling
W.Grabinski on the behalf of International MOS-AK Committee
WG20112020
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Nov 20, 2020
#EspoTek Labrador: a complete arsenal of electronic engineering instruments: an oscilloscope, function generator, power supply, logic analyzer and multimeter. https://t.co/KjhalAi080 #semi https://t.co/CC6pt5DxiD
#EspoTek Labrador: a complete arsenal of electronic engineering instruments: an oscilloscope, function generator, power supply, logic analyzer and multimeter. https://t.co/KjhalAi080#semi pic.twitter.com/CC6pt5DxiD
— Wladek Grabinski (@wladek60) November 20, 2020
from Twitter https://twitter.com/wladek60
November 20, 2020 at 02:29PM
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[Launch Event] EMPHASIS University of Cyprus
LAUNCH EVENT: November 25, 2020 10:00-13:30EET
EMPHASIS is a multidisciplinary research centre involving departments from the School of Engineering and School of Pure & Applied Sciences from the University of Cyprus. Join us online to learn more about our labs' research in the key enabling technologies behind the digital revolution: electronics, microwaves & antennas, photonics and sensors.
SCHEDULE: (Eastern European Time)
10:00–10:10: Introduction
Prof.Tasos Christofides, Rector of the University of Cyprus
10:10–10:20: Introductory Remarks
Dr.Nikolas Mastroyiannopoulos, Chief Scientist for Research and Innovation
10:20–10:50: EMPHASIS Research Centre: Vision & Goals,
Prof.Stavros Iezekiel, Acting Director of EMPHASIS
BREAK
11:00–11:30: EMPHASIS Research Laboratory Presentations 11:30–13.30: Presentation of Selected Research Projects in Electronics, Microwaves & Antennas, Photonics and Sensors
SESSION1: 11:30-12:30
• Medical Electronics,Prof.Julius Georgiou
• Sensors for Precision Agriculture,
Dr.Marios Sophocleous
• Resveratrolloaded Polymeric Miceles for Theranostic Targeting of Breast Cancer Cels,
Dr.Yiota Grigoriou
• White Light Emitting Structures Based on II-Nitrides and Lead Halide Perovskite Nanocrystals,
Dr.Modestos Athanasiou
• Multi-bacteria,Multi-antibiotic Testing Using Surface Enhanced Raman Spectroscopy
(SERS)forUrinary Tract Infection (UTI)Diagnosis,
(SERS)forUrinary Tract Infection (UTI)Diagnosis,
Dr.Katerina Hadjigeorgiou
BREAK
SESSION2: 12:30-13:30
• Electric-Field Measurements of Microwave Circuits,Dr.Haris Votsi
• Integrated Circuits for RF Metasurfaces,
Loukas Petrou/Kypros Kossifos
• Influence of Carriers in Spin Pumping in Organic Semiconductors,
Constantinos Nicolaides
• Microwave Photonics for Space,
Georgios Charalambous
• Wireless Power Transfer (WPT) and Far-Field RF Energy Harvesting,
Dr.Abdul Quddious
[paper] Characterization of ultrathin FDSOI devices using subthreshold slope method
Teimuraz Mchedlidze1, and Elke Erben2
Characterization of ultrathin FDSOI devices using subthreshold slope method
Phys. Status Solidi A. Accepted Manuscript
DOI: 10.1002/pssa.202000625
1 TU Dresden, Germany
2 Globalfoundries, Dresden, Germany
Abstract: The subthreshold current-voltage (subthreshold slope) characteristic of fully depleted silicon-on-insulator high-k dielectric-metal gate field-effect transistor is applied for evaluation of the interface traps located at both, the front and back channels. The proposed characterization method allows an estimation of averaged trap densities separately for the front and the back interfaces of the channel. Performing subthreshold slope measurements at several temperatures allow the extraction of the energy distributions of the interface trap densities for both interfaces and obtaining essential characteristics of the stack.
Fig: Results of ID(VGF,k,T) measurements for EG sample. At each temperature
(200, 300 and 400K) a group of curves contains data for eight k values
(k = 0 to 3 with step 0.5 and kOC; solid curve).
Acknowledgements: The authors would like to acknowledge funding of the study in the frames of the IPCEI WIN- FDSOI project from Global Foundries. We want to thank Jörg Weber (TU Dresden), Luca Pirro (Global Foundries) and Rolf Öttking (AQ Computare, Chemnitz) for thoughtful discussions and suggestions.
Nov 19, 2020
#Nanoscale #Schottky #diodes fabricated via adhesion lithography https://t.co/dkeSdlinNP #semi https://t.co/u353DjjCVP
#Nanoscale #Schottky #diodes fabricated via adhesion lithography https://t.co/dkeSdlinNP#semi pic.twitter.com/u353DjjCVP
— Wladek Grabinski (@wladek60) November 19, 2020
from Twitter https://twitter.com/wladek60
November 19, 2020 at 04:38PM
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