[paper] SPICE-level Crossbar-array Circuit Simulator

Fan Zhang¹ and Miao Hu² 

CCCS: Customized SPICE-level Crossbar-array Circuit Simulator

for In-Memory Computing

IEEE/ACM International Conference on Computer-Aided Design

(ICCAD ’20) November 2– 5, 2020, Virtual Event, USA. 

ACM, New York, NY, USA, 8 pages.

DOI: 10.1145/3400302.3415627

1Arizona State University Tempe, Arizona
2Binghamton University Binghamton, New York

ABSTRACT: Resistive crossbar arrays are known for their unique structure to implement analog in-memory vector-matrix-multiplications (VMM). However, general-purpose circuit simulators, such as HSPICE and HSIM, are too slow for large scale crossbar array simulations with consideration of circuit parasitics. Although there are some specific simulators designed for crossbar arrays, they mainly focus on area/power/delay estimation rather than accurate SPICE-level simulation, thus could not model its functionality on analog in-memory computing. In this paper, we firstly give a SPICE-level modeling of resistive crossbar array with consideration of circuit parasitics in MATLAB. We also propose efficient methods to further speedup simulations by model simplifications. Last but not least, ResNet-20 on CIFAR-10 is applied to demonstrate the work. With the proposed model simplification methods, simulation speed can be improved by ~31X with tolerable errors, and more than 5X speedup is achieved on ResNet-20 while the accuracy drop is 6%.

Figure: Implement the ResNet on the crossbar with sub-block optimization. 

RELATED WORK: Other than general-purpose circuit simulators, specific simulation platforms have been proposed for crossbar-based application analysis; examples include: 

[MNSIM] L. Xia, B. Li, T. Tang, P. Gu, X. Yin, W. Huangfu, P. Chen, S. Yu, Y. Cao, Y. Wang, Y. Xie, and H. Yang. MNSIM: Simulation platform for memristor-based neuromorphic computing system. In 2016 Design, Automation Test in Europe Conference Exhibition (DATE). 469–474.
[NeuroSim] P. Chen, X. Peng, and S. Yu. 2018. NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, 12 (Dec 2018), 3067–3080.