[paper] Flexible TFT Electronics

Hikmet Çeliker, Wim Dehaene and Kris Myny

Multi-project wafers for flexible thin-film electronics by independent foundries.

Nature (2024)

DOI: 10.1038/s41586-024-07306-2

1. ESAT, KU Leuven, Leuven, Belgium
2. imec, Leuven, Belgium

Abstract: Flexible and large-area electronics rely on thin-film transistors (TFTs) to make displays large-area image sensors, microprocessors, wearable healthcare patches, digital microfluidics, and more. Although silicon-based complementary metal–oxide–semiconductor (CMOS) chips are manufactured using several dies on a single wafer and the multi-project wafer concept enables the aggregation of various CMOS chip designs within the same die, TFT fabrication is currently lacking a fully verified, universal design approach. This increases the cost and complexity of manufacturing TFT-based flexible electronics, slowing down their integration into more mature applications and limiting the design complexity achievable by foundries. Here we show a stable and high-yield TFT platform for the fabless manufacturing of two mainstream TFT technologies, wafer-based amorphous indium–gallium–zinc oxide and panel-based low-temperature polycrystalline silicon, two key TFT technologies applicable to flexible substrates. We have designed the iconic 6502 microprocessor in both technologies as a use case to demonstrate and expand the multi-project wafer approach. Enabling the foundry model for TFTs, as an analogy of silicon CMOS technologies, can accelerate the growth and development of applications and technologies based on these devices.

FIG:  Photograph of all three chips at once: the vintage WDC 65C02 in a 40-pin DIP package (left), the flex LTPS 6502 (middle) and the flex IGZO 6502 (right)

Acknowledgements: We thank PanelSemi (a system-on-film foundry service provider in Taiwan) for providing LTPS panels and Pragmatic for providing IGZO wafers as a verification of our designs, using their foundry-mode panel and wafer delivery services. Part of this work has received funding under the Horizon Europe programme from the European Research Council under grant agreement no. 101088591 ‘ORISON project’. Views and opinions expressed are, however, those of the authors only and do not necessarily reflect those of the European Union or the European Research Council. Neither the European Union nor the granting authority can be held responsible for them.

[C4P] Orbitaly2024 in Bologna

8th International Conference on Organic Bioelectronics

Orbitaly2024

Bologna Sept. 23-25, 2024

OrBItaly (Organic BIoelectronics Italy) is an international conference, organized by the Italian scientific community and dedicated to the most recent results in the field of bioelectronics, with a particular focus on the employment of organic materials. OrBItaly has attracted in the years a growing interest of the scientists coming from all over the world. The 2024 edition is the seventh one of this cross-disciplinary conference, and will be held in Bologna, on September 23rd-25th, 2024, at the San Giovanni in Monte historic building in the centre of Bologna.

The abstract submission is open, with its deadline on 15th June 2024. 

All details about the conference can be found on the website: https://eventi.unibo.it/orbitaly2024

Looking forward to meeting you in Bologna

The OrBItaly 2024 Organizing Committee

Beatrice Fraboni, 

Francesco Decataldo, 

Marta Tessarolo, 

Tobias Cramer,

Vito Vurro

[webinar] Open Source EDA Development of Chips in Europe

Professor Marie-Minerve Louerat, Sorbonne Université-CNRS, GoIT Project, has announced the upcoming webinar on Open Source EDA fostering development of Chips in Europe

"Introduction to the open-source EDA ecosystem"

online webinar to foster engagement for Open-Source EDA and Open-Silicon development in Europe

📅 Tuesday May 14, 2024 🕙 10:00-12:00 (CEST) with Free Online Registration

Workshop Agenda:

• European Semiconductor Design Ecosystem (10 min)
• Matthew Xuereb, European Commission
• Open-Source Semiconductor Ecosystem (15 min)
• Luca Alloatti, Free Silicon Foundation (I) ETS
• Open-Source EDA Software and Semiconductor Design (15 min)
• Jean-Paul Chaput, Sorbonne Université, Coriolis Foundation
• European Roadmap on the Advancement of Open-Source EDA Tools, next steps (15 min)
• Rihards Novickis, Latvian Institute of Electronics and Computer Science
• Q&A session / Feedback (up to 1 hour)

NB: 2nd event - to be announced

Location: Paris, Sorbonne Université

📅 Date: June 18, 2024, before FSiC2024 conference

[IEEE SSCS] “PICO” Open-Source Chipathon

IEEE SSCS “PICO” Open-Source Chipathon

Automating Analog Layout

https://sscs.ieee.org/about/tc-ose/sscs-pico-design-contest

– Sign-Up Deadline: May 10, 2024 –

The IEEE Solid-State Circuits Society is pleased to announce its fourth open-source integrated circuit (IC) design contest under the umbrella of its PICO Program (Platform for IC Design Outreach). While this contest is open to anyone (no restrictions), we encourage the participation of pre-college students, undergraduates, and geographical regions that are underrepresented within the IC design community. 

The goal of this year’s event is to advance the automatic generation and open sharing of analog circuit layout cells to increase our community’s design productivity and to catch up with other fields where sharing and automation is a key enabler of progress (e.g., in machine learning).

Die photo in background courtesy of IBM

Contest Outline

1. Interested individuals sign up using this form by May 10, 2024.
2. Phase 1 (~June): Through a series of weekly meet-ups and training sessions, the participants learn to create basic one- or two-transistor layout generators using Python and open-source CMOS PDKs. Using Jupyter Notebooks hosted on Google Colab allows anyone with an internet connection to participate - no downloads or installations required! Relevant circuit examples can be found in [1], [2]. We will leverage code modules available with the OpenFASoC [3] environment.
3. Phase 2 (~July): Interested participants define larger layout building blocks that they wish to automate (examples: comparator, bandgap, phase interpolator, OTA). Teaming among participants is encouraged to maximize collaboration and learning).
4. Phase 3 (~August-September): Participants implement their generators and submit sample layouts and test structures for potential tape-out to an open-source MPW (tentatively SKY130).
5. Phase 4 (~October-November): A jury evaluates the created generators/layouts and selects the test structures that will be taped out. The teams work together to assemble a shared database with all the designs and to complete the tapeout. Ideally, this phase will involve automated verification through CACE [4] or a similar tool.
6. Phase 5 (TBD): The designs will be tested using lab measurements by a subset of participants and SSCS volunteers with access to lab facilities. Some of the test setups may be available for remote characterization. The obtained measurement data will be added to the repositories containing the layout generators.

 References

[1] H. Pretl, “Fifty Nifty Variations of Two-Transistor Circuits,” MOS-AK Workshop Spring 2022, URL: https://www.mos-ak.org/spring_2022/presentations/Pretl_Spring_MOS-AK_2022.pdf.
[2] H. Pretl and M. Eberlein, "Fifty Nifty Variations of Two-Transistor Circuits: A tribute to the versatility of MOSFETs," in IEEE Solid-State Circuits Magazine, vol. 13, no. 3, pp. 38-46, Summer 2021, URL: https://ieeexplore.ieee.org/document/9523464.
[3] OpenFASoC: Fully Open-Source Autonomous SoC Synthesis using Customizable Cell-Based Synthesizable Analog Circuits, https://github.com/idea-fasoc/OpenFASOC/.
[4] Circuit Automatic Characterization Engine, URL: https://github.com/efabless/cace.

[paper] SiC Power MOSFET SPICE modelling

Akbar Ghulam

Accurate & Complete behaviourial SPICE modelling 

of commercial SiC Power MOSFET OF 1200V, 75A

25th EuroSimE, Catania, Italy, 2024, pp. 1-4,

DOI: 10.1109/EuroSimE60745.2024.10491420

* UNIPA Palermo (IT)

Abstract: Silicon Carbide (SiC) is proved to be an excellent replacement for Silicon in high voltage and high frequency applications due to its electro-thermal properties. Since SiC power MOSFETs have only recently been more widely available commercially, accurate simulation models are immediately required to forecast device behavior and facilitate circuit designs. The goal of this paper is to develop an accurate LTSPICE model based on a modified Enz-Krumenacher-Vittoz (EKV), MOSFET model for a 1200V, 30mΩ & 75ASiC power MOSFET “SCTW100N120G2AG” provided by STMicroelectronics that is currently on the market. The modified EKV model outperforms the reduced quadratic model by describing MOSFET behavior over different zones which are weak, moderate, and strong inversion zones with only a single equation. A wide range of experimental data was used to build the model's parameters. To estimate device performance in high frequency switching applications, the model has been expanded to include package parasitic components that include parasitic capacitances. The model's static and transient properties were simulated, and the results were compared with those acquired from the actual device.

FIG: The SiC MOSFET's circuit schematic utilizing a modified EKV model

Acknowledgements: We would like to thank STMicroelectronics, as for completion of this study has been greatly aided by their participation and availability of relevant data.