[github] new RevEDA Release

Revolution EDA Schematic/Symbol/Layout Editors

https://github.com/eskiyerli/revedaRelease

A new release of Revolution EDA is almost here, including a brand-new hierarchical layout editor with GDS export capability, revamped schematic, and symbol editors. Layout editor can use python-based parametric layout cells. The editor can also create vias and via arrays, paths (Manhattan, diagonal and free-angle), rectangles, polygons, pins and texts. Schematic editor can now import Spice subcircuits and create symbols for inclusion in the schematic editor. A cell can have more than one cellview such as SPICE, Verilog-A or symbol that can be used in the netlisting. The netlisting process can be controlled by a switch-view list or by a separate config view. Unlike leading commercial EDA systems, netlisting and GDS export process are running as separate threads and do not block the user's work.

Any interested parties are kindly invited to get in touch with Murat Eskiyerli, the lead RevEDA developer

[C4P] 82nd DRC

DRC 2024 

The 82nd Device Research Conference

The University of Maryland, College Park

2024.DEVICERESEARCHCONFERENCE.ORG

DRC will be held in coordination with the Electronic Materials Conference (EMC), which will occur the same week, from June 26-28. This recognizes the strong interaction between device and electronic materials research and provides fruitful exchanges of information between attendees of both Conferences.

The 2024 Conference will feature:

• An informative, timely short course in rapidly developing fields
• Oral and poster presentations on electronic/photonic device experiments 
• and simulations
• Plenary and invited presentations given by worldwide leaders
• Evening rump sessions
• Strong student participation and Student Paper Awards
• Focus Sessions on Devices for Neuromorphic Computing
• More than 50 invited speakers covering a wide spectrum of devices

Topics to be presented include:

Devices for Biological and Healthcare Applications Emerging Devices Devices for Extreme Conditions Spintronic and Magnetic Devices Memory Devices Modeling and Simulation of Devices Nanoscale and Vacuum Devices Optoelectronic and Optical Devices

Power Devices Quantum Devices Heterogeneously Integrated Devices Thin-Film and Flexible Devices RF and Terahertz Devices Wide-bandgap Device 2D Materials and Devices Neuromorphic Computing Devices

Important Dates

• Feb. 16, 2024 Abstract Submission Deadline
• April 5, 2024 Acceptance Notification
• April 10, 2024 Registration Opens
• May 15, 2024 Early Bird Registration Deadline

[paper] OTA using the Open Sky130 PDK

Carolina Vieira Souza, Edmar Philipe Ribeiro

and Estêvao Coelho Teixeira

Design of a Linear Transconductance OTA using the Open Sky130 Process Design Kit

Sociedade Brasileira De Microeletrônica

(2023) sbmicro.org.br
doi: 10.5281/zenodo.10646550

Faculdade de Engenharia, Universidade Federal de Juiz de Fora, Brazil

Abstract: This paper describes the design, layout and simulation of a linear transconductance Operational Transconductance Amplifier (OTA) using the SkyWater 130nm open Process Design Kit (PDK). By using a known source degeneration technique, it is possible to either decrease and linearize the transconductance of the OTA for a wider range of input voltages, making it proper for use on Gm-C filters. Only open source tools, suited for the Sky130 PDK, were used in this design, showing the applicability to analog designs.

Fig: Linear OTA Structure: (a) Complete circuit, with source degeneration resistors;
(b) Alternative source degeneration triode MOSFETs; and its GDSII layout, with identification of some relevant parts: (A) differential pair; (B) source-degeneration resistors; (C) biasing transistors.

Acknowledgment: This work is result from a scientific initiation project covered by the VI VIC 2022/2023 Program, by PROPP/UFJF.

[paper] Polylogarithms in MOSFET Modeling

A. Ortiz-Conde and F. J. García-Sánchez

Recent Applications of Polylogarithms in MOSFET Modeling

2023 IEEE 33rd International Conference on Microelectronics

MIEL, Nis, Serbia, 2023, pp. 1-8

DOI: 10.1109/MIEL58498.2023.10315897

Department of Electronics and Circuits, Universidad Simón Bolívar, Caracas, Venezuela

Abstract: We present a review of recent uses of the special mathematical function known as the polylogarithm for MOSFET modeling applications. We first summarize some basic properties of polylogarithms, with a particular focus on those with negative exponential argument. After examining cases of the use of first order polylogarithms pertinent to electron device modeling, we explain the reasons that motivate the use of polylogarithms of diverse orders for formulating mono- and poly-crystalline succinct compact MOSFET models. We then analyze a particular representative example: the modeling of polysilicon MOSFETs using the polylogarithm. Recalling that polylogarithms may be used to faithfully represent Fermi-Dirac Integrals in general, and considering that they are analytically differentiable and integrable, we describe a full Fermi–Dirac Statistics-based version of the usually approximate Boltzmann Statistics-based MOSFET Surface Potential Equation (SPE).

TABLE: Some Features of Polylogarithms with Negative Exponential Argument

[paper] Compact Model of Graphene FETs

Nikolaos Mavredakis, Anibal Pacheco-Sanchez, Oihana Txoperena,

Elias Torres, and David Jiménez

A Scalable Compact Model for the Static Drain Current of Graphene FETs

IEEE TED, Vol. 71, No. 1, January 2024

DOI:  10.1109/TED.2023.3330713

1 Departament d’Enginyeria Electrònica, Escola d’Enginyeria, UAB, 08193 Bellaterra, Spain
2 Graphenea Semiconductor SLU, 20009 San Sebastián, Spain.

Abstract: The main target of this article is to propose for the first time a physics-based continuous and symmetric compact model that accurately captures I–V experimental dependencies induced by geometrical scaling effects for graphene field-effect transistor (GFET) technologies. Such a scalable model is an indispensable ingredient for the boost of large-scale GFET applications, as it has been already proved in solid industry-based CMOS technologies. Dependencies of the physical model parameters on channel dimensions are thoroughly investigated, and semi-empirical expressions are derived, which precisely characterize such behaviors for an industry-based GFET technology, as well as for others developed in the research laboratory. This work aims at the establishment of the first industry standard GFET compact model that can be integrated in circuit simulation tools and, hence, can contribute to the update of GFET technology from the research level to massive industry production.

Fig: Graphenea GFET schematic cross-section not drawn to scale. Graphene under metal contacts is not shown.The drain current has explicit derivation in respect to Qgr, where Qt and Qp(n) are the transport sheet and p(n)-type charges, respectively; Vc is the chemical potential, h is the reduced Planck constant, uf is the Fermi velocity, e is the electron charge, and k is a coefficient. Qt and, thus, ID can be calculated according to Vc polarity at source (Vcs) and drain (Vcd), respectively. Hence, at n-type region where Vcs, Vcd > 0 and Qp = 0

Acknowledgements: This work was supported in part by the European Union’s Horizon 2020 Research and Innovation Program GrapheneCore3 under Grant 881603; in part by the Ministerio de Ciencia, Innovación y Universidades under Grant RTI2018-097876-B-C21 (MCIU/AEI/ FEDER, UE), Grant FJC2020-046213-I, and Grant PID2021-127840NBI00 (MCIN/AEI/FEDER, UE); in part by the European Union Regional Development Fund within the Framework of the ERDF Operational Program of Catalonia 2014–2020 with the Support of the Department de Recerca i Universitat, with a grant of 50% of Total Cost Eligible; and in part by the GraphCAT Project under Grant 001-P-001702.