Sep 10, 2023

[book] Advanced Ultra Low-Power Semiconductor Devices

Advanced Ultra Low-Power Semiconductor Devices
Design and Applications

Edited by Shubham Tayal, Abhishek Kumar Upadhyay, Shiromani Balmukund Rahi, and Young Suh Song

ISBN: 9781394166411 | (C)2023  Hardcover | 306 pages

Description
This outstanding new volume offers a comprehensive overview of cutting-edge semiconductor components tailored for ultra-low power applications. These components, pivotal to the foundation of electronic devices, play a central role in shaping the landscape of electronics. With a focus on emerging low-power electronic devices and their application across domains like wireless communication, biosensing, and circuits, this book presents an invaluable resource for understanding this dynamic field.

Bringing together experts and researchers from various facets of the VLSI domain, the book addresses the challenges posed by advanced low-power devices. This collaborative effort aims to propel engineering innovations and refine the practical implementation of these technologies. Specific chapters delve into intricate topics such as Tunnel FET, negative capacitance FET device circuits, and advanced FETs tailored for diverse circuit applications.

Beyond device-centric discussions, the book delves into the design intricacies of low-power memory systems, the fascinating realm of neuromorphic computing, and the pivotal issue of thermal reliability. Authors provide a robust foundation in device physics and circuitry while also exploring novel materials and architectures like transistors built on pioneering channel/dielectric materials. This exploration is driven by the need to achieve both minimal power consumption and ultra-fast switching speeds, meeting the relentless demands of the semiconductor industry. The books scope encompasses concepts like MOSFET, FinFET, GAA MOSFET, the 5-nm and 7-nm technology nodes, NCFET, ferroelectric materials, subthreshold swing, high-k materials, as well as advanced and emerging materials pivotal for the semiconductor industrys future.

Sep 8, 2023

[conference] 10th Micro Nano 2023

10th International Conference "Micro Nano 2023"
Location: Demokritos Congress Center
Dates: November 2nd-5th 2023

The Micro Nano 2023 Organizing Committee is looking forward to welcoming you to Athens to the 10th International Conference on Micro-Nanoelectronics, Micro-Nanosciences and Nanotechnologies (https://2023.micro-nano.gr), our annual event that brings together Academia, Research and Industry to discuss the latest advancements of the field.

We are happy to announce that the abstract submission is already open and would like to prompt you to submit your work by September 18th. Also, take advantage of the early bird registration discounts, which are open until October the 9th

Visit https://2023.micro-nano.gr/call-for-paper/ to submit your abstract 
and https://2023.micro-nano.gr/fees-registration/ for registration details.

We would like to remind you that this year’s conference includes a Celebratory Special Event for the conference’s 10th Anniversary, scheduled as an Opening Ceremony on the first day (November 2nd, 2023) to commemorate and celebrate 40 years of Microelectronics in Greece. We are also excited about this year’s 
Check our website for more information on the stimulating presentations that lie ahead.

Dates to remember:
  • Abstract submission deadline: September 18th, 2023
  • Early-bird registration: October 9th, 2023
  • Late poster presentation: October 23rd, 2023
Venue:
  • Special Event: Main Hall of the National and Kapodistrian University of Athens (Panepistimiou 30)
  • Special Event (Nov.2): “40 years of Microelectronics in Greece”
    https://2023.micro-nano.gr/special-event/
Technical Program
We are looking forward to seeing you all in November!

On behalf of the Organizing Committee,
Prof. Margarita Chatzichristidi, Conference Chair
Dr. Eleni Makarona, Conference Co-chair

Conference e-mail address: MicroNano2023@chem.uoa.gr


 

Sep 5, 2023

[paper] VNWFET-based technology

VNWFET-based technology: from device modelling to standard cell library
Sara Mannaa, Cedric Marchand, Damien Deleruyelle, Bastien Deveautour, 
Ian O’Connor, Alberto Bosio
2023 IEEE 23rd International Conference on Nanotechnology (NANO),
Jeju City, S.Korea, 2023, pp. 576-581
DOI: 10.1109/NANO58406.2023.10231288

Univ Lyon, ECL, INSA Lyon, CNRS, UCBL, CPE Lyon, INL, UMR5270, 69130 Ecully, France

Abstract: Vertical Nanowire Field Effect Transistors (VNWFETs) are an emerging technology with significant potential to reduce footprint and consequently interconnect capacitance, thereby achieving improved energy-efficiency and being naturally compatible with advanced 3D integration approaches. However, while initial estimations have focused on projections and estimations, no work has so far used a detailed compact model to attempt accurate transistor-level simulations for standard cell library characterization, thus enabling logic synthesis. In this paper, we propose a design flow to make the link from an existing (laboratory-scale) VNWFET technology and the associated compact model, to standard static logic cell design and characterization, and ultimately logic synthesis. To the best of our knowledge, this is the first work to prove the possibility of such a realistic design flow tailored to VNWFET technologies.

Fig: Through actual VNWFET fabrication setting up a design-technology co-optimization (DTCO) approach, the FVLLMONTI vision is to develop regular 3D stacked hardware layers of NNs empowering the most efficient machine translation thanks to fine-grain hardware / software co-optimisation.

Acknowledgment: This work has been founded by FVLLMONTI European Union’s Horizon 2020 research and innovation programme under grant agreement No 101016776.

Call for Book Chapters

Nanoscale Electronic Device Applications of Carbon Nanotubes,
Graphene, Silicene and Molybdenum Disulfide



[C4P] EDTM Conference 2024, Bangalore


8th IEEE Electron Devices Technology and Manufacturing
EDTM Conference 2024
Theme: Strengthening Globalization in Semiconductors
Hilton Bangalore, India, March 3rd- 6th, 2024
https://ewh.ieee.org/conf/edtm/2024/

Call for Paper: We cordially invite you to submit ORIGINAL 3-page Camera-Ready papers to the 2024 IEEE Electron Devices Technology and Manufacturing (IEEE EDTM 2024) Conference for possible presentations. Original papers are sought on any topic within the scope of IEEE EDTM 2024. There are 14 R&D Tracks for IEEE EDTM 2024, among them:

TRACK 9. Modeling and Simulation (MS)
Advances in modeling/simulation of devices, packages and processes; Technology CAD and benchmarking; Atomistic process and device simulation; Compact models for DTCO and STCO; AI/ML-augmented modelling; Material and interconnect modeling; Models for photonic devices.

Important Dates for Authors

  • Three-page camera-ready paper submission starts: August 1,2023
  • Paper submission deadline: October 15, 2023 October 30, 2023 
  • Notification for Acceptance: December 15, 2023

Accepted IEEE EDTM 2024 papers will be considered for competition for the Best Paper Award, Best Student Paper Awards and Best Poster Awards.

More details on paper submission can be found at the Paper Submission webpage.