VNWFET-based technology: from device modelling to standard cell library
Sara Mannaa, Cedric Marchand, Damien Deleruyelle, Bastien Deveautour,
Ian O’Connor, Alberto Bosio
2023 IEEE 23rd International Conference on Nanotechnology (NANO),
Jeju City, S.Korea, 2023, pp. 576-581
DOI: 10.1109/NANO58406.2023.10231288
Univ Lyon, ECL, INSA Lyon, CNRS, UCBL, CPE Lyon, INL, UMR5270, 69130 Ecully, France
Abstract: Vertical Nanowire Field Effect Transistors (VNWFETs) are an emerging technology with significant potential to reduce footprint and consequently interconnect capacitance, thereby achieving improved energy-efficiency and being naturally compatible with advanced 3D integration approaches. However, while initial estimations have focused on projections and estimations, no work has so far used a detailed compact model to attempt accurate transistor-level simulations for standard cell library characterization, thus enabling logic synthesis. In this paper, we propose a design flow to make the link from an existing (laboratory-scale) VNWFET technology and the associated compact model, to standard static logic cell design and characterization, and ultimately logic synthesis. To the best of our knowledge, this is the first work to prove the possibility of such a realistic design flow tailored to VNWFET technologies.
Fig: Through actual VNWFET fabrication setting up a design-technology co-optimization (DTCO) approach, the FVLLMONTI vision is to develop regular 3D stacked hardware layers of NNs empowering the most efficient machine translation thanks to fine-grain hardware / software co-optimisation.
Acknowledgment: This work has been founded by FVLLMONTI European Union’s Horizon 2020 research and innovation programme under grant agreement No 101016776.
