[paper] integrated PD SOI CMOS microcantilever biosensor

Yi Liu, Yuan Tian, Cong Lin, Jiahao Miao & Xiaomei Yu*

A monolithically integrated microcantilever biosensor 

based on partially depleted SOI CMOS technology

Microsystems & Nanoengineering volume 9, Article number: 60 (2023)

DOI: 10.1038/s41378-023-00534-y

* School of Integrated Circuits, Peking University, National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Beijing, 100871, China

Abstract: This paper presents a monolithically integrated aptasensor composed of a piezoresistive microcantilever array and an on-chip signal processing circuit. Twelve microcantilevers, each of them embedded with a piezoresistor, form three sensors in a Wheatstone bridge configuration. The on-chip signal processing circuit consists of a multiplexer, a chopper instrumentation amplifier, a low-pass filter, a sigma-delta analog-to-digital converter, and a serial peripheral interface. Both the microcantilever array and the on-chip signal processing circuit were fabricated on the single-crystalline silicon device layer of a silicon-on-insulator (SOI) wafer with partially depleted (PD) CMOS technology followed by three micromachining processes. The integrated microcantilever sensor makes full use of the high gauge factor of single-crystalline silicon to achieve low parasitic, latch-up, and leakage current in the PD-SOI CMOS. A measured deflection sensitivity of 0.98 × 10−6 nm−1 and an output voltage fluctuation of less than 1 μV were obtained for the integrated microcantilever. A maximum gain of 134.97 and an input offset current of only 0.623 nA were acquired for the on-chip signal processing circuit. By functionalizing the measurement microcantilevers with a biotin-avidin system method, human IgG, abrin, and staphylococcus enterotoxin B (SEB) were detected at a limit of detection (LOD) of 48 pg/mL. Moreover, multichannel detection of the three integrated microcantilever aptasensors was also verified by detecting SEB. All these experimental results indicate that the design and process of monolithically integrated microcantilevers can meet the requirements of high-sensitivity detection of biomolecules.

FIG: a) Micrograph of the fabricated integrated microcantilever sensor IC.
b) SEM photograph of the microcantilever array

Acknowledgements: This research was funded by the National Natural Science Foundation of China (Grant No. 61935001).

Open Access: this article is licensed under a Creative Commons Attribution 4.0 International License 

[paper] Schottky Barrier FET at Deep Cryogenic Temperatures

Christian Roemer^1,2, Nadine Dersch¹, Ghader Darbandy¹, Mike Schwarz¹,

Yi Han³, Qing-Tai Zhao³, Benjamın Iniguez² and Alexander Kloes¹

Compact Modeling of Schottky Barrier Field-Effect Transistors 

at Deep Cryogenic Temperatures

EUROSOI-ULIS 2023

in Tarragona (Catalonia, Spain) on May 10-12 2023

1 NanoP, TH Mittelhessen - University of Applied Sciences, Giessen, Germany
2 DEEEA, Universitat Rovira i Virgili, Tarragona, Spain
3 Peter-Grunberg-Institute (PGI 9), Forschungszentrum Julich, Germany

Abstract: In this paper, a physics-based DC compact model for Schottky barrier field-effect transistors at deep cryogenic temperatures is presented. The model uses simplified tunneling equations at temperatures of ϑ ≈ 0 K in order to calculate the field emission injection current at the device’s Schottky barriers. The compact model is also compared to and verified by measurements of ultra-thin body and buried oxide SOI Schottky barrier field-effect transistors and is able to capture the signature of resonant tunneling effects in the transfer characteristics.

FIG: Band diagram at the source side Schottky junction (left-hand side). The solid blue line is the conduction band of the channel and the blue dashed line shows the metal’s Fermi energy level. The right-hand side subplot shows the tunneling probability, with the exponential part (red line) and the total probability, including the oscillations (green line).

[paper] GaN HEMTs: Past, development, and future

Haorui Luo^ab, Wenrui Hua^a, Yongxin Guo^ab,

On large-signal modeling of GaN HEMTs: Past, development, and future

Chip, 2023, 100052

DOI: 10.1016/j.chip.2023.100052.

^a Department of Electrical and Computer Engineering, National University of Singapore

^b National University of Singapore (Suzhou) Research Institute, China

Abstract : In the past few decades, circuits based on gallium nitride high electron mobility transistor (GaN HEMT) have demonstrated exceptional potential in a wide range of high-power and high-frequency applications, such as the new generation mobile communications, object detection, consumer electronics, etc. As a critical intermediary between GaN HEMT devices and circuit-level applications, GaN HEMT large-signal models play a pivotal role in the design, application and development of GaN HEMT devices and circuits. This review provides an in-depth examination of the advancements in GaN HEMT large-signal modeling in recent decades. Detailed and comprehensive coverage of various aspects of GaN HEMT large-signal model are offered, including large-signal measurement setups, classical formulation methods, model classification, non-ideal effects, etc. In order to better serve follow-up research, this review also explores potential future directions for the development of GaN HEMT large-signal modeling.

FIG : Timeline of some typical GaN HEMT large-signal models.

Funding : This work was supported in part by the National Research Foundation (NRF) of Singapore under Grant NRF-CRP17-2017-08.

Postdoc position in GaN power devices

The POWERlab (https://powerlab.epfl.ch) at EPFL is looking for excellent and motivated candidates to work on new concepts for power electronic devices based on GaN heterostructures. The candidate will pursue novel ideas related to concepts developed in our laboratory, for example [1]. The candidate will have the opportunity to work on several aspects involved in demonstrating high-performance power devices (cleanroom fabrication, device simulation and characterization) relying on the excellent facilities in our laboratory and at EPFL. Most importantly, the candidate is encouraged to try new ideas and approaches.

Profile: The candidate is expected to have a solid theoretical background in semiconductors and experience in cleanroom fabrication of GaN electronic devices, with strong aptitude to perform experiments, explore new concepts, and communicate his/her findings in high-quality scientific publications.

What is offered: The selected candidate will be offered a fellowship with very competitive salary and excellent conditions to excel in his/her research.

How to apply: If you are interested, and have the correct profile for this position, please send your CV to elison.matioli@epfl.ch, including publication list and names of two references.

REF:

[1] L. Nela, J. Ma, C. Erine, P. Xiang, T.-H. Shen, V. Tileli, T. Wang, K. Cheng and E. Matioli, “Multi-channel nanowire devices for efficient power conversion” Nature Electronics, 4, 284–290, (2021)

[chapter] Systematic Design of Analog CMOS Circuits with Lookup Tables

Systematic Design of Analog CMOS Circuits with Lookup Tables

By Paul G. A. Jespers, Université Catholique de Louvain, Belgium

in Foundations and Trends in Integrated Circuits and Systems

Vol. 2: No. 3, pp 193-243. http://dx.doi.org/10.1561/3500000004

Publication Date: 08 May 2023

© 2023 P. G. A. Jespers*

ABSTRACT The idea underlying the methodology described in this monograph consists in the use of a set of Lookup Tables embodying device data extracted prior from systematic runs done once and for all using an advanced circuit simulator, the same as used for final design verifications. In this way, all parameters put to use during the sizing procedure incorporate not only the bearings of bias conditions and geometry, but also every second-order effect present in the simulator’s model, in particular short-channel effects. Consequently, the number of verification simulations one has to perform is not only substantially reduced, but the designer may concentrate on actual design strategies without being bothered by inconsistencies caused by poor models or inappropriate parameters.

Fig: The drain current ID versus the gate-to-source voltage VGS (plain lines) compared to the EKV best fit (+). The other lines represent the exponential and quadratic approximations.

∗The author acknowledges the kind support of Prof. Boris Murmann in writing this monograph.