Showing posts with label compact device modeling. Show all posts
Showing posts with label compact device modeling. Show all posts

Apr 8, 2019

Symposium on Schottky Barrier MOS devices

Towards neuromorphic and quantum computing applications” 
October 4, 2019, Paris (F)
organized by EDS French Chapter & Universite Paris-Sud

A symposium on Schottky Barrier MOS (SB-MOS) devices is planned for October 4th at the new Center for Nanoscience and Nanotechnology laboratory in Palaiseau, France. This is the third meeting of an enthusiastic group of Schottky barrier researchers and this year it is sponsored by LabexNanoSaclay, the IEED EDS French chapter, the Robert Bosch GmbH and Silvaco Inc.


This year the theme of the symposium is “Towards neuromorphic and quantum computing applications” organized by Dr. Laurie Calvet (C2N, Palaiseau, France), Dr. Francesca Chiodi (C2N, Palaiseau, France), Dr. Mireille Mouis (IMEP-LAHC, Grenoble INP, France) and Dr. Mike Schwarz (Robert Bosch GmbH, NanoP THM, Germany) and the staff at the Centre of Nanoscience and Nanotechnology at the Université Paris-Sud. 

The symposium starts on October 4th at 9:00 am and the following speakers have confirmed their invitations: Prof. Benjamin Iniguez (DEEEA, Universitaet Rovira I Virgili), Dr. Laurie E. Calvet (C2N, CNRS-Université Paris-Sud), Dr. Mike Schwarz (Robert Bosch GmbH, NanoP THM, Germany), Dr. David Green / Dr. Ahmed Nejim (Silvaco Inc.), Dr. John Snyder (JCAP, LLC), Dr. Francesca Chiodi (C2N, CNRS-Université Paris-Sud), Dr. François Lefloch (CEA, Grenoble), Dr. Fabrice Nemouchi (CEA, Grenoble).



Mar 14, 2019

[mos-ak] [press note] 2nd MOS-AK India Conference at IIT Hyderabad Feb. 25-27, 2019

2019 IEEE International Conference on Modeling of Systems Circuits and Devices
Organised by Joint Chapter of CAS /ED Societies, IEEE Hyderabad Section
2nd MOS-AK India Conference (IEEE Conference #45395)
Venue: IIT Hyderabad February 25-27, 2019

The MOS-AK Compact Modeling Association, a global standardization forum for semiconductor device models, held its consecutive 2nd International IEEE MOS-AK India Conference 2019 between February 25-27, 2019 at the IIT Hyderabad. The 2nd International IEEE MOS-AK India Conference 2019 is the results of join, collaborative effort. The conference organization would not be possible without direct involvements and financial support provided directly by Collage and IIT Hyderabad as well as the MOS-AK distinguished industrial sponsors including: ams semiconductors, Rhode and Schwarz, Keysight, Synergy, Synopsys, Xilinx and SCL. The MOS-AK India Conference has  also drawn attention of the Joint Chapter of the CAS and EDS Societies of the IEEE Hyderabad Section which provided direct technical program cosponsorship. The Indian Electronic Semiconductor Association (IESA) as well as Swissnex India have provide pronounced dissemination support.

Inauguration session of 2nd International IEEE MOS-AK India Conference 2019 has been chaired by Prof. Mohammed Arifuddin Sohel, MJ College Hyderabad, who welcomed all MOS-AK participants and invited prominent guests Surinder Singh, Director, SCL;  Sebasties Hug, CEO and Consul General of Swissnex;  Sumohan Chenapayya, Dean R&D, IIT Hyderabad;  V. Hanuma Sai, Director, ams semiconductors India Pvt. Ltd.;  N. Venkatesh, Chair, IEEE Hyderabad Section;  Wladek Grabinski, MOS AK (EU);  P.A. Govindacharyulu, General Co Chair, MOS AK India 2019  to open  the 2nd MOS-AK/India Conference.

The MOS-AK India Conference program has been organized as three days scientific R&D event covering recent advances into the technology TCAD simulations, compact/SPICE modeling as well as the device level analog/RF and digital IC designs. The internationally renowned academic and industrial speakers and presenters have delivered 4 tutorial lectures [1-4], 7 keynote talks [5-11], 2 plenary talks [12-13] as well as 22 regular research papers. The MOS-AK Association is an open research forum adequately supporting all R&D activities. An open panel discussion was organized to review challenges and opportunities for women in engineering (WIE) [14]. The MOS-AK speakers shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in response to the dynamically evolving semiconductor industry and academic R&D efforts. The event featured advanced technical presentations covering compact model development, implementation, and deployment. Presented original unpublished works in all the topics related to the compact/SPICE modeling and its Verilog-A standardization will be submitted for further publication. The conference proceedings will be submitted to IEEE Explore. Best MOS-AK/India papers has been selected and awarded: Gold leaf [15], Silver leaf [16] and Bronze leaf [17] certificates, accordingly. Highest ranked paper authors from regular submission will be invited to extend their R&D contribution in the form of a book chapters in a book titled "Compact Modeling: Technology, Devices, IC Design" by River Publishers, the technical program promoter of MOS-AK/India 2019 Conference. These R&D topics have also received attention of local media and press [18-21]. For more information about each of the R&D contributions, go online to 2nd MOS-AK/India Conference
Photo: All the MOS-AK/India Conference participants at IIT Hyderabad
The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses arround the globe thru 2019 year, including:
About MOS-AK Association:
MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common information exchange system among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools including FOSS for the compact/SPICE models development, validation/implementation and distribution. For more information please visit: mos-ak.org

Tutorials:
[1] Dr. Charvaka Duvvury iT2 Technologies (USA) ESD on-chip protection design 
[2] Dr. Wladek Grabinski MOS-AK (EU) Verilog-A Standardization
[3] Weronika Zubrzycka, AGH, (PL) Radiation effect and Radiation hardening in devices 
[4] Prof. Roberto Murphy, INOE (MX) Characterization of Semiconductor Devices in the High Frequency Regime
Keynote Talks: 
[5] Prof. Yogesh Singh Chauhan, IIT Kanpur (IN) Negative Capacitance Transistors - Modeling, Simulation and Processor Performance
[6] Dr. Surinder Singh, Semiconductor Labs, Chandigarh  (IN), Chandigarh Research at SCL
[7] Weronika Zubrazycka, AGH, (PL) Radiation Effects on Circuits for Space and High-Energy Physics Applications - A case study 
[8] Madabusi Govindrajan, GLOBALFOUNDRIES, Bangalore (IN)  Challenges for RF modeling in the connected era 
[9] Dr. Usha Gogineni, Maxim Semiconductors (IN)  Compact Models for Analog and Mixed Signal Design 
[10] Prof. Santanu Mahapatra, IISc, Bangalore (IN)  Atom-to-Circuit modeling technique for emerging nanomaterial based MOSFETs 
[11] Prof. Gilson Wirth, UFRGS (BR) (Webinar) Charge Trapping Phenomena in MOSFETS: From Noise to Bias Temperature Instability 
Plenary Talks: 
[12] Prof. Jaijeet Roychowdhury, UC, Berkeley, USA Well-Posed Compact Modeling 
[13] Dr. Ehrenfried Seebacher, ams (A) Compact Modeling for Industrial Applications 
Panel Discussion: 
[14] Dr. G. Uma Devi, Director, NRSC, (IN): Challenges and opportunities for Women in Engineering (WIE). 
Best papers awards:
[15] Chithra and Nagendra Krishnapura, "Modeling Techniques for Faster Verification of a Time to Digital Converter System-on-Chip Design"
[16] Mohit Ganeriwala, Enrique Marin, Francisco Ruiz and Nihar Mohapatra," A Compact Charge and Surface Potential Model for III-V Quadruple-Gate FETs With Square Geometry"
[17] Suprava Dey, Tara Prasanna Dash, Chinmay Kumar Maiti, Jhansirani Jena, Eleena Mohapatra and Sanghamitra Das," Performance Evaluation of Gate-All-Around Si Nanowire Transistors with SiGe Strain engineering"
Headlines: 
[18] "Swiss interest in India's energy and tech fields" Date: Feb. 27,2019 Publication: The Hindu Edition: Hyderabad
[19] "IIT Hyderabad hosts MOS-AK India 2019 International Conference on Modeling of Systems Circuits and Devices" India Education diary  Edition: Online: Prof. Sushmee Badhulika 
[19] Indo-Swiss collaboration needed in education" Date: Feb. 27,2019 Publication: The New Indian express, Edition: Hyderabad
[20] "Switzerland looking forward to stronger ties with Telangana" Feb. 27,2019   Publication: Telangana Today, Edition:  Hyderabad
[21] "IIT Hyderabad hosts MOS-AK India 2019 International Conference on Modeling of Systems Circuits and Devices " Date: Feb. 27,2019 Publication: Andhra Jyothi Edition: Hyderabad pp:3

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Jan 9, 2019

Compact Transcapacitance Model for Short Channel DG FinFETs

(Proceedings of the Int. Conference on Microwave and THz Technologies and Wireless Comm.)
Ashkhen Yesayan
Institute of Radiophysics and Electronics
Alikhanian Brothers str. 1, 0203 Ashtarak, Armenia
Received 15 November 2018

Abstract: A compact capacitance model is developed accounting for small-geometry effects in FinFETs. While decreasing the channel length, the transcapacitance model becomes very sensitive to all short channel effects, both in moderate and strong inversion regimes. In addition, for short channel devices, we need to take into account the inter-electrode capacitive coupling in the subthreshold regime, which is not significant for long channel devices. The quantum mechanical effects, which are very significant for thin Fins, are included in the model. The effect of mobility degradation on C-V characteristics is also demonstrated. The model was validated with numerical 3D Atlas simulations and a good accuracy of the model has been demonstrated in all operating regimes.

References:
[1] Tech. rep., International technology roadmap for semiconductor (ITRS). 2009.
[2] J.-M. Sallese, F. Krummenacher, F. Pregaldiny, C. Lallement, A. Roy, C. Enz, A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism, Solid-State Electron, vol. 49 no. 3, pp. 485–489. 2005.
[3] A Yesayan, F Prégaldiny, N Chevillon, C Lallement, JM Sallese, Physics-based compact model for ultra-scaled FinFETs, Solid-State Electronics, vol. 62, no1, pp. 165-173, 2011.
[4] Liang X, Taur Y., A 2-D analytical solution for SCEs in DG MOSFETs. IEEE Trans Electron Dev 2004;51(9):1385–91.
[5] Ward D, Dutton R. ,A charge-oriented model for MOS transistor capacitances. IEEE J Solid-State Circ, 1978;13(5):703–8.
[6] Tang M. Etude et modélisation compacte du transistor FinFET. Ph.D. Thesis, University of Strasbourg; December 2009.
[7] Borli H, Vinkenes K, Fjeldly T., Physics-based capacitance modeling of short-channel double-gate MOSFETs. Phys Status Solidi (c) 2008;5(12):3643–6.
[8] Arora N., MOSFET models for VLSI circuit simulation. New York: Theory and Practice, Springer-Verlag; 1993, ISBN:3-211-82395-6

Source:

Dec 19, 2018

Compact Transistor Modeling with Radiation Effects

A Radiation-Hardened Instrumentation Amplifier for Sensor Readout Integrated Circuits in Nuclear Fusion Applications

Kyungsoo Jeong 1, Duckhoon Ro 1, Gwanho Lee 2  Myounggon Kang 2* and Hyung-Min Lee 1*

1 School of Electrical Engineering, Korea University, Seoul 02841, Korea; jksoo2002@korea.ac.kr (K.J.); roduckhoon@korea.ac.kr (D.R.)
2 Department of Electronics Engineering, Korea National University of Transportation, Chungju 27469, Korea; ghlee@ut.ac.kr

* Correspondence: mgkang@ut.ac.kr (M.K.); hyungmin@korea.ac.kr (H.-M.L.); Tel.: +82-43-841-5164 (M.K.); +82-2-3290-3219 (H.-M.L.)

Abstract: A nuclear fusion reactor requires a radiation-hardened sensor readout integrated circuit (IC), whose operation should be tolerant against harsh radiation effects up to MGy or higher. This paper proposes radiation-hardening circuit design techniques for an instrumentation amplifier (IA), which is one of the most sensitive circuits in the sensor readout IC. The paper studied design considerations for choosing the IA topology for radiation environments and proposes a radiation-hardened IA structure with total-ionizing-dose (TID) effect monitoring and adaptive reference control functions. The radiation-hardened performance of the proposed IA was verified through model-based circuit simulations by using compact transistor models that reflected the TID effects into complementary metal–oxide–semiconductor (CMOS) parameters. The proposed IA was designed with the 65 nm standard CMOS process and provides adjustable voltage gain between 3 and 15, bandwidth up to 400 kHz, and power consumption of 34.6 µW, while maintaining a stable performance over TID effects up to 1 MGy.

Electronics 2018, 7, 429; doi:10.3390/electronics7120429
Received: 22 November 2018; Accepted: 9 December 2018; Published: 12 December 2018

Apr 26, 2018

Symposium on Schottky Barrier MOS Devices 2018

"devil of savior"
It is the 40th anniversary of Institut für Halbleitertechnik und Nanoelektronik (IHTN) of the TU Darmstadt, Germany. In addition to many activities in September, a small symposium on Schottky Barrier MOS (SB-MOS) devices is planned for August 7th in Darmstadt. This is the second meeting of an enthusiastic group of Schottky barrier researchers and this year it is sponsored by the EDS German chapter and hosted by the IHTN of TU Darmstadt.
This year the symposium is organized by Dr. Tillmann Krauss, Dr. Udo E. Schwalke, Dr. Mike Schwarz and the staff of the TU Darmstadt. The symposium starts at 11:00 am in the lecture hall at the ITHN TU Darmstadt. 
The following agenda is planned:






AGENDA:

11:00 – 11:15 Welcome and introduction by Prof. Schwalke
11:15 – 11:30 “Wrap-Up of Schottky Barrier Simulation Methodologies”, Dr. Mike Schwarz (Robert Bosch GmbH, NanoP THM) (15mins)
11:30 – 12:00 “DC/AC compact modeling of Tunnel-FETs”, Prof. Alexander Kloes (NanoP THM) (30mins)
12:00 – 12:30 “Benefits of Schottky Barrier vs. Conventional Doped Source/Drain MOS devices”, Dr. John Snyder (JCap, LLC) (30mins)
12:30 – 13:30 “Lunch”
13:30 – 14:00 “Nanowire Schottky devices”, Dr. Walter Weber (TU Dresden) (30mins)
14:00 – 14:30 “Nanoelectronics: From Silicon to Carbon”, Prof. Udo Schwalke (TU Darmstadt) (30mins)
14:30 – 14:45 “Coffee Break”
14:45 – 15:15 “Transfer-free fabrication of nanocrystalline graphene field-effect sensors”, Dennis Noll (TU Darmstadt) (30mins)
15:15 – 15:45 “Modeling of neuromorphic devices”, Dr. Laurie E. Calvet (Université Paris-Sud) (30mins)

Attendees are welcome to attend the symposium. Further information are present at http://www.iht.tu-darmstadt.de/ihtn_institute/

Feb 28, 2018

[paper] Compact electro-thermal modeling of a SiC MOSFET power module under short-circuit conditions

Proceedings of 43rd Annual Conference of the IEEE Industrial Electronics Society
IECON 2017
Lorenzo Ceccarelli, Paula Diaz Reigosa, Amir Sajjad Bahman, Francesco Iannuzzo,
Frede Blaabjerg
Center of Reliable Power Electronics, Department of Energy Technology Aalborg University,
Pontoppidanstræde 101
9220 Aalborg, Denmark 

ABSTRACT: A novel physics-based, electro-thermal model which is capable of estimating accurately the short-circuit behavior and thermal instabilities of silicon carbide MOSFET multi-chip power modules is proposed in this paper. The model has been implemented in PSpice and describes the internal structure of the module, including stray elements in the multi-chip layout, self-heating effect, drain leakage current and threshold voltage mismatch. A lumped-parameter thermal network is extracted in order to estimate the internal temperature of the chips. The case study is a half-bridge power module from CREE with 1.2 kV breakdown voltage and about 300 A rated current. The short-circuit behavior of the module is investigated experimentally through a non-destructive test setup and the model is validated. The estimation of overcurrent and temperature distribution among the chips can provide useful information for the reliability assessment and fault-mode analysis of a new-generation SiC high-power modules [read more...]

Fig.: SiC MOSFET model structure. 

Feb 21, 2018

[paper] Low Power Low Jitter 0.18 CMOS Ring VCO Design with Strategy Based on EKV3.0 Model

Amine AYED and Hamadi GHARIANI
LETI Laboratory-ENIS
Sfax, Tunisia
IJACSA Vol. 8, No. 12, 2017

Abstract—In this paper, the design of micro-power CMOS ring VCO with minimum jitter intended for a concept of frequency synthesizer in biotelemetry systems is studied. A design procedure implemented in MATLAB is described for a circuit realization with TSMC 0.18μm CMOS technology. This conventional design methodology based on EKV3.0 model is clearly suited to the challenges of analog circuits design with reduced channel width. Measures realized with ADS confirmed methodology capability to circuit sizing respecting the specifications of application. The designed ring VCO operates at a central frequency of 433MHz in ISM band with an amplitude of oscillation equal to 500 mV. The integration area was intrinsic (without buffers and without external capacitances). The simulated phase noise is about -108 dBc/Hz at 1MHz, the value of rms jitter is 44.8 ps and the power consumption of the designed VCO is 6.37 mW @ 433 MHz [read more...]

Fig.: Eye diagram for a VCO output @ 433MHz


Oct 24, 2017

Cryogenic characterization of CMOS technologies

A. Beckers, F. Jazaeri, A. Ruffino, C. Bruschini, A. Baschirotto and C. Enz
Cryogenic characterization of 28 nm bulk CMOS technology for quantum computing
47th ESSDERC, Leuven, Belgium, 2017, pp. 62-65.

Abstract: This paper presents the first experimental investigation and physical discussion of the cryogenic behavior of a commercial 28 nm bulk CMOS technology. Here we extract the fundamental physical parameters of this technology at 300,77 and 4.2 K based on DC measurement results. The extracted values are then used to demonstrate the impact of cryogenic temperatures on the essential analog design parameters. We find that the simplified charge-based EKV model can accurately predict the cryogenic behavior. This represents a main step towards the design of analog/RF circuits integrated in an advanced bulk CMOS process and operating at cryogenic temperature for quantum computing control systems [read more...doi: 10.1109/ESSDERC.2017.8066592



R. M. Incandela, L. Song, H. A. R. Homulle, F. Sebastiano, E. Charbon and A. Vladimirescu
Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures
47th ESSDERC, Leuven, Belgium, 2017, pp. 58-61.

Abstract: The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations and measurements for DC and time-domain at 4 K and, for the first time, at 100 mK [read more...doi: 10.1109/ESSDERC.2017.8066591

Sep 12, 2017

[book] Systematic Design of Analog CMOS Circuits

Paul G. A. Jespers, Boris Murmann
Cambridge University Press; 31 Oct 2017; 342pp

Discover a fresh approach to efficient and insight-driven analog integrated circuit design in nanoscale-CMOS with this hands-on guide. Expert authors present a sizing methodology that employs SPICE-generated lookup tables, enabling close agreement between hand analysis and simulation. This enables the exploration of analog circuit tradeoffs using the gm/ID ratio as a central variable in script-based design flows, and eliminates time-consuming iterations in a circuit simulator. Supported by downloadable MATLAB code, and including over forty detailed worked examples, this book will provide professional analog circuit designers, researchers, and graduate students with the theoretical know-how and practical tools needed to acquire a systematic and re-use oriented design style for analog integrated circuits in modern CMOS.

Aug 30, 2017

[paper] Surface Potential Equation for Low Effective Mass Channel Common Double-Gate MOSFET

Ananda Sankar Chakraborty and Santanu Mahapatra, Senior Member, IEEE
in IEEE Transactions on Electron Devices
vol. 64, no. 4, pp. 1519-1527, April 2017
doi: 10.1109/TED.2017.2661798

Abstract: Formulation of accurate yet computationally efficient surface potential equation (SPE) is the fundamental step toward developing compact models for low effective mass channel quantum well MOSFETs. In this paper, we propose a new SPE for such devices considering multisubband electron occupancy and oxide thickness asymmetry. Unlike the previous attempts, here, we adopt purely physical modeling approaches (such as without mixing the solutions from finite and infinite potential wells or using any empirical model parameter), while preserving the mathematical complexity almost at the same level. Gate capacitances calculated from the proposed SPE are shown to be in good agreement with numerical device simulation for wide range of channel thickness, effective mass, oxide thickness asymmetry, and bias voltages [read more...]
FIG: Total gate capacitance per unit width Cgg (Vg) for 7-nm-thick device with 100% asymmetry in front and back oxide thicknesses. nmax = 2. Line = model. Symbol = TCAD

Aug 29, 2017

VALint: the NEEDS Verilog-A Checker

By Xufeng Wang1, Geoffrey Coram2, Colin McAndrew3
1. Purdue University 2. Analog Devices, Inc. 3. Freescale Semiconductor
Version 1.0.0 - published on 31 Mar 2017
doi:10.4231/D3HX15S0V

Abstract: VALint is the NEEDS created, automatic Verilog-A code checker. Its purpose is to check the quality of the Verilog-A code and provide the author feedback if bad practices, common mistakes, pitfalls, or inefficiencies are found. This VALint is published as a standalone tool for the compact model community. It is also built-in as an integrated part of the NEEDS publishing platform [read more...]


Aug 28, 2017

[paper] Nanoscale MOSFET Modeling

 Nanoscale MOSFET Modeling: 
Part 1: The Simplified EKV Model for the Design of Low-Power Analog Circuits
C. Enz, F. Chicco and A. Pezzotta
in IEEE Solid-State Circuits Magazine, vol. 9, no. 3, pp. 26-35, Summer 2017
doi: 10.1109/MSSC.2017.2712318

Abstract: This article presents the simplified charge-based Enz-Krummenacher-Vittoz (EKV) [11] metal-oxide-semiconductor field-effect transistor (MOSFET) model and shows that it can be used for advanced complementary metal-oxide-semiconductor (CMOS) processes despite its very few parameters. The concept of an inversion coefficient (IC) is first introduced as an essential design parameter that replaces the overdrive voltage VG-VT0 and spans the entire range of operating points from weak via moderate to strong inversion (SI), including the effect of velocity saturation (VS). The simplified model in saturation is then presented and validated for different 40- and 28-nm bulk CMOS processes. A very simple expression of the normalized transconductance in saturation, valid from weak to SI and requiring only the VS parameter mc, is described. The normalized transconductance efficiency Gm/ID, which is a key figure-of-merit (FoM) for the design of low-power analog circuits, is then derived as a function of IC including the effect of VS. It is then successfully validated from weak to SI with data measured on a 40-nm and two 28-nm bulk CMOS processes. It is then shown that the normalized output conductance Gds/ID follows a similar dependence with IC than the normalized Gm/ID characteristic but with different parameters accounting for drain induced barrier lowering (DIBL). The methodology for extracting the few parameters from the measured ID-VG and ID-VD characteristics is then detailed. Finally, it is shown that the simplified EKV model can also be used for a fully depleted silicon on insulator (FDSOI) and Fin-FET 28-nm processes [read more...]

FIG: The simplified EKV model applied to a 28-nm FDSOI CMOS process: 
Gm n UT / ID versus IC for three different transistor channel lengths

References
[1] A. Bahai, “Ultra-low energy systems: Analog to information,” in Proc. European Solid-State Circ. Conf., Sept. 2016, pp. 3–6.
[2] D. Binkley, Tradeoffs and Optimization in Analog CMOS Design. Hoboken, NJ: Wiley, 2008.
[3] W. Sansen, Analog Design Essentials. New York: Springer-Verlag, 2006.
[4] A. Mangla, M. A. Chalkiadaki, F. Fadhuile, T. Taris, Y. Deval, and C. C. Enz, “Design methodology for ultra low-power analog circuits using next generation BSIM6 MOSFET compact model,” Microelectr. J., vol. 44, no. 7, pp. 570–575, July 2013.
[5] Y. S. Chauhan, S. Venugopalan, M. A. Chalkiadaki, M. A. U. Karim, H. Agarwal, S. Khandelwal, N. Paydavosi, J. P. Duarte, C. C. Enz, A. M. Niknejad, and C. Hu, “BSIM6: Analog and RF compact model for bulk MOSFET,” IEEE Trans. Electron Dev., vol. 61, no. 2, pp. 234–244, Feb. 2014.
[6] C. Enz, M. A. Chalkiadaki, and A. Mangla, “Low-power analog/RF circuit design based on the inversion coefficient,” in Proc. European Solid-State Circ. Conf., Sept. 2015, pp. 202–208.
[7] C. Enz and A. Pezzotta, “Nanoscale MOSFET modeling for the design of low-power analog and RF circuits,” in Proc. Int. Conf. MIXDES, June 2016, pp. 21–26.
[8] W. Sansen, “Analog CMOS from 5 micrometer to 5 nanometer,” in Proc. IEEE Int. Solid State Circuits Conf. Dig. Tech. Papers, Feb. 2015, pp. 1–6.
[9] W. Sansen, “Analog design procedures for channel lengths down to 20 nm,” in Proc. IEEE 20th Int. Conf. Electronics, Circuits, and Systems, Dec. 2013, pp. 337–340.
[10] C. C. Enz and E. A. Vittoz, Charge-Based MOS Transistor Modeling - The EKV Model for Low-Power and RF IC Design. Hoboken, NJ: Wiley, 2006.
[11] C. C. Enz, F. Krummenacher, and E. A. Vittoz, “An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications,” Analog Integr. Circuits Signal Process. J., vol. 8, pp. 83–114, July 1995.
[12] P. Heim, S. R. Schultz, and M. A. Jabri, “Technology-independent biasing technique for CMOS analogue micropower implementations of neural networks,” in Proc. Sixth Australian Conf. Neural Networks, Sydney, Australia, 1995, pp. 9–12.
[13] C. C. Enz and E. A. Vittoz, “CMOS low-power analog circuit design,” in EmergingTechnologies: Designing Low Power Digital Systems, R. Cavin and W. Liu, Eds. Piscataway, NJ: IEEE, 1996, pp. 79–133.
[14] E. Vittoz and J. Fellrath, “CMOS analog integrated circuits based on weak inversion operations,” IEEE J. Solid-State Circuits, vol. 12, no. 3, pp. 224–231, June 1977.
[15] A. Mangla, C. C. Enz, and J. M. Sallese, “Figure-of-merit for optimizing the current efficiency of low-power RF circuits,” in Proc. Int. Conf. Mixed Design Integrated Circuits and Systems, June 2011, pp. 85–89.
[16] A. Mangla, “Modeling nanoscale quasi-ballistic MOS transistors,” Ph.D. dissertation, EPFL, Switzerland, Dissertation No. 6385, 2014.
[17] R. R. Troutman and A. G. Fortino, “Simple model for threshold voltage in a short- channel IGFET,” IEEE Trans. Electron. Dev., vol. 24, no. 10, pp. 1266–1268, Oct. 1977.
[18] N. Arora, MOSFET Models for VLSI Circuit Simulation. New York: Springer-Verlag, 1993.
[19] Z. H. Liu, C. Hu, J. H. Huang, T. Y. Chan, M. C. Jeng, P. K. Ko, and Y. C. Cheng, “Threshold voltage model for deep submicrometer MOSFETs,” IEEE Trans. Electron Dev., vol. 40, no. 1, pp. 86–95, Jan. 1993.
[20] M. A. Chalkiadaki, “Characterization and modeling of nanoscale MOSFET for ultra-low power RF IC design,” Ph.D. dissertation, EPFL, Switzerland, Dissertation No. 7030, 2016.

Aug 18, 2017

[paper] Improvements to a compact MOSFET model for design by hand

Improvements to a compact MOSFET model for design by hand
A. de Jesus Costa, F. Martins Cardoso, E. Pinto Santana and A. I. Araújo Cunha
15th IEEE NEWCAS
Strasbourg, France, 2017, pp. 225-228
doi: 10.1109/NEWCAS.2017.8010146

Abstract: In this work, an improved version of the basic structure of a compact MOSFET model and the respective parameters extraction methodology are proposed. The aim of this approach is to increase accuracy in hand calculations for analog circuit design without significantly increasing its complexity. The influences of both inversion level and channel length are considered in the modeling of a few features such as mobility, threshold voltage and onset of saturation. Simple design examples of current sinks and sources are accomplished to compare the basic and the improved models [read more...]

Aug 7, 2017

ICCDCS 2017

Tenth International Caribbean Conference on Devices, Circuits and Systems (ICCDCS 2017)

June 5-7 2017, Cozumel, México
08:00 to 9:00RegistrationRegistrationRegistration 
08:45 to 9:00Opening Ceremony
09:00 to 10:00Key Note 1: "Adaptive Heterogenous Multi-Core Technologies- Intelligent, Interconnected and Integrated Cyber-Physical Systems (I3CPS)"Jürgen BeckerKey Note 3: "The Life and Times of Eugeni García"Benjamín ÍñiguezKey Note 6: "On the Extraction Methods for MOSFET Series Resistance and Mobility Degradation using a Single Test Device",Adelmo Ortiz Conde
10:00 to 10:30BreakBreakBreak
10:30 to 12:30Session 1Session 3Session 5
10:30 to 10:50"Model Based Photopic Electroretinogram Source Separation: A Multiresolution Analysis Approach"Prashanth Chetlur Adithya, Alaql Abdulrahman, Radouil Tzekov, Ravi Sankar and Wilfrido Moreno"A Programmable CMOS Voltage Controlled Ring Oscillator for Radio-Frequency Diathermy On-chip Circuit"Antonio Corres- Matamoros, Esteban Martinez-Guerrero and Jose E. Rayas-Sanchez"Health Index Assessment for Power Transformers with Thermal Upgraded Paper up to 230kV, Using Fuzzy Inference. Part II: A Sensibility Analysis"Diego Chacón, Juan Pablo Lata and Ricardo Medina
10:50 to 11:10"Analytical Model Parameter Determination for Microwave On-Chip Inductors up to the Second Resonant Frequency"José Valdés Rayón, Reydezel Torres and Roberto Murphy"A logarithmic CMOS image sensor with wide output voltage swing range"Fernando Campos, Mário Bordon, Marcelo Silva and Jacobus Swart"Implementation Model Using a Hippocratic Protocol in Mobile Terminals with NFC Technology"Carlos Kowalevicz, Jose Pirrone Puma and Monica Huerta
11:10 to 11:30"Energy Consumption Improvement based on Distance Adaptive Modulation in Optical Elastic Network"Sabi Bandiri, Rafael Braga, Tales Pimenta and Danilo Spadoti"Improving Magnitude Response in Two-Stage Corrector Comb Structure"Gordana Jovanovic Dolecek and Lyda Herrera Sepulveda"Internet of Things as an Attack Vector to Critical Infrastructures of Cities"Pablo Leonidas Gallegos-Segovia, Jack Fernando M. Larios-Rosillo and Erwin Jairo Sacoto-Cabrera
11:30 to 11:50"Switching Region Analysis for SOTB Technology"Carlos Cortes Torres, Nobuyuki Yamasaki and Hideharu Amano"Analysis of the influence of the buffer layer in the characteristic impedance of electro-optic modulators"Ana Gabriela Correa Mena, Luis Alejandro González Mondragón, Leidy Johana Quinteros Rodríguez, José Valdés Rayón and Ignacio Enrique Zaldívar Huerta"Sensors for Parkinson's Disease Evaluation"Raquel Torres, Monica Huerta, Ricardo Gonzalez, Roger Clotet and Juan Pablo Bermeo
11:50 to 12:10"Scalable Models to Represent the Via-Pad Capacitance and Via-Traces Inductance in Multilayer PCB High-Speed Interconnects"Abraham Isidoro Muñoz, Miguel Angel Tlaxcalteco Matus, Reydezel Torres Torres and Gaudencio Hernandez Sosa"Impact of neglecting the metal losses on the extraction of the relative permittivity from PCB transmission line measurements"Erika Yazmin Teran Bahena and Reydezel Torres Torres"QoS Evaluation of VPN in a Raspberry Pi devices over Wireless Network"Luis Caldas, Juan Jara and Mónica Huerta
12:10 to 12:30"Implementation of a Reconfigurable Neural Network in FPGA"Janaina Oliveira, Robson Moreno, Odilon Dutra and Tales Pimenta"Reconfigurable FIR Filter Coefficient Optimization in Post-Silicon Validation to Improve Eye Diagram for Optical Interconnects",Ismael Duron-Rosales, Francisco E. Rangel-Patino, Jose E. Rayas-Sanchez, Jose L. Chavez-Hurtado and Nagib Hakim"A Proposed Digital Predistorter Based on NLMS and PSO Algorithms"Omar Alngar, Walid El-Deeb and El-Sayed El-Rabaie
12:30 to 15:00LunchLunchClosing remarks
15:00 to 16:00Key Note 2: "Following the Path of 3D Integration"Malgorzata Chrzanowska-JeskeKey Note 4: “Modeling and Verification of Heterogeneous Systems”Filipe Vinci
16:00 to 16:15BreakPoster Introduction*
16:15 to 17:55Session 2Session 4
16:15 to 16:35"MRAM control Transistor Resilience against Heavy-Ion Impacts", Walter Enrique Calienes Bartra, Raphael Brum, Guilherme Flach and Ricardo ReisBreak w/poster session (16:15 to 17:00)
16:35 to 16:55"A Charge-controlled Memristor Model for Image Edge Detection with a Memristive Grid"Arturo Sarmiento and Yojanes Rodríguez-Velásquez
16:55 to 17:15"Characterization and modelling of Ag/TiO2/ITO devices exhibiting bipolar memristive properties", Jesús Jiménez-León, Arturo Sarmiento, Carlos De La Cruz Blas and Cristina Gomez-Polo
17:15 to 17:35"Assessing the accuracy of the open, short and open-short de-embedding methods for on-chip transmission line s-parameters measurements"Juan Garcia Santos and Reydezel TorresKey Note 5: (17:00 to 18:00) "Innovation by ASIC design and emerging substream markets"Jacobus Swart
17:35 to 17:55"Evaluation of Interconnects Based on Electromigration Criteria and Circuit Performance"Rafael Nunes, Roberto Orio and Jacobus Swart
19:00Welcome Cocktail
19:30Conference Banquet
Poster Session:
"Differentiated synchronization plus FHIR a solution for EMR's Ecosystem", Roger Clotet, Emilio Hernández and Monica Karel Huerta
"Design and Validation of a Portable Radio-Frequency Diathermy Prototype", Antonio Corres-Matamoros, Esteban Martinez-Guerrero and Jose E. Rayas-Sanchez
"Stimulating social interaction among elderly people through sporadic social networks", Jorge Osmani Ordoñez-Ordoñez, Jack Fernando Bravo-Torres, Oscar David Sari-Villa, Esteban Fernando Ordoñez-Morales, Martín López-Nores and Yolanda Blanco-Fernández
"Sensing Climatic Variables in a Orchid Greenhouse", Luis Fernandez, Mónica Huerta, Giovanni Sagbay, Roger Clotet and Angel Soto
"Low cost system for monitoring physiological signals using FPGA and Android Tablet", J. Bucheli, D. Rivas, J. Gavilema, D. Mullo, J. L. Carrillo, M. Huerta

Jun 14, 2017

[paper] Well-Posed Device Models for Electrical Circuit Simulation

Well-Posed Device Models for Electrical CircuitSimulation
A Guide to Creating Robust Device Models
A. Gokcen Mahmutoglu, Tianshi Wang, Archit Gupta and Jaijeet Roychowdhury
March 25, 2017

Synopsis: This document provides guidelines for creating computational device models that work well in simulation. We build our discussion around the mathematical notion of “well-posedness”. We show that the requirements for a model to be well-posed stem from the internal working mechanisms of simulators. Therefore, our main aim is to provide insight into the numerical procedures used by simulators in order to help model developers avoid ill-posedness issues. We start our discussion with an example that shows how an ill-posed Verilog-A model can produce different simulation results in different simulators. We then provide a step-by-step simulation case study. In this case study, we illustrate the role of device models in simulations by examining the steps a simulator goes through, from taking a netlist as input to producing a simulation result as output. Finally, we distill our discussion in a functional definition of a well-posed model. As an extension to our theoretical discussion, we also provide practical guidelines that should be followed by Verilog-A models in order to avoid ill-posedness issues [read more...]

This document is published as a part of the Nano-Engineered Electronic Device Simulation (NEEDS) initiative. NEEDS is an NSF-funded initiative whose charter includes the development of tools and techniques for the production of high-quality device models1:
NEEDS has a vision for a new era of electronics that couples the power of billion-transistor CMOS technology with the new capabilities of emerging nano-devices and a charter to create high-quality models and a complete development environment that enables a community of compact model developers.

NEEDS Team: Purdue, MIT, UC Berkeley, and Stanford.”

1For more information about NEEDS please visit https://nanohub.org/groups/needs/.

Dec 12, 2016

[Fellowship] Physics Based Modeling Simulation and Electrical Characterization

Physics Based Modeling Simulation and Electrical Characterization 
of Quantum Effects in Multigate MOSFETs
[DRDO Fellowship]

Dr. Vimala Palanichamy is looking for Junior Research Fellowship (INR 25000 Stipend per Month) for this project funded by Defense Research and Development Organization (DRDO), Government of India. Please refer below advertisement for applying for Junior Research Fellowship for working on the project: 

Oct 25, 2016

[ESSDERC Paper] Compact model for variability of low frequency noise due to number fluctuation effect

Compact model for variability of low frequency noise due to number fluctuation effect
N. Mavredakis and M. Bucher
2016 46th European Solid-State Device Research Conference (ESSDERC)
Lausanne, Switzerland, 2016, pp. 464-467

Abstract: Variability of low frequency noise (LFN) in MOSFETs is both geometry- and bias-dependent. RTS noise prevails in smaller devices where noise deviation is mostly area-dominated. As device dimensions increase, operating conditions determine noise variability maximizing it in weak inversion and increasing it with drain voltage. This dependence is shown to be directly related with fundamental carrier number fluctuation effect. A new bias- and area-dependent, physics-based, compact model for 1/f noise variability is proposed. The model exploits the log-normal behavior of LFN. The model is shown to give consistent results for average noise, variance, and standard deviation, covering bias-dependence and scaling over a large range of geometry.

Keywords: compact models, Low-frequency noise, MOSFET, Reactive power, Semiconductor device modeling, Shape, Standards, MOSFET, low frequency noise, noise variability

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7599686&isnumber=7598672

Jul 20, 2016

Leti-UTSOI Compact Model

The Leti-UTSOI compact model is the only one to be totally dedicated to the FDSOI technology. In its recent version, the Leti-UTSOI model has reached its maturity. In collaboration with STM, its robustness was validated by successfully complying with the full test suite recommended by the CMC. The Leti-UTSOI model is now currently used at STM in the IC design division. It is now available in an industrial design-kit. The documentation and some model cards (typical) are available below:
The Leti-UTSOI Verilog-A code can also be obtained contacting LETI UTSOI Developers.


Leti-UTSOI Compact Model

The Leti-UTSOI compact model is the only one to be totally dedicated to the FDSOI technology. In its recent version, the Leti-UTSOI model has reached its maturity. In collaboration with STM, its robustness was validated by successfully complying with the full test suite recommended by the CMC. The Leti-UTSOI model is now currently used at STM in the IC design division. It is now available in an industrial design-kit. The documentation and some model cards (typical) are available below:
The Leti-UTSOI Verilog-A code can also be obtained contacting LETI UTSOI Developers.


LETI Compact Modeling Links

LETI compact modeling links points to the Workshops and Conferences:

MOS-AK (Modeling of Systems and Parameter Extraction Working Group)
S3S (IEEE SOI-3D Subthreshold Microelectronics Technology Unified Conference)

IEDM (IEEE International Electron Devices Meeting)
VLSI  (29th International Conference on VLSI Design)
SISPAD (Simulation of Semiconductor Processes and Devices)